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The impact of negative capacitance (NC) of the ferroelectric materials in controlling the direct source to drain tunneling (DSDT) in ultra-short channel FETs is presented in this paper. Besides, an analytical model is developed by solving 2-D Poisson’s equation incorporating the degeneracy of source/drain (S/D) regions. We demonstrate that in NC gate stack based Si channel FETs (NC-FETs), the scaling limit can be pushed down to 7 nm gate length, without using effective mass engineering and alternate channel materials. However, under severe subthreshold tunneling circumstances, we find that as the % content of tunneling current rises above the value of 50% in the net current, the subthreshold slope (SS) ceases to improve with the higher ferroelectric thickness. The rigorous analysis of DSDT-Negative drain induced barrier lowering (NDIBL) and impact of the S/D doping over DSDT is also incorporated in the paper. It is found that DSDT decreases drastically in the NCFET compared to baseline FETs due to the NC effect. Hence, using NC effect, transistor can be scaled down to 7 nm physical gate length with SS 80 mV/dec and I OFF 70 nA / μ m compared to 173 mV/dec and 1.5 × 10 6 nA / μ m, respectively for the baseline FET at the same gate length.

Halo implanted MOSFETs exhibit anomalous behavior in drain current power spectral density ( S ID ) of flicker noise (1/f) with the variation in drain voltage, but this behavior cannot be captured by existing 1/f models. To identify the reasons for this abnormal behavior of 1/f noise, we have performed experimentally calibrated technology computer-aided design (TCAD) simulations. We find that this anomalous behavior comes from the drain-side halo region, and it has complex dependence on the bias and geometry. We propose a sub-circuit model for 1 / f noise that successfully captures the anomalous behavior of S ID with the drain bias. This model calculates the individual contributions and the impact of different device regions, such as the source side halo, channel, and drain side halo, on the overall noise of the device. The proposed model is in good agreement with the experimentally calibrated TCAD simulations for different geometries, biases, and temperatures. The proposed model is also validated with the measurement data.

We present a surface potential based analytical model for double gate tunnel field effect transistor (DGTFET) for the current, terminal charges, and terminal capacitances. The model accounts for the effect of the mobile charge in the channel and captures the device physics in depletion as well as in the strong inversion regime. The narrowing of the tunnel barrier in the presence of mobile charges in the channel is incorporated via modeling of the inverse decay length, which is constant under channel depletion condition and bias dependent under inversion condition. To capture the ambipolar current behavior in the model, tunneling at the drain junction is also included. The proposed model is validated against TCAD simulation data and it shows close match with the simulation data.

In this paper, flicker noise behavior of lateral non-uniformly doped MOSFET is studied using impedance field method. Our study shows that Klaassen Prins (KP) method, which forms the basis of noise model in MOSFETs, underestimates flicker noise in such devices. The same KP method overestimates thermal noise by 2–3 orders of magnitude in similar devices as demonstrated in Roy et al. (2007). This apparent discrepancy between thermal and flicker noise behavior lies in origin of these noises, which leads to opposite trend of local noise power spectral density vs doping. We have modeled the physics behind such behavior, which also explain the trends observed in the measurements (Agarwal et al., 2015).

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C–V and I–V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.

This paper proposes, the investigation of the Suspended Gate Field-Effect Transistor (SG-FET) small-slope switch based on a hybrid numerical simulation approach combining ANSYSTM Multiphysics and ISE-DESSISTM in a self-consistent system. The proposed numerical simulations uniquely enable the investigation of the behavior and the physics of complex micro-electro-mechanical/solid-state devices, such as the SG-FET. Abrupt switching as well as the effect of trapped charges in the gate dielectric are demonstrated. The numerical data serve to calibrate an analytical EKV-based SG-FET model, which is then used to design and originally simulate a sub-micron (90 nm) scaled SG-FET complementary inverter. It is shown that, due to abrupt switching in the subthreshold region and electro-mechanical hysteresis, the SG-FET inverter could deliver a significant power saving (1-2 decades reduction of inverter peak current and practically no leakage power) compared to traditional CMOS inverter.