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Soft-switching inverters can achieve high efficiencies and low switchdv/dtanddi/dt, but often impose additional stress on the switches due to their resonant behavior. Multicell converters, on the other hand, can process high voltages by arranging the switches to share the stress. This paper proposes a buck–boost multicell soft-switching inverter with inherent cell voltage balancing. Both the current and voltage stresses are shared by the cells. Soft-switching conditions are achieved for all switching transitions without any need for auxiliary circuitry or clamps. A multiple-winding transformer transfers energy between the terminals and provides galvanic isolation. An analytical study and experimental results on a 1200-W prototype verify the operation of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a fast and practical method is proposed for open-circuit (OC) fault diagnosis (FD) in a three-phase quasi-Z-source inverter (q-ZSI). Compared with the existing fast OC FD techniques in three-phase voltage source inverters, this method is more cost-effective since no ultrafast processor or high-speed measurement is required. Additionally, the method is independent of the load condition. The proposed method is only applicable to Z-source family inverters and is based on observing the effect of shoot-through intervals on the system variables during switching periods. The proposed algorithm includes two consecutive stages: OC detection and fault location identification. When both stages of the OC FD algorithm are done, a redundant leg is activated and utilized instead of the failed leg. The accuracy of the proposed method is confirmed by the experimental results from a low-voltage q-ZSI prototype. [ABSTRACT FROM AUTHOR]

Recently, a few fault-tolerant control strategies have been proposed for T-type three-level inverters to improve the reliability of the inverter system. However, the neutral-point (NP) voltage oscillations suppression is never considered in the previous fault-tolerant control strategies. In order to suppress the NP voltage oscillations when open-circuit fault occurs to NP switches, this paper proposes two novel fault-tolerant control strategies named as improved two-level switching tolerant control and hybrid switching tolerant control (HS-TC). Both methods are implemented by adding an optimal time-offset to the three-phase turn-ontimes. The corresponding time-offset value of each method is simply calculated considering the phase current and dwell time of [O] state. Moreover, an NP voltage balancing algorithm to eliminate the dc deviation and a dc bias to further reduce the NP voltage oscillations are used in the HS-TC. The performance and comparison of the tolerant controls with respect to the NP voltage oscillations, current total harmonic distortion, and dynamic response are illustrated and analyzed through the simulation and experimental results. [ABSTRACT FROM AUTHOR]

There is increasing interest in the use of transformer-less systems for grid-connected photovoltaic applications. Compared to transformer-coupled solutions, transformer-less systems offer a typical efficiency increase of 1–2%, reduced system size and weight, and a reduction in cost. However, the removal of the transformer has technical implications. In addition to the loss of galvanic isolation, dc current injection into the grid is a potential risk. While desirable, complete mitigation of dc current injection via convention current control methods is known to be particularly challenging. For this reason, this paper proposes an active dc suppression method, in which the dc current injection is accurately determined by extracting the line-frequency component from inverter dc-link current measurements, and then, mitigated with an active closed-loop controller. Experimental results from a laboratory grid-connected inverter system are presented to demonstrate the high performance of the proposed technique. [ABSTRACT FROM AUTHOR]

An isolated single sourced multi-output dc/dc converter with a high-frequency link was proposed before to feed different cells of the Asymmetrical Cascaded H-bridge (ACHB) inverter. One of the fundamental advantages of the ACHB is that the main H-bridge is commutated with fundamental frequency, passing the majority of the inverter power. However, the isolated dc/dc converter needs to be connected to the main voltage source with high-voltage/high-frequency switches, which limits the power capability and the efficiency of the converter. In this paper, a switching pattern based on nearest level modulation method is proposed to command all the power to be transferred through the main H-bridge. Therefore, the power circulates between the auxiliary H-bridges with no need for high-voltage switches. As a result, a single-input single-output auxiliary converter is needed with only 5% of the power rating. This solution reduces cost and size while it improves the efficiency of the converter. Furthermore, the architecture makes the inverter more suitable for high power and high-voltage applications. The inverter switching strategy is based on programmable firing angles. The main dc-link of the grid connected inverter is controlled to achieve maximum power point tracking, while the dc/dc isolated converter is controlled to regulate the auxiliary dc-links. The proposed topology is verified by simulation and experimental results using a 1.5 kW hardware prototype. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

In this paper, capacitor current sensorless control by using an observer is applied in a seamless transfer single-phase inverter. The proposed control system is a multiloop control system. The control loop is composed of a capacitor voltage outer control loop and capacitor current inner control loop for stand-alone mode. For on-grid mode, the grid current outer loop controller is combined with the stand-alone control structure to form a simple controller structure for mode switching. The capacitor current feedback signal is calculated using the observer in the discrete-time domain and thus sensors are not required. Use of the proposed observer for the inverter with capacitor current control has many advantages, such as sensorless capacitor current calculation, one-sample-ahead data prediction for sampling delay compensation, and an average capacitor current without ripple components. Verification of the theoretical analysis is presented through simulation and experiment. A 5-kW single-phase inverter prototype combined with a Li-ion battery is set up with a digital controller using a TI TMS320F28377D microcontroller unit to confirm the feasibility of the system. [ABSTRACT FROM AUTHOR]

This paper proposed a novel family of pulsewidth modulation (PWM) strategies for single-phase quasi-switched boost inverter (qSBI). By combining shoot-through (ST) mode in the inverter's switches and the turning-on state of an additional switch, the qSBI produced a high voltage gain without adding any passive components. Compared to the conventional PWM strategy for the same input and output voltage gain, the introduced PWM strategies for qSBI could reduce voltage stress across semiconductors and capacitor with the following additional merits: having smaller high-frequency inductor current and capacitor voltage ripples, using high modulation index with low ST duty cycle, and having higher efficiency. Circuit analysis, operating theories, and simulation results of the single-phase qSBI with the introduced PWM5 strategy are shown. A 500-W laboratory prototype was constructed and the effectiveness of the introduced PWM strategy was validated. The qSBI with the proposed PWM strategies is suitable for applications where the required voltage gain lies between 2 and 3. [ABSTRACT FROM AUTHOR]

Cascaded multilevel inverter (CMI) is one of the most popular multilevel inverter topologies. This topology is synthesized with some series-connected identical H-bridge cells. CMI requires several isolated dc sources which brings about some difficulties when dealing with this type of inverter. This paper addresses the problem by proposing a switched-capacitor (SC)-based CMI. The proposed topology, which is referred to as switched-capacitor single-source CMI (SCSS-CMI), makes use of some capacitors instead of the dc sources. Hence, it requires only one dc source to charge the employed capacitors. Usually, the capacitor charging process in a SC cell is companied by some current spikes which extremely harm the charging switch and the capacitor. The capacitors in SCSS-CMI are charged through a simple auxiliary circuit which eradicates the mentioned current spikes and provides zero-current switching condition for the charging switch. A computer-aid simulated model along with a laboratory-built prototype is adopted to assess the performances of SCSS-CMI, under different conditions. [ABSTRACT FROM AUTHOR]

Most photovoltaic (PV) systems are composed of series and parallel inverters. The electromagnetic interference (EMI) mainly comes from the off–on of inverter switches with pulsewidth modulation (PWM). The output EMI peaks of PV systems would increase markedly due to the interference superposition effect caused by parallel inverters, whose carrier initial phases are in phase or close to each other. In this paper, an auto-screening carrier phase-shift scheme is proposed to weaken the superposition effect of EMI peaks and to get the result of reverse offset at its best. In a PV system, through voltage detections and spectrum estimations of each inverter with a series of phase-shift carriers, a best carrier phase of each inverter is obtained automatically to minimize EMI peaks of the PV system. In order to avoid the conflict that the screening processes of two or more inverters are underway at the same time, a specific frequency signal is output temporarily as an occupancy mark in one of the inverters. The feasibility and effectiveness of the proposed scheme are verified by experimental results in a PV system composed of four parallel single-phase inverters. [ABSTRACT FROM AUTHOR]

Individual microgrids have proven their ability to provide uninterrupted power to critical end-use loads during severe events. Building on the performance of individual microgrids during extreme events, there has been an increasing interest in the operations of network microgrids. By networking microgrids during extreme events, it is possible to share resources, increase the duration for which they can operate islanded, improve efficiency, and increase the resiliency of critical end-use loads. While there are benefits to networking the operations of resiliency-based microgrids, the switching operations that they require introduce transients, which can result in a loss of dynamic stability. The issue of dynamic stability is especially acute in microgrids with high penetrations of inverter-connected generation, and correspondingly low system inertia. While the low inertia of these microgrids can be increased by over-sizing the rotating generators, the increased capital and operating costs can become a barrier to deployment. This paper will present a method of augmenting primary frequency controls to support the switching transients necessary for the operation of networked microgrids, without the need to over-size rotating machines. [ABSTRACT FROM AUTHOR]

A discontinuous pulsewidth modulation (DPWM) strategy for three-level neutral-point-clamped (NPC) traction inverter drive for electric vehicles (EVs) with minimum switching loss for the full power factor (PF) range is developed and presented in this paper. Considering the dynamic loading conditions in an EV propelled by an induction motor (IM), the discontinuous modulation strategy is generalized to obtain minimum switching loss for a wide variations in load PF and modulation depth. The dynamic operating conditions in EV may render frequent unbalances in dc-link capacitor voltages in NPC inverter. It is demonstrated that the addition of an appropriate offset signal with the reference discontinuous signals generates compensating neutral current in the right direction, which can be used to mitigate existing unbalance in two dc-link capacitor voltages. Minimum switching loss at variable PF is attained by positioning the nonswitching clamped regions of the reference auxiliary signals according to the load PF. The effectiveness of the proposed scheme for a wide range of torque/speed variations is studied through simulation by developing a MATLAB/SIMULINK model of an IM traction inverter drive with field-oriented control strategy for closed loop control. Finally, the modulation scheme is validated through experimentation in a small-scale prototype NPC inverter with motor loads. [ABSTRACT FROM AUTHOR]

In this paper, a multipulse ac–dc converter fed multilevel inverter (MLI)-based indirect vector controlled induction motor drive (IVCIMD) is proposed for medium-power application. A 54-pulse ac–dc converter is utilized at the supply side to suppress the input current total harmonic distortion, as per the IEEE-519 standard. Mainly three separate isolated transformers are utilized and each transformer is configured as an 18-pulse ac–dc converter. Due to the phase shift in primary windings, these three transformers are reconfigured as a 54-pulse ac–dc converter. A 15-level binary-based cascaded MLI is utilized at the motor side to enhance the required performance of IVCIMD. A 15-level inverter is switched at fundamental frequency, which ensures the very low switching losses in the proposed IVCIMD. A modified nearest level modulation strategy is proposed to achieve fundamental switching frequency. The performance of the proposed IVCIMD is simulated at various operating conditions by utilizing Simulink/MATLAB platform. Simulated results are validated with experimental results on a developed prototype in the laboratory to show its usefulness for medium-power applications. [ABSTRACT FROM AUTHOR]

This paper proposes advanced speed control for a five-leg voltage source inverter (FLVSI) that drives the dual three-phase induction motor system used in industrial manufacturing processes. The advanced speed control method consists of two controllers: 1) The first is a slip controller that satisfies the application requirement, i.e., to control the mechanical speed of two motors equally regardless of the load condition. 2) The second is an angle controller that satisfies the FLVSI requirement, i.e., to control the phase angle difference between the two motors for minimizing the common leg current because the common leg current can be twice higher than other leg's current depending on the operation condition of the dual motor. Stability analysis of the two controllers under advanced speed control is implemented, and the whole performance of the advanced speed control for the FLVSI-fed dual-motor drive system is shown to identify its feasibility through the experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

This paper proposes a transformerless line-interactive uninterruptible power supply (UPS) with low ground leakage current. A high-efficiency bidirectional inverter is suggested, which performs the line-interactive UPS functions with low ground leakage current. It has a full-bridge inverter and a bidirectional switch, which operate with the unipolar pulsewidth modulation. Because the bidirectional switch operates at the line-frequency, switching losses can be lower than the previous transformerless inverters. As the inverter operates, the parasitic capacitance between the inverter and the ac voltage ground is clamped to zero voltage for a positive line cycle and to the ac voltage for a negative line cycle, respectively. Thus, the parasitic capacitance can be prevented from being charged or discharged, which ensures the absence of the ground leakage current. The operation modes of the proposed system are described. The control schemes are presented to design the proposed inverter for the line-interactive UPS. Experimental results for a 2.0 kW prototype are discussed to verify the performance of the proposed system. [ABSTRACT FROM AUTHOR]

This paper proposes a new diode-clamped multilevel inverter that can effectively balance the voltages of dc capacitors. For the proposed inverter, the inductors are inserted between the diodes and the main switches. Also, the voltage balance of the dc capacitors can be guaranteed by controlling the opening time of the corresponding main switches in particular modes. Thus, the parallel circuits on the dc side in the conventional inverters are canceled. Consequently, the proposed topology requires fewer switches, diodes, and capacitors, although it adds the compensation currents to the corresponding main switches. Both the simulation and experimental results demonstrate the suitability and applicability of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper proposes a deadbeat finite set model predictive current control based on discrete space vector modulation (DSVM) in order to achieve robust characteristics from the grid impedance variation while guaranteeing high performance of output current waveforms and a fixed switching frequency. The proposed DSVM strategy enables to obtain a large number of virtual voltage vectors without complex initialization process or lookup table, which are the drawbacks of the conventional DSVM strategies. A deadbeat technique was adopted to minimize the number of candidate voltage vectors considered in the cost function in order to avoid the high computational burden caused by considering all voltage vectors. The simulation and experimental results were presented to verify the effectiveness and performance of the proposed method using a two-level grid-connected voltage source inverter. [ABSTRACT FROM AUTHOR]

Although high-frequency circulating current exists in parallel-operated inverters, it has not attracted as much attention as low-frequency circulating current, and thus has not been analyzed in detail previously. In this paper, a mathematical model and analysis are presented, which reveal the spectrum components and their changing trends of the circulating currents caused by carrier phase differences. The impact of carrier phase difference on high-frequency circulating current is also analyzed and verified. A closed-loop control scheme is proposed to suppress the switching frequency circulating current caused by carrier phase difference. In addition, the deadbeat and closed-loop control are combined to suppress the low- and high-frequency circulating currents simultaneously, to improve the overall performance of circulating current suppression. The effectiveness of the proposed scheme is verified by the simulation and experimental results acquired from a laboratory platform. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

This paper analyzes the accuracy of the zero-order hold (ZOH) model for the digital pulse width modulator (DPWM) in the s-domain. The s-domain model and the exact z-domain model for the current control of a single-phase inverter with an L-type filter are elaborated for quantifying the deviation of the ZOH model for the DPWM. The influences of the different computational delay and duty-cycle update modes on this deviation is analyzed in detail. The compensation method for this deviation of the ZOH model is proposed for accurately predicting the stability region of the control system in the s-domain. Simulations and experimental tests are executed to verify the effectiveness and correctness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents a new least-mean-square (LMS) algorithm based deadtime compensation method to suppress the current distortion in permanent-magnet synchronous motor (PMSM) field-oriented control (FOC) drives. Compared to conventional average value compensations, the proposed method is robust to switching device parameter variations thanks to the online adaptation capability of the LMS algorithm. Similarly, the disturbance observer compensators are also immune to switching device parameter variations; however, varying motor parameters degrade their compensation performance. Without prior knowledge of switching device or motor parameters, the proposed method can directly reduce the deadtime current harmonics by generating compensation voltage references. In addition, the proposed method is easy to implement since it does not require voltage errors estimation or current harmonics extraction, which are necessary for disturbance observer and adaptive filter based methods. The proposed method is tested on a 2.5-kW voltage-source inverter PMSM drive controlled by an FOC algorithm. Its effectiveness is validated by both experimental results and spectrum analysis. [ABSTRACT FROM AUTHOR]

An adaptive control of DPWM implementable in clamped-three-level inverters with two strings of photovoltaic (PV) panels in cascaded connection is proposed in this paper. The proposed modulation is developed based on the so-called circuit-level decoupling concept. It is able to provide balance line voltage even under unbalanced dc links. The unequal dc voltages appeared due to asymmetric maximum point of power trackings (MPPTs) are controlled by proper injection of zero-sequence voltage to the common mode voltage, while the total dc voltage is regulated based on the voltage commands generated by the MPPT of each string. Thus, both PV strings are able to be operated based on their MPPTs while there is almost no low-order harmonic distortion at the inverter output current. Compared with the previous methods, the high capability of the proposed method is evaluated by simulation study and experimental tests. [ABSTRACT FROM AUTHOR]

Inverter dead-time is known to make open-loop induction motor drives oscillatory, while operating at light-loads in particular. While dead-time compensation schemes exist, precise compensation of the same is often challenging as it involves factors such as device and driver delays and switching transition times, which are difficult to be quantified accurately. Hence, the effect of dead-time could be under or overcompensated. This paper presents a comprehensive analysis of the impact of such undercompensation and overcompensation on the stability of a 100-kW induction motor drive, along with experimental investigations of the same. The effects of undercompensation and overcompensation on the inverter output voltage are analyzed on a switching-cycle average basis. Further, small-signal models are proposed for an open-loop drive, when it is undercompensated and overcompensated. Stability analysis of the above motor drive is reported, which predicts oscillatory behavior with both under and overcompensation, over certain fundamental frequency ranges, respectively. Further, two different types of oscillatory behavior, characterized by different oscillating frequencies, are observed for the cases of under and overcompensation. The analyses are supported by simulations. Experimental investigations carried out also support the analyses and simulation results. [ABSTRACT FROM AUTHOR]

Reliability of power inverters is of dominant importance in various applications, including industrial, military, aerospace, and commercial applications. Therefore, developing fault tolerant (FT) power inverters is extremely needed from the viewpoints of system availability and avoiding harmful consequences. Tolerating various types of faults, preserving full output ratings after the fault, and being cost-effective represent the main challenges for most of existing FT solutions. In this paper, a new FT single-phase five-level inverter topology is proposed. The proposed topology can effectively tolerate both of single or multiple switches faults whether they are of open- or short-circuit fault types. Moreover, the proposed topology does not deteriorate system efficiency in postfault operation compared to the previously developed FT solutions. Evaluation of the effectiveness and robustness of the proposed topology is verified in both of simulation and experimental environments. Different case studies are investigated in order to cover various types and locations of switches’ faults. Moreover, comprehensive comparisons are provided to validate the superiority of the proposed topology over the previously addressed techniques. [ABSTRACT FROM AUTHOR]

To develop thermoelectric power conditioning systems that are highly efficient over a wide range of input voltages and support medium-rated power, this paper introduces a hybrid resonant dc/dc converter using an active voltage-doubler rectifier. When the input voltage is higher than the preset nominal input voltage, the converter operates in the phase-shift full-bridge series-resonant converter mode, in which it achieves high efficiency by softly switching the primary-side switches and reducing the conduction loss. When the input voltage is lower than the nominal one, it operates in the resonant boost mode that boosts the resonant inductor current. By using the active voltage-doubler rectifier on the secondary side of the converter, we can build the converter with less number of active components. As a result, the proposed converter achieves, at low cost, high boost-ratio and high efficiency over a wide range of input voltages. A detailed analysis of the converter operation is presented along with the design procedure. At 35–55 V, a 600-W/360-V prototype of the proposed converter has been built and tested to demonstrate its effectiveness. [ABSTRACT FROM AUTHOR]

A sawtooth carrier-based sinusoidal pulse width modulation (SC-SPWM) technique for asymmetrical six-phase two-level inverters is proposed in this paper, which could reduce both the peak-to-peak amplitude and the changing frequency of the common-mode voltage (CMV). The intersection-plotting method reveals that the mirror symmetrical sawtooth carriers for two three-phase groups can help optimize the distribution of overlapping areas, which is the CMV reduction mechanism of SC-SPWM. Additionally, the Fourier analysis is employed to quantitatively evaluate the modulation index and harmonic performance of SC-SPWM compared with the conventional SPWM and two phase-shifted SPWM methods. Also, further analysis demonstrates that dead time does not affect the reduction of CMV in a noticeable way. Finally, both simulation and experimental results coincide with the theoretical analysis that the proposed SC-SPWM shows the best performance in reducing the CMV amplitude and changing frequency among these four SPWM methods, though it leads to a higher phase current distortion. [ABSTRACT FROM AUTHOR]

In this paper, a three-level quasi-switched boost T-type inverter (3L qSBT2I) is proposed. A new pulse-width modulated (PWM) control method is presented to reduce the inductor current ripple of the qSBT2 I. In the introduced PWM technique, the shoot-through duty cycle is maintained constant to keep the modulation index as high as possible. Then, the only control parameters of the qSBT2I are the duty cycles of the two additional switches. By controlling the duty cycles of the two additional switches, the voltage gain of the proposed qSBT2 I can be improved to a value larger than that of the conventional 3L impedance source inverters. The steady-state analysis, operating principles, and comparisons with the impedance source-based 3L inverters are presented. A 1-kW prototype is constructed to verify the operating principle of the 3L qSBT2I. An indirect dc-link voltage regulator and a capacitor voltage-balance controller are applied to the proposed qSBT2I. Simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

Three-level converters typically feature low switching loss and small filter size. In order to realize a high-power-density design for three-level converters, SiC MOSFETs may be selected instead of using Si insulated-gate bipolar transistors. However, all-SiC-MOSFET-based converters suffer from extremely high total cost. In this paper, a SiC MOSFET and Si device hybrid active neutral-point-clamped (ANPC) converter is proposed. It consists of four Si active switches and only two SiC MOSFETs. Thus, it has lower total cost compared to the all-SiC-MOSFET-based ANPC converter. Furthermore, a dedicated modulation scheme is proposed to completely move all the switching events from Si devices to SiC MOSFETs by using redundant switching states. As a result, the switching losses are significantly reduced and extremely high efficiency is achieved. The proposed converter has fully utilized the low-switching-loss advantage of SiC MOSFETs and the low-cost advantage of Si devices, which shows significant superiority in high-end grid-connected inverter and rectifier applications. [ABSTRACT FROM AUTHOR]

This paper presents a novel three-phase DC-link multilevel inverter topology with reduced number of input DC power supplies. The proposed inverter consists of series-connected half-bridge modules to generate the multilevel waveform and a simple H-bridge module, acting as a polarity generator. The inverter output voltage is transferred to the load through a three-phase transformer, which facilitates a galvanic isolation between the inverter and the load. The proposed topology features many advantages when compared with the conventional multilevel inverters proposed in the literatures. These features include scalability, simple control, reduced number of DC voltage sources, and less devices count. A simple sinusoidal pulse-width modulation technique is employed to control the proposed inverter. The performance of the inverter is evaluated under different loading conditions and a comparison with some existing topologies is also presented. The feasibility and effectiveness of the proposed inverter are confirmed through simulation and experimental studies using a scaled down low-voltage laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper presents a dual-mode Cuk inverter for photovoltaic/thermoelectric power applications. A dual-mode Cuk inverter operates in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM), and has the advantages of low ripples of voltage and current at the input and output, medium power density, and step-up/step-down ability, but is difficult to control because DCM and CCM have distinct system dynamics. To overcome this control problem, we propose to use a repetitive controller (RC) with a multiple phase-lead compensator for the dual-mode Cuk inverter. If the RC is applied by itself, the distinct system dynamics may severely degrade its system performance. Thus, in the proposed RC, we mainly use a multiple phase-lead compensator to compensate for the different phase lags of the dual-mode Cuk inverter. To reduce the burden from the RC, we use the dual-mode nominal duty ratio as feedforward control input. We also analyze the boundary of operation modes in the dual-mode Cuk inverter, then provide detailed and practical guidelines to design the control parameters. Experimental results obtained on a 500-W digitally controlled module integrated converter prototype confirmed the effectiveness of the control approach. [ABSTRACT FROM AUTHOR]

This paper investigates the open-circuit faults of switching devices in the three-level T-Type inverter and proposes a new tolerant control method. The three-phase current and variation of the neutral-point voltage are detected to determine the fault switch. A carrier-based pulse width modulation is developed to tolerate switch fault by transiting from three-level to two-level switching. This makes the modulation scheme easier to be implemented compared to space vector modulation. For the neutral-point fault, the fault phase is operated by two-level modulation to produce the same rating voltage. On the other hand, the inverter is able to produce balanced voltage with reduced rating by keeping the phase of half-bridge fault to the neutral-point voltage. The neutral-point voltage is also able to be balanced by using two-level modulation since it does not contribute the neutral-point current. The performance and effectiveness of the proposed tolerant control are verified by a laboratory build. [ABSTRACT FROM AUTHOR]

Owing to low cost, small size, and low weight, transformerless inverters became prominent in single-phase grid connected photovoltaic (PV) systems. Key issues pertaining to these inverters include suppression of common mode (CM) leakage current and improvement of conversion efficiency. Achieving higher efficiency in single-phase grid-connected photovoltaic systems depends on the number of stages involved in feeding power to the grid, predominantly, if the PV array voltage is less than the peak value of the grid voltage. In this paper, an integrated dc–dc converter based grid-connected transformerless PV inverter is proposed which is aimed at maintaining high efficiency, even if the PV array voltage falls below the peak value of grid voltage (efficient operation at an extended input voltage range). A modulation strategy is discussed in order to minimize the flow of CM leakage current. Further, the efficiencies of certain transformerless inverter topologies are analyzed and compared with that of the proposed topology. Detailed simulation studies are carried out in MATLAB/Simulink environment to verify the analysis. Experimental results for a scaled down laboratory prototype are included as a proof-of-concept to validate the claims. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

The requirements for peripheral circuits of power converters are becoming more restrictive due to the enhancement of Si-based power devices and due to practical use of SiC device. In the design of modern high-speed switching converters, the stray inductances and capacitances both in the device package and in the gate drive circuit in addition to those in the main circuit of the power converter must be considered. In these situations, the gate driving technique represents the key technology for enhancement of high-speed switching ability of power devices, as there are design limitations to reduce the stray inductances and capacitances. So far, several active gate control methods have been proposed. Most conventional active gate drivers are configured using analog circuits such as transistors and diodes. Thus, it is difficult to reconfigure their control parameters to fit the stray inductances and capacitances after the implementation of power converter and gate circuits. As a solution to these problems, the authors have proposed a programmable gate driver IC, which is a digitally controlled circuit. This gate driver IC can control the gate current at 63 separate levels, operated by programmable fully digital 12-bit and clock signals. In this paper, an active gate current control based on the load current in a half-bridge inverter with two programmable gate driver ICs is demonstrated. This developed gate control is different to the general current feedback control followed the reference value. It is verified that the proposed active gate control can effectively improve the tradeoff relationship between the surge voltage and switching loss of the pulsewidth modulation half-bridge inverter circuit. [ABSTRACT FROM AUTHOR]

An optimal current control strategy for asymmetrical hybrid multilevel inverters (MLIs) is proposed in this paper enabling their use on motor drives, static synchronous compensators, and photovoltaic and wind generators, where a fast and precise current regulation is required. A key feature of these highly efficient converters is that an ac machine (motor or transformer) operates according to an open-end winding configuration, connected on one side to a main MLI and, on the other side, to an auxiliary two-level inverter (TLI). The first efficiently controls the main power stream operating at a low switching frequency, while the TLI acts as an active power filter, exploiting a conventional high-frequency two-level pulsewidth modulation (PWM) technique. The proposed control scheme optimally exploits the key features of the two inverters by suitably sharing the control task. In fact, a predictive current control is assigned to the MLI, which can be accomplished by low switching frequency operations, while the high switching frequency of the PWM-operated TLI is exploited to accomplish a fast and precise closed-loop current control, processing only a part of the power stream flowing through the system, thus producing low power losses. Simulations and experimental results confirm the consistency of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper proposes new angles constraint for selective harmonic elimination-pulsewidth modulation (SHE)-PWM utilized in single-phase inverter applications. The proposed angles constraint naturally eliminates all triplen harmonics, whereas they conventionally appeared in all single-phase output voltages. The harmonic amplitude formula is developed based on the obtained angles constraint, and then modified single-phase SHE equations are defined to eliminate only specified low nontriplen harmonics. Therefore, more harmonics would be eliminated with the same switching frequency in modified SHE-PWM. Five-level voltage waveform has been opted to implement the introduced method, but it can be applied on all multilevel voltage waveforms such as seven-level with even number of angles. Unlike the conventional SHE technique, THD is analyzable in modified SHE to find optimum values for switching angles in order to control noneliminated harmonic amplitudes and minimize THD. Moreover, the cancellation of triplen harmonics empowers a single-phase inverter to supply nonlinear loads beside linear ones. Some experimental tests are accomplished using a single-phase five-level modified packed U-cell (MPUC) inverter. Results are discussed to prove the excellent performance of a single-phase MPUC inverter under both normal and harmonic loads and accurate elimination of determined triplen and nontriplen harmonics by applying the presented angles constraint. [ABSTRACT FROM AUTHOR]

This paper illustrates the application of a solving method of linear systems to a multilevel inverter. This study applies a generic pulsewidth modulation (PWM) method to a multilevel topology. This method finally highlights some specific modulation schemes. First, the study describes the mathematical model of the inverter leg. The leg is made of three level T-type structure. The model is extended to the three-phase inverter. The generalized inverse is used to generate the solution set of the conduction rates. Among the modulation strategies possible, three specific modulation schemes are proposed. The modulation schemes are applied to simulate a PWM three-phase inverter. Finally, some experimental results complete the analysis. [ABSTRACT FROM AUTHOR]

In this paper, a novel six-switch dual-output inverter is proposed. The three-switch leg in the proposed inverter is implemented with the dual-buck structure. Hence, it retains all the benefits of the conventional dual-buck inverter such as improved reliability owing to the absence of short-circuit problems and higher efficiency with the use of power metal–oxide–semiconductor field-effect transistor (mosfet) without reverse recovery issues on its body diode. In addition, the passive components can be reduced with the high switching frequency operation. A 3.5-kW, 400-V dc input mosfet-based hardware prototype was built and tested to verify the performance of the proposed inverter and a maximum efficiency of 97% was achieved. [ABSTRACT FROM AUTHOR]

A wide-range soft-switching high-efficiency cycloconverter-type high-frequency-link inverter with dual-phase-shift modulation strategy is proposed in this paper. By adding an auxiliary inductor in primary-side full bridge circuit and adopting center-tapped four-winding transformer structure, the soft-switching range for primary-side switches has been extended. The secondary-side active clamper network is designed to recycle leakage inductor energy, and suppress voltage spikes caused by the resonance of the leakage inductor and the parasitic capacitance of switches. One feature of the proposed inverter is that both the primary-side full-bridge and active clamper network employ phase-shift modulation technique where all switches are driven with nearly 50% duty cycle square signals, hence a simple and reliable transformer-isolated gate drive circuit with small transmission delay is presented. Moreover, all switches in the proposed inverter achieve zero voltage switching, which contributes to higher conversion efficiency as well as higher switching frequency. Analysis, design, and implementation of the proposed inverter are discussed in detail. A 200-kHz laboratory prototype for the high-voltage audio amplifier application is developed and the experimental results are presented to validate the analysis and performance of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a zero-sequence circulating current (ZSCC) control scheme for the multiparalleled three-level T-type inverters (3LT2Is). Based on the analysis with the proposed generalized model of multiparalleled 3LT2Is, it is seen that the ZSCC is influenced by the circuit parameters, duty cycles, and the circulating currents of the l th and first 3LT2I. To mitigate the circulating currents, a deadbeat control strategy for n-paralleled (n≥3) inverters is proposed, which is realized by adjusting the duty cycle of the small vectors in each PWM sampling period. Compared with the conventional PI control method, the ZSCC spike is mitigated with the proposed scheme, thus improving the quality of the output currents. Also, the reliability of the 3LT2Is system is improved because such a scheme only needs the information about the ZSCC and zero-sequence duty ratio in the l th and the first inverter. The proposed method can also be applied to the neutral-point-clamped converters. Simulation and experimental results verify the effectiveness of the theoretical analysis and the proposed method. [ABSTRACT FROM PUBLISHER]

Microinverters operating into the single-phase grid from new energy source with low-voltage output face the challenges of efficiency bottleneck and twice-line-frequency variation. This paper proposed a multilevel inverter based on bridge modular switched-capacitor (BMSC) circuits with its superiority in conversion efficiency and power density. The topology is composed of dc–dc and dc–ac stages with independent control for each stage, aiming to improve system stability and simplify the control method. The BMSC dc–dc stage, which can be expanded to synthesize more levels, not only features multilevel voltage gain but also partially replaces the original bulk input capacitor and functions as an active energy buffer to enhance power-decoupling ability between dc and ac sides. In dc–ac stage, the control strategy of optimized unipolar frequency doubling sine-wave pulse width modulation is proposed to improve the quality of output waveform. Meanwhile, the multilevel voltage phase has been optimized to further reduce the power loss. Finally, a prototype has been built and tested. Associated with the simulation, the experimental results validate the practicability of these analyses. [ABSTRACT FROM PUBLISHER]

Three-phase three-leg inverter is one of the most popular topologies for inverters. When short-circuit fault occurs, the inverter is generally switched to the current-controlled mode from voltage-controlled mode to limit the fault currents. In this situation, the inverter becomes equivalent to a symmetric, three-phase, positive sequence current source. However, the voltage limiting may occur under asymmetrical fault. In this paper, a closed-loop model based on time-domain is originally developed as a means to investigate the fault current characteristics under asymmetrical fault. Based on the proposed model, a more intuitive insight into fault currents is presented as follows. 1) The positive sequence fundamental component of three-phase currents can still track the symmetric current references. 2) The magnitude of fault phase currents (ignoring the harmonics) will vary between 1 and $\sqrt 3 $ times of magnitude of current limiting references. Based on the conclusion, although the magnitudes of fault phase currents can be reduced by adopting smaller current limiting references, the actual magnitudes of fault phase currents will still vary in a range depending on the load impendence of healthy phase. Therefore, the reliable action of the protection devices is greatly affected and the selective protection cannot be realized. Furthermore, in order to achieve completely controllable fault currents under asymmetrical fault, two alternative current limiting strategies are presented with reverse current limiting references, and with current limiting references based on the introduced phase angle regulation. The theoretical results are validated by simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper introduces a new analysis approach to modeling resonant converters that can be used to determine closed-form expressions for the exact resonant network waveforms. This approach, based on superposition of step responses to inverter and rectifier imposed steps, can easily be applied to resonant converters with high-order resonant networks, multiple inverters, and/or rectifiers. The usefulness of the proposed analysis approach is demonstrated first by applying it to a series-resonant converter, wherein it is used to determine accurate closed-form expressions for its tank current in different operating modes. These expressions are utilized to draw insights that help identify the converter's operating mode, and determine associated expressions for its output voltage and the switching frequency required to achieve a desired output power. The proposed approach is also applied to the multi-inverter multi-element impedance control network (ICN) resonant converter, wherein it is used to derive closed-form expressions for the converter's currents. These expressions are utilized to evaluate the behavior and optimize the design of an ICN resonant converter. A prototype 200-W 500-kHz ICN resonant converter optimized using the proposed approach is used to validate the modeling results. It is shown that there is an excellent agreement between the experimental and modeled waveforms during steady-state operation as well as during startup transients. [ABSTRACT FROM AUTHOR]

Pulse generator in an ultrasound system produces electrical pulsing signals to drive piezoelectric transducer, which causes mechanical vibration of the crystals and generates sound waves. Different from conventional imaging short pulses, high-power ultrasonic system for therapeutic applications requires MHz pulses bursts of up to tens of milliseconds. The capability of switching high voltage (±90 V) at multi-MHz, delivering effective power efficiently, is crucial for practical systems. The advantages of low device loss at high switching frequency, and high power density make gallium nitride (GaN) high electron mobility transistors better devices than traditional silicon (Si) MOSFETs in such system. The GaN-based high-frequency transformer push–pull inverter presented in this paper is capable to produce high energy pulsating output with burst pulse length up to 50 ms and bipolar pulse amplitude of 180 Vpp. The maximum pulse frequency can be up to 10 MHz. The peak output power is 90 W with power density of 50.85 W/in2. The peak power for all the 128 pulser channels reaches up to 11.5 KW with average power of 192 W. This is the highest output power for pulse drivers that have been reported. A novel power transistor based RF switch circuit is also proposed in this design as the interface between image signal, high power signal, and return signal. [ABSTRACT FROM AUTHOR]

This paper characterizes the sampling effect in digital sinusoidal pulse width modulation (SPWM) of voltage source inverter (VSI). The time-domain analysis presented in this paper establishes the relation between the fundamental frequency, carrier frequency, and the sampling frequency at different modulation indices of the SPWM. The analysis investigates the effect of sampling frequency of the digital controller on the output of the VSI. It is shown that the low-frequency harmonic components appear in the frequency spectrum of the VSI output voltage due to sampling. As a result, the output current of digitally controlled VSI is stepped in nature. The double Fourier integral solution of the switched waveform for inner and outer integral limits has been used to derive the expression. The integral solution is obtained using Jacobi-Anger expansions. The generalized results developed in this paper are useful to investigate the sampling effect in high switching frequency DSPWM. The proposed sampling effect has been analyzed for SPWM of single-phase H-bridge inverter. The analytical results are verified using simulation and experimental results. The experimental results have been obtained with the use of field-programmable gate array (FPGA) as a digital controller. [ABSTRACT FROM PUBLISHER]