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Streaming codes take a string of source symbols as input and output a string of coded symbols in real time, which eliminate the queueing delay of traditional block codes and are thus especially appealing for delay sensitive applications. Existing works on streaming code performance either focused on the asymptotic error-exponent analyses, or on the optimal code construction under deterministic adversarial channel models. In contrast, this work analyzes the exact error probability of random linear streaming codes (RLSCs) in the large field size regime over the stochastic i.i.d. symbol erasure channel model. A closed-form expression of the error probability of large-field-size RLSCs is derived under, simultaneously, the finite memory length and decoding deadline constraints. The result is then used to examine the intricate tradeoff between memory length (complexity), decoding deadline (delay), code rate (throughput), and error probability (reliability). Numerical evaluation shows that under the same code rate and error probability requirements, the end-to-end delay of RLSCs is 40–48% of that of the optimal block codes (i.e., MDS codes). This implies that switching from block codes to streaming codes not only eliminates the queueing delay completely (which accounts for the initial 50% of the delay reduction) but also improves the reliability (which accounts for the additional 2–10% delay reduction). [ABSTRACT FROM AUTHOR]

This article presents a wearable breath-monitoring device integrated with humidity- and ammonia-sensing functions. The breath-monitoring device was constructed using a piezoelectric cantilever array and hollow flexible polydimethylsiloxane (PDMS) membrane. Important parameters of breath, such as the respiratory rate and tidal volume, can be detected without actuated energy. The Nafion-based capacitive humidity sensor and ZnO nanoparticle-based resistance ammonia sensor were compactly integrated into the housing ring of a breath monitoring device. The fabricated humidity sensor demonstrated a faster response in the sensing range below 75% compared with a commercial product. The sensitivity of the fabricated ammonia sensor reached 0.16 ppm/mV and the sensor exhibited an approximately fourfold shorter response time compared with the commercial product. Two applications were tested for the developed device prototype. One was monitoring the humidity and ammonia of the environmental air along with breath parameters while breathing. The other was to examine the amount of breath air exhaled from the body of the subject. The total power consumed by the developed prototype device was approximately 46 mW, which is significantly lower than that of existing commercial products. This compact and lightweight prototype device demonstrates significant potential for wearable applications. [ABSTRACT FROM AUTHOR]

This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current ($I_{\text {ON}}$). The capacitance matching and ON-state performance are evaluated using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current ($I_{\text {OFF}}$) and $I_{\text {ON}}$ relative to International Roadmap for Devices and Systems (IRDS) projections. There is a significant long-term advantage to integrated circuit (IC) power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing. [ABSTRACT FROM AUTHOR]

This brief investigates scaled 2-D MoS2 ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) considering the trapped-charge-induced variability with the aid of Technology Computer Aided Design (TCAD) atomistic simulations. Our study indicates that, compared with the Si channel, the monolayer MoS2 channel with larger electron affinity and bandgap energy can result in an FeFET NVM with larger memory window (MW). Moreover, due to its lower channel permittivity and channel thickness, the 2-D MoS2 FeFET possesses a superior immunity to trapped-charge-induced variability, and the gap in MW between MoS2 and Si FeFETs enlarges under the presence of trapped charges. Besides, due to its atomically thin channel thickness and superior electrostatic integrity, the scaled 2-D MoS2 FeFET possesses a remarkably better read margin than the Si counterpart. Our study may provide insights for future scaling of FeFET NVMs. [ABSTRACT FROM AUTHOR]

This article investigates the impact of interface trapped-charge variations on the dimensional scaling of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) under two scenarios: a uniform ferroelectric and random ferroelectric-dielectric (FE-DE) phase distribution. Our study indicates that both memory window (MW) and read margin decrease with increasing trap density (< nT >), and the MW of FeFET devices with scaled channel width can be more vulnerable to the trapped-charge variations than that with scaled gate length. Under the presence of the FE-DE phase variation, for low < nT >, the impact of trapped charges is mainly on the MW degradation for the high MW instances. As the < nT > continues to rise, the trapped charges can further worsen the worst case MW significantly. Besides, when down-scaling the interfacial layer thickness of the FeFET device to increase the MW, the increased σ MW due to the random interface trapped charges may also need to be considered. Our study may provide insights for device design with advanced FeFET NVMs. [ABSTRACT FROM AUTHOR]

Single ferroelectric-FET (FeFET) reconfigurable logic-in-memory is an attractive beyond-von-Neumann scheme for data-centric computing. Different from using body-to-source voltage to tune the operating point of the FeFET for reconfigurability, this brief presents an alternative approach based on the unique ferroelectric minor-loop behavior (which results from the partial switching of domains). Through simulation, we show that the NAND/ NOR reconfigurability can theoretically be achieved by adequately modulating the reference and writing pulses for the FeFET nonvolatile memory (NVM). Our approach may serve as an option when the body-effect capability is lacking for nonplanar FeFETs or 3-D stacked FeFETs which can be crucial to future high-density integration. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs. [ABSTRACT FROM AUTHOR]

This letter investigates the depolarization field in a metal-ferroelectric-metal-insulator-metal (MFMIM) nonvolatile memory (NVM) considering the minor hysteresis loop operation. Our study indicates that, different from previous studies merely considering the major loop operation, the depolarization field for the ferroelectric undergoing the minor loop increases with decreasing oxide thickness. In other words, in addition to suppressing the gate leakage, thicker oxide thickness is favorable to lower the depolarization field and improves the retention for a given memory window (MW). This letter may provide insights for device design of ferroelectric nonvolatile memories. [ABSTRACT FROM AUTHOR]

This paper investigates the fin-width ($\text{W}_{\textsf {Fin}}$) sensitivity of threshold voltage ($\text{V}_{\textsf {T}}$) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ for NC-FinFETs. Our study may provide insights for future scaling of FinFETs. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal–ferroelectric–insulator–semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications. [ABSTRACT FROM AUTHOR]

For the first time, the drain-bias dependence of mean free path, predicted by previous Monte Carlo simulations, is experimentally confirmed in Si ${n}$ FinFETs by using an improved formulation, considering the additional scatterings attributed to source/drain as well as the carrier degeneracy. This letter indicates that, for optimized Si ${n}$ FinFETs, the carrier velocity and drive current still increase monotonically with decreasing channel length. However, the degradation in mean free path leads to the saturation in ballistic ratio (~60%), resulting in quasi-ballistic transport for devices even with sub-20-nm channel length. [ABSTRACT FROM AUTHOR]

This letter investigates the impact of fin line-edge roughness (Fin-LER) on the intrinsic variation of negative capacitance FinFETs (NC-FinFETs) by TCAD atomistic simulation coupled with the Landau–Khalatnikov equation. We report a feedback mechanism stemming from the internal voltage amplification inherent in the negative capacitance FET. This feedback mechanism results in the superior immunity to Fin-LER-induced threshold-voltage and subthreshold-swing variations for NC-FinFETs as compared with the FinFET counterparts. This letter may provide insights for device/circuit designs using negative capacitance FETs. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and scalable model, this paper explores the design space for negative-capacitance (NC) field-effect transistors (FETs) with a 2D semiconducting transition-metal-dichalcogenide channel. In addition, the impact of back-gate biasing on the design space and the body effect of 2D-NCFETs is also investigated. Our study indicates that, to mitigate the conflict between subthreshold swing and hysteresis and to maximize the design space for the 2D-NCFET, a thin buried oxide and an adequate reverse back-gate bias can be applied to achieve the optimum design. [ABSTRACT FROM PUBLISHER]

For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or few-layer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. The monolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design. [ABSTRACT FROM AUTHOR]

A phase-locked loop (PLL) architecture is proposed for improved efficiency of power and thermal management techniques in system-on-chips (SoCs). PLL architecture introduces two techniques: a dual-stage phase-acquisition loop filter that enables fast lock time of 1.2 \mu \texts without any frequency overshoots and a nonlinear DCO that enables a wide frequency range of 0.5–9.5 GHz and a low period jitter of ±1.25%UI p-p with a single wideband tuning. With this proposed PLL architecture, SoC can continue its operation without any interruption caused by frequency overshoots during power and thermal management techniques like dynamic core-count scaling and dynamic voltage frequency scaling. The PLL achieves 0.45 ps rms period jitter at 3.25 GHz in fractional-N mode operation, while consuming a total power of 7.1 mW. [ABSTRACT FROM PUBLISHER]

This brief presents a compact subthreshold model for short-channel monolayer transition metal dichalcogenide (TMD) field-effect transistors. In this model, the impact of fringe fields from the high-K gate dielectric is considered and incorporated into a new characteristic-length expression using a single model parameter. This model has been verified with 2-D numerical simulations for TMD devices with gate length down to 5.9 nm based on ITRS 2028 low-power technology node. [ABSTRACT FROM PUBLISHER]

This letter evaluates and analyzes the impacts of random variations on cell stability and write-ability of low-voltage SRAMs using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) node with the aid of atomistic TCAD mixed-mode simulations. Our study indicates that, for 6T SRAM, the monolayer/bilayer TMD devices may fail to provide the $6\sigma $ yield requirement for read static noise margin (RSNM) due to severe metal-gate work function variation in spite of their excellent electrostatics, and hence circuit techniques, such as bootstrapped dynamic power rails or the standard 8T cell, are needed. Besides, R_{\mathrm {SD}} as a major concern of TMDs should be less of an issue for near-/sub-threshold SRAMs for ultra low-power applications. For the standard 8T cell structure, the RSNMs of both monolayer and bilayer 8T SRAMs improve significantly, and the bilayer 8T SRAM exhibits better write static noise margin (WSNM). In addition, write-assist techniques (including negative bit-line, boosted word-line, and lower cell supply) for improving WSNM are examined and shown to be more effective for monolayer 8T SRAMs than the bilayer counterparts. [ABSTRACT FROM PUBLISHER]

For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electrostatics and superior stability, the monolayer TMD is favored for low-power SRAM applications, while the bilayer TMD, with higher carrier mobility, is more suitable for relaxed channel length and high-performance SRAM applications. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of quantum capacitance on the intrinsic inversion-capacitance ( C\mathrm{ inv}) characteristics of high-mobility multigate III–V-on-insulator nMOSFETs through a numerical simulation corroborated by the theoretical calculation. Nonmonotonic C\mathrm{ inv} characteristics stemming from the energy dependence of 1-D density-of-states and significant C\mathrm{ inv} degradation due to quantum capacitance have been found in trigate In0.53Ga0.47As and InAs devices based on the ITRS 2018–2024 technology nodes. This paper indicates that, to compensate the excess inversion-charge ( Q\mathrm{ inv} ) loss due to quantum capacitance, the needed mobility gain of the trigate InGaAs and InAs devices (against the Si counterparts) should be at least $\sim 3\times $ and $\sim 4\times $ , respectively. This paper also suggests that the quantum-capacitance-induced Q\mathrm{ inv} loss can be mitigated by raising the fin aspect ratio of the III–V multigate device. [ABSTRACT FROM AUTHOR]

This paper analyzes the impacts of read-assist and write-assist circuits on GeOI FinFET 6T SRAM cells considering intrinsic random variations, process corner, and temperature variation. The word-line under-drive (WLUD) read-assist is more efficient to improve the read static noise margin and read $V_{{\rm {MIN}}}$ of fast-N slow-P corner GeOI FinFET SRAM cells compared with the Silicon-On-Insulator (SOI) counterparts. GeOI FinFET SRAM cells with WLUD show less cell read access-time degradation compared with the SOI counterparts at both 25 °C and 125 °C. With transient voltage collapse (TVC) write-assist, the write-ability and variation tolerance of GeOI and SOI FinFET SRAM cells are improved. The temperature dependence of data retention time is different between the GeOI and SOI FinFET SRAM cells. The maximum TVC write-assist pulsewidth constrained by the data retention failure is smaller in GeOI FinFET SRAMs at 25 °C and becomes comparable at 125 °C compared with the SOI FinFET SRAMs. [ABSTRACT FROM AUTHOR]

This paper provides an analytical subthreshold model for trigate MOSFETs with thin buried oxide (BOX) for multithreshold (multi- Vth ) applications. This model shows a fairly good scalability in substrate bias and BOX thickness, which is crucial to the prediction of multi- Vth modulation through BOX. In addition, we demonstrate the application of our model in multi- Vth device design for trigate GeOI p-MOSFETs with the body-effect coefficient ( $\gamma $ ) over a wide range of design space efficiently examined. We have shown an enhanced multi- Vth modulation behavior in trigate GeOI p-MOSFETs. Our study indicates that, for a given subthreshold swing and $\gamma $ , the GeOI trigate p-MOSFET can possess a higher fin aspect ratio than the SOI counterpart. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of backgate biasing ( VBS ) on the drain current ( ID ) of ultrathin-body III-V heterojunction tunnel FET (HTFET). Compared with homojunction TFET and III-V/Ge MOSFET, this paper indicates that HTFET exhibits significantly higher I\mathrm{{\scriptstyle OFF}} ( ID at VGS = 0 V and VDS=0.5 V) modulation efficiency and the influence of VBS rapidly decreases with increasing VGS . In addition, it is observed that the change of source available states with VBS determines the ID modulation efficiency of p-type HTFET (pHTFET). Depending on the source doping concentration and operating VGS , the ID of HTFET under forward VBS can be anomalously smaller than that at VBS=0 V. Furthermore, the impacts of source/drain doping concentrations and junction properties are discussed and shown to be critical in determining the ID modulation efficiency of HTFET. We find that, under controlled ambipolar current, reverse backgate biasing can be utilized to suppress the I\mathrm{{\scriptstyle OFF}} of HTFET, and the modulation efficiency increases with decreasing source doping concentration. Our study may provide insights for device/circuit designs with advanced TFET technologies. [ABSTRACT FROM PUBLISHER]

This paper extensively evaluates the stability and performance of heterochannel 6T/8T SRAM cells integrated in monolithic 3-D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. This paper indicates that stacking the NFET tier over the PFET tier results in larger design margins for cell robustness and performance. Furthermore, the partition of 3-D layout design among distinct layers shows profound impacts on the stability, standby leakage, and performance of monolithic 3-D SRAM cells. Compared with the Si-based cells, the use of heterochannel devices increases the improvements of monolithic 3-D design over the 2-D counterparts and emerges as a suitable candidate for future monolithic 3-D IC applications. [ABSTRACT FROM PUBLISHER]

This brief investigates the random grain-boundary (GB)-induced variability in poly-crystalline silicon thin-film transistor for stackable NAND flash applications using 3-D Voronoi grain patterns. Compared with the 1-D and 2-D methods, the 3-D Voronoi grain can show a more realistic threshold-voltage variability when devices are downscaled along the channel height (Hch) direction. Therefore, a full 3-D consideration is needed when modeling the random GB-induced variation. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of backgate bias (Vbg) on the sensitivity of threshold voltage (Vth) to process and temperature variations for ultra-thin-body (UTB) GeOI and InGaAs-OI MOSFETs. Our study indicates that the quantum-confinement effect significantly suppresses the Vbg dependence of the Vth sensitivity to process and temperature variations. Since Si, Ge, and InGaAs channels exhibit different degrees of quantum confinement, the impact of quantum confinement has to be considered when one-to-one comparisons among hetero-channel UTB devices regarding variability are made. Our study is crucial to the robustness of multi- Vth designs with advanced UTB technologies. [ABSTRACT FROM PUBLISHER]

We present a comparative leakage analysis of germanium-on-insulator (GeOI) FinFET and germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit levels. Band-to-band tunneling (BTBT) leakage-induced bipolar effect is found to result in an amplified BTBT leakage for GeOI FinFET. Device and circuit designs to mitigate the amplified BTBT leakage of GeOI FinFETs are suggested. The effectiveness of various high threshold voltage technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed. [ABSTRACT FROM AUTHOR]

This paper analyzes and compares the stability, margin, performance, and variability of ultrathin-body (UTB) SOI 6T SRAM cells operating near the subthreshold region with different threshold voltage (Vth) design. Our results indicate that UTB SOI 6T SRAM cell using low Vth devices (\vert Vth\vert = 0.19 V) shows a comparable read static noise margin (RSNM), 41% improvement in σRSNM, 84% improvement in write static noise margin (WSNM), and 67% improvement in σWSNM as comparaed with the case using higher Vth devices (\vert Vth\vert = 0.49 V). As Vth decreases (work function moves to the band edge), the “cell” access time improves significantly with correspondingly higher standby leakage. For low Vth devices (\vert Vth\vert = 0.19 V), it is shown that lowering bit-line precharge voltage by 50 mV reduces the standby leakage by 20%. Our study suggests that the lower Vth devices operating slightly into super-threshold region improve the stability/variability significantly and offer higher performance for ultralow voltage SRAM applications. [ABSTRACT FROM PUBLISHER]