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B Abstract b Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. In the year 2004 she received her M.Sc. Degree in Electrical Engineering at Pontifical Catholic University of Rio Grande do Sul (Brazil) and in 2008 her Ph.D. in Computer Engineering from the Politecnico di Torino (Italy). Graph B Tiago Roberto Balen b received the Electrical Engineering degree, MSc and PhD degrees from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 2004, 2006, and 2010, respectively. [Extracted from the article]

The article discusses the use of Physical Unclonable Functions (PUFs) in electronic systems for secret key generation and device authentication. Specifically, it focuses on the use of SRAM PUFs, which are popular due to the randomness they possess during power-on. The authors propose two methods that utilize both stable and unstable SRAM bits as PUF bits to increase the usage rate of SRAM bits and resist PUF clone attacks. Extensive experiments have been conducted to demonstrate the effectiveness of these methods. The article also provides brief biographies of the authors. [Extracted from the article]

In this paper, a schmitt trigger-based single-sided 7T stable SRAM is proposed for ultra-low energy and near-threshold operation, which supports a bit interleaving scheme. The proposed ST-7T SRAM design improves the WSNM (Write Static Noise Margin) and RSNM (Read Static Noise Margin) and consumes less energy. Moreover, obtain high read strength by utilizing a single-sided ST (schmitt trigger) inverter. Furthermore, write ability is also enhanced by applying an ST inverter write assist scheme (Negative VWWL technique), which can limit the tripping voltage of the ST inverter circuit. The PST-7T (Proposed ST-7T) circuit minimizes the read power by 49.96%, write power by 39.27%, and leakage power by 39.17% compared to conventional-6T SRAM. The RSNM and WSNM of the proposed SRAM circuit are enhanced by 66.28% and 18.97% compared to conventional-6T SRAM. The write energy and read energy utilization are also lowered by 14.87% and 14.19% compared to the SE7T SRAM cell. [ABSTRACT FROM AUTHOR]

This paper investigates a low leakage power 8 T (LP8T) SRAM cell with high read and write stability. The proposed LP8T (PLP8T) SRAM cell has separate write and read bit lines. As an outcome, the read disturbance is removed. Furthermore, the utilization of a schmitt-trigger (ST) inverter enhances the read stability. Moreover, the write assist technique can enhance the writing ability. When compared to conventional-6 T SRAM, the PLP8T SRAM cell improves HSNM, RSNM, and WSNM by 1.4× 2.3 × and 1.3× respectively. The PLP8T SRAM's read and write access times are lowered by 53.24 and 42.18%, respectively. The PLP8T SRAM has a 50% lower read and write power than conventional-6 T SRAM. In addition, there will be a sufficient improvement when compared to chang10T, HSWA9T, SEDFC8TT, and ST11T SRAM cells. [ABSTRACT FROM AUTHOR]

In this paper, a 12-transistor radiation tolerant SRAM cell has been proposed in 16-nm CMOS predictive technology model. The proposed 12T SRAM cell offers higher immunity to soft error than all other compared memory cells. The proposed SRAM cell proves its robustness against radiation strike by showing the largest amount (4.1 fC) of critical charge (QC) among all the comparison SRAM cells. The proposed 12T cell consumes 48.03%, and 48.68% lower hold power than QUCCE 12T and QUCCE 10T SRAM cell, respectively. It exhibits 79.92%, 33.77%, 84.84%, and 59.97% shorter read delay compared to 6T SRAM, QUCCE 10T, WE QUATRO, and QUCCE 12T, respectively at a nominal supply voltage of 0.7 V. In terms of write delay the proposed 12T exhibits 68.49% shorter write delay as compared with QUCCE 10T. The proposed circuit has higher RSNM as compared to other SRAM cells and consumes lesser silicon area than other comparison cells except 6T and QUCCE 10T SRAM cell. The read stability of proposed 12T is 3.10×, 1.76×, 2.09×, 1.62 × times higher than 6T SRAM, QUCCE 10T, WE QUATRO, and QUCCE 12T, respectively. The proposed 12T exhibits 65.85%, 41.46%, 26.82%, and 41.46% improvement in critical charge (QC) in comparison with 6T SRAM, QUCCE 10T, WE QUATRO and QUCCE 12T, respectively. However, these improvements are achieved at the cost of marginal degradation of write margin as compared to 6T, QUCCE 10T, WE QUATRO and QUCCE 12T SRAM cells, respectively. In terms of area, the proposed 12T acquires lesser area as compared to QUCCE 12T (6.32%) and WE QUATRO (12%). Hence, the proposed 12T SRAM cell is a promising selection for future highly reliable terrestrial applications. [ABSTRACT FROM AUTHOR]

Today's high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or nonvolatile data storage for electronic devices such as mobile phones, laptops, the Static Random-Access Memory (SRAM) has been perfect choice for industrialists. So, memory usage is significant and more than 65% of electronic devices uses memory as its heart. Nevertheless, memory turns out to be a leading factor affecting speed, power and data retention in a handheld system. The urge for optimization in power is all time relevant. The proposed system is designed to optimize a single bit memory cell of conventional static random-access memory and hence developed a stable system with low power consumption and obtained significantly low Power-Delay-Product (PDP) by varying operating frequencies in MHz (Mega Hertz) range. Also, a comparative analysis of a 4 × 4 SRAM array is carried out between 6 T SRAM cell and 9 T SRAM cell. Here 62.83% power reduction is obtained in the proposed system as compared with the existing system at an operating frequency of 2 GHz. In this paper, a power reduction of 62.273% is obtained for the array structure. The power dissipation and Power Delay Product [PDP] of the single bit 9 T SRAM cell is also lower than the conventional 6 T SRAM. Thus, the paper implements the proposed scheme of SRAM into an array along with all connecting peripherals. [ABSTRACT FROM AUTHOR]

Burst buffer has become a major component to meet the I/O performance requirement of HPC bursty traffic. This paper proposes Gfarm/BB that is a file system for a burst buffer efficiently exploiting node-local storage systems. Although node-local storages improve storage performance, they are only available during the job allocation. Gfarm/BB should have better access and metadata performance while it should be constructed on-demand before the job execution. To improve the read and write performance, it exploits the file descriptor passing and remote direct memory access (RDMA). It improves the metadata performance by omitting the persistency and the redundancy since it is a temporal file system. Using RDMA, writes and reads bandwidth are improved by 1.7x and 2.2x compared with IP over InfiniBand (IPoIB), respectively. It achieves 14 700 operations per second in the directory creation performance, which is 13.4x faster than the fully persistent and redundant case. The construction of Gfarm/BB takes 0.31 seconds using 2 nodes. IOR benchmark and ARGOT-IO application I/O benchmark show the scalable performance improvement by exploiting the locality of node-local storages. Compared with BeeOND, Gfarm/BB shows 2.6x and 2.4x better performance in IOR write and read benchmarks, respectively, and it shows 2.5x better performance in ARGOT-IO. [ABSTRACT FROM AUTHOR]

This paper presents an error resilience evaluation of the intra prediction step in Versatile Video Coding decoders when approximate storage is employed in the Reference Line Buffer (RLB). We present an error injection framework to simulate the use of approximate storage in the RLB buffer with commonly used bit error rate (BER) values from literature for static random-access memory and dynamic random-access memory technologies. We perform an error resilience evaluation based on peak signal-to-noise ratio and structural similarity for twelve video sequences, considering different decoding settings, with four quantization parameters, two encoding configurations, and seven BERs. We also present a few examples, showing how approximately decoded sequences can look and performing a subjective visual quality analysis. Our analysis characterizes how the impacts of approximation are dependent on video content and configurations. The results show that approximate storage can be used in some of the evaluated scenarios with very low degradation on the final visual quality of the decoded video sequences. [ABSTRACT FROM AUTHOR]

Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]

A novel reduced power with enhanced speed (RPES) technique for Static Random Access Memory (SRAM) topologies using Carbon Nano Tube Field Effect Transistors (CNTFETs) instead of traditional MOSFETs which is in demand for edge AI devices, energy efficient deep neural networks, smart wearable devices and high-speed era is proposed in this paper. This work reduces propagation delay and sub-threshold leakage current using RPES technique with a power supply of 0.9V. The performance and power delay product (PDP) of 6T, 8T and 10T SRAM cells is analysed for CNTFET based RPES technique at 45nm technology. Simulated results using Stanford CNTFET model shows improvement in PDP of proposed 6T SRAM cell by 66% compared to Conv6T and 27% compared to Ternary 4TSTI 6T SRAM. Conv 8T and Diff 8T are implemented using RPES technique which shows improvement by 40.9% and 74.3% respectively. Among SE10T and Diff 10T topologies, Diff 10T has better PDP when implemented using RPES technique. All SRAM cells mentioned are analyzed for various high-k dielectric materials, oxide thickness and pitch values of CNTFET and best fitting results are proposed for SRAM cells. [ABSTRACT FROM AUTHOR]

As the technology is scaled the power consumption increases significantly, because of which the battery life of portable devices is reduced. Due to high power density, the increased power consumption becomes an obstacle for scaling of devices. Power optimization is the most significantly visible in future portable IC's. As per increasing need for a low power circuit, the reduction in leakage current becomes very important aspect while designing any IC. The leakage can be reduced by altering the threshold voltage. Further as the technology is scaled FinFET is the alternate for CMOS with increased control of gate over the channel. In this paper a FinFET based 7T SRAM cell is proposed which is faster in its operation and consumes less power. In order to further reduce the leakage power, FinFET based 7T SRAM cell is designed using self-controllable voltage level (SVL) techniques. In this paper, an 18 nm FinFET based SRAM cell is designed using SVL circuit to reduce the leakage current and power. The proposed design has the least leakage current of 16.56 nA and leakage power of 11.59 nW by using the combined technique of LSVL and USVL. All the circuit design and simulation have been done in Cadence Virtuoso using 18 nM FinFET technology. [ABSTRACT FROM AUTHOR]

This paper proposes a Reconfigurable In-Memory Advance Computing architecture using a novel 10 SRAM cell. In addition to basic logic operations, the proposed R-InMAC can also implement complex Boolean computing operations such as binary addition/subtraction, binary-to-gray, gray-to-binary conversion, 2's complement, less/greater than, and increment/decrement. Furthermore, content addressable memory (CAM) operation to search a binary string in a memory array is also proposed efficiently. It can search true and complementary data strings in a single cycle. The proposed R-InMAC architecture's reconfigurability allows it to be configured according to the needed operation and bit precision, making it ideal and energy-efficient. In addition, compared to the standard SRAM cells, the proposed 10T cell is suited for implementing the XNOR-based binary convolution operation required in Binary Neural Networks (BNNs) with improved latency of 58.89%. The optimized full adder of the proposed R-InMAC shows decrement in the area by 40%, static power by 28%, dynamic power by 55.2%, and latency by 25.3% as compared to conventional designs, making this work a promising candidate for modern edge AI compute in-memory systems. [ABSTRACT FROM AUTHOR]

This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T) SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based cross-coupled inverters comprise the storage cell of the proposed MST11T bit cell. In comparison with conventional inverters, ST-based inverters have sharp voltage transfer characteristics. As a result, the proposed bit cell's stability performance increases. The proposed SRAM cell's leakage power consumption is reduced because of the use of stacked N-type transistors. For the read operation of the proposed bit cell, the read decoupled technique is used. As a result, the read static noise margin (RSNM) has greatly improved. The proposed bit cell's write static noise margin (WSNM) is increased by adopting feedback-cutting methodology. The performance of the proposed bit cell is compared with that of conventional 6 T, conventional 8 T, Schmitt-trigger 10 T (known as ST2), modified PMOS-PMOS-NMOS-based cell core 10 T (MPPN10T), feedback-cutting 11 T (FC11T), Schmitt-trigger 11 T (ST11), and Schmitt-trigger 12 T (ST12T) cells. According to the simulation results, the proposed MST11T SRAM cell has RSNM of 2.42, 1.18, 1.71, 1.30, and 1.80 times higher when compared to 6 T, FC11T, ST2, MPPN10T, and ST12T, respectively. The WSNM of the proposed bit cell has been increased by 1.56, 2.44, 1.28, 1.71, 1.35, 1.52, and 1.02 times, respectively, over 6 T, 8 T, ST2, MPPN10T, FC11T, ST11T, and ST12T. Furthermore, the suggested cell has a read delay that is 1.32, 1.79, and 1.53 times lower than ST11T, FC11T, and ST12T, respectively. The proposed bit cell has a write delay that is 1.14 and 1.63 times lower than FC11T and ST11T, respectively. The proposed MST11T bit-cell consumes 3.74, 1.56, 4.59, 5.38, and 4.83 times less leakage power than the 8 T, ST2, MPPN10T, FC11T, and ST12 bit-cells, respectively. When compared to 8 T/ST2/MPPN10T/ST12T at 0.2 V supply voltage, the enhanced facts incur a 4.87/3.79/3.78/1.97 penalty in write delay. The figure of merit (FOM) is derived as a result of this extensive access to the revolutionary SRAM cell performance, i.e., offering greater values at a 0.2 V DC supply voltage. In addition, the paper examines the impact of manufacturing process and temperature changes on MST11T cell enactment, as well as the circuit robustness using HSPICE with 7-nm FinFET technology. [ABSTRACT FROM AUTHOR]

Low power cache memory in a system on chip is in high demand today. With the lowering of MOSFET's channel length, low-power SRAM design has become a more challenging task. This paper presents differential 8T SRAM cell with minimum power utilization. The proposed cell has one pair of transmission gate as access switches. Due to use of TG instead of pass gate access transistor its write access time (TWA) is short. The low power consumption of the cell is due to stacking effect. This paper compares design metrics of the proposed cell with conventional 6T (CON6T) and ZIGZAG 8T (ZG8T) SRAM cells. The proposed 8T SRAM cell shows 1.15×/1.17× improvement in TWA as compared to CON6T/ZG8T at a penalty of 2.65×/2× in read access time (TRA). The proposed cell consumes 3.22× less hold power compared to both CON6T and ZG8T SRAM cells. And the proposed cell consumes 4.41× (4.44×) less write power as compared to CON6T (ZG8T) SRAM cell. Our proposed cell takes 1.37× lower chip area as compared to ZG8T cell at the expense of 1.49× higher area as compared to CON6T SRAM cell. The proposed cell also achieves 1.5×/3× higher stability during write operation as compared to CON6T/ZG8T SRAM cell, respectively. Read static margin of the proposed cell is same as CON6T but 3.2× lower than ZG8T SRAM cell. [ABSTRACT FROM AUTHOR]

A CNFET-based nonvolatile 4CNFET2M resistive RAM (ReRAM) cell is proposed in this paper. In this design, four CNFETs are employed as high-speed, low power and high endurance switches while the two memristors constitute the memory element. In this paper, the proposed 4CNFET2M ReRAM has been compared with the standard 6T SRAM (S6T) cell and the contemporary 2T2M ReRAM cell. The proposed cell shows 1.68 ×/2.14 × shorter read delay (TRA) when compared to S6T/2T2M while exhibiting 4.16 × shorter write delay (TWA) than that of 2T2M @ VDD = 1 V. Moreover, at VDD = 1 V, it displays a 2.32 × narrower spread in TWA than 2T2M as well as 8.0 ×/7.25 × narrower spread in TRA than that of S6T/2T2M. The proposed cell consumes 2.57 × 106 ×/2.70 × lower hold power (HPWR) than that of S6T/2T2M at VDD = 1 V. In addition, it exhibits tolerance to variations in temperature as well as pitch and Vth of memristor. All this is achieved at a 32.44 × penalty in TWA when compared to S6T. The use of CNFET devices, which possess far superior electrical characteristics in comparison to traditional CMOS devices, integrated with memristor technology, paves the way for such major improvements in design metrics of the proposed cell. [ABSTRACT FROM AUTHOR]

With the enhancement of technology, the usage of electronics in various applications involving large memories for storing and processing data has increased. In this sort of application, SRAM is mainly used because of its high speed. Moreover, with the high usage of memory cells, power consumption has increased to a great extent. The current literature shows that the various parameters of SRAM, such as speed and power, need to be improved for memory cells used in object tracking applications. To improve these parameters, the architectures of SRAM must be combined with new techniques. In recent years, reversible circuits have gained extensive attention because of their low-power and low-speed characteristics. In this brief, a low-power high-speed reversible static RAM is proposed. The proposed SRAM has the combined features of data processing with low-power dissipation and high speed. The proposed architecture of SRAM yields better performance and is similar to traditional SRAM architecture in terms of delay. This paper also implements a 32 × 64 memory block for object tracking applications. This work is carried out with 45 nm CMOS technology. In the proposed design, transistors are made to operate in the weak inversion region through the use of the EKV model. The design proposed in this paper reduces garbage outputs by 60%, the quantum cost by 70%, and the quantum delay by 70% compared to the current architectures. The proposed design is simulated at different supply voltages to ensure that the power dissipation and delay of SRAM are proportional to the voltage supplied. [ABSTRACT FROM AUTHOR]

The von Neumann computing architecture faces considerable challenges (e.g., high throughput and improving energy efficiency) in developing artificial intelligence (AI) edge devices. In-memory computation (IMC) is a new computing paradigm to improve the energy efficiency and the throughput of dot product operations for AI edge devices. In this paper, a 6T2M hybrid SRAM (HSRAM)-based IMC macro is proposed that supports non-volatile storage and in-memory dot product (IMDP) operation. The HSRAM bit cell is designed using NMOS and memristor devices, which reduces the area overhead and improves the energy efficiency compared to prior SRAM-based IMC macro due to non-volatile storage capability. A 128 x 128 IMC macro based on HSRAM is designed in 65 nm technology. For normal memory operation, the read margin of the proposed HSRAM bit cell is improved by 84.1% compared to 4T2R ReRAM, and the write margin is enhanced by 44.01% compared to 8T SRAM. For IMDP operation, it can compute 128 parallel dot products on binary input and binary weight values with 500 MHz frequency and achieves the energy efficiency of 134.5 TOPS/W at VDD = 1V. According to Monte Carlo simulations, the IMDP operation has a standard deviation of 4.24 percent in accumulation, which equates to a classification accuracy of 96.71% on the MNIST dataset and an 82.51% on the CIFAR-10 dataset. [ABSTRACT FROM AUTHOR]

Reliability of Static Random Access Memories (SRAMs) is immensely affected by radiation induced soft errors. Multiple Cell Upsets (MCUs) are caused by these soft errors and this lead to data corruption in several SRAM cells. Error Correcting Codes are normally exploited to alleviate the effect of MCUs. Single Error Correction–Double Error Detection (SEC–DED) codes are not the appropriate preference against MCUs rather these codes are suitable for protecting SRAM cells against Single Cell Upset. Single Error Correction–Double Error Detection–Double Adjacent Error Correction (SEC–DED–DAEC) codes are more suitable due to increasing trends of single and double-adjacent errors in SRAM cells. In this paper, a new SEC–DED–DAEC code has been proposed which is proficient of correcting single and double-adjacent errors in SRAMs. Our newly proposed code has been termed as Single and Double-adjacent Error Correcting Code (SDECC). Proposed codecs have been designed by employing new parity check matrices for different word lengths which are frequently applied in memory. The mis-correction probability of proposed SDECC codes are up to 88.24% and 80.67% lesser for 2-random and 3-random bit errors respectively with respect to related existing designs. Proposed codecs have been replicated and synthesized in ASIC environment. It is observed that area and power consumption of the proposed codecs are reduced up to 8.93% and 21.47% compared to the recently published results respectively. [ABSTRACT FROM AUTHOR]

Cache memory is a key component for most microprocessors in embedded system. The increasing processing load has resulted in an upsurge in the demand for low power, high performance SRAM bit cells. Consequently, in this paper a 7T bit cell is designed for feature size 32 nm and 300 mV supply voltage. The improvement in the performance of the proposed cell is validated against the results obtained for pre-existing 6T, 7T, 8T, 9T, and 10T cells. The read and hold noise margin for the cell is obtained to be 96 and 68 mV respectively, whereas the static margin for the write operation is 170 mV. To perform a successful write operation, a pulse-width of 30 ns is utilized. The power analysis reveals that the proposed cell has minimal read/write power consumption. The leakage power for the cell is 8.4 pW and 1.2 pW for Q = '0' and '1' respectively. Tolerance analysis justifies that the cell maintains its functionality and yields credible outputs under process-voltage-temperature variations for static performance metrics. The layout for the proposed 7T cell occupies 0.584 µm2 area. This is 5.55% smaller than a single ended 6T. The area for other 7T counterparts, 8T, 9T, and 10T cells is larger than the proposed cell. [ABSTRACT FROM AUTHOR]

Portable applications and battery-operated devices require highly reliable, stable, and low-power nanometer-sized embedded cache static random access memory (SRAM) cells. The conventional 6-transistor (6 T) SRAM cell and its variants suffer from malfunctioning during the read/write operations, and instability, and are vulnerable to the multi-bit soft-error rate at scaled technology node and low supply voltage (VDD). In this regard, this paper proposes an 12 T SRAM cell with reliable functioning and reduced multi-bit soft-errors appropriate for low-power portable applications. This cell performs single-end bitline decoupled read operation and write data-dependent feedback-cutting-aware differential write operation to improve the read static noise margin (RSNM) and write static noise margin (WSNM), respectively. The presence of stack transistors in the cell core and read path, and also high virtual ground (VGND) minimize the leakage power dissipation. The proposed cell is compared with other state-of-the-art SRAM cells at VDD = 0.7 V and under harsh process, voltage, and temperature (PVT) variations. It offers at least 1.18X higher RSNM, 1.27X higher WSNM, and 2.02X lower leakage power dissipation. It also shows the second-best read power and incurs a penalty in write power. This cell shows at least 1.17X, 1.32X, and 1.04X smaller spread in read delay, RSNM, and WSNM, respectively, when subjected to PVT variations. In addition, the proposed cell eliminates the write half-select disturbance by employing a separate gate to drive the access transistors and thus column-interleaving structure and error correction coding can be applied to reduce multiple-bit upset and increase soft-error immunity. The soft-error in the proposed cell is reduced by at least 1.37X in critical charge. Generally, the proposed cell offers the best overall performance among all the compared cells by showing the highest proposed figure of merit. [ABSTRACT FROM AUTHOR]

The paper presents an SRAM macro capable of working down to 350 mV with programmable wordline boosting feature. Wordline boosting allows us to improve the performance while keep the supply voltage in sub-threshold region. The measurement results on a 16 kb macro achieves minimum energy consumption of 0.536 fJ/b at 400 mV and operating at 400 mV. In addition, the macro achieves 22% lower energy consumption under optimal boost condition with respect to no boost condition for the same operation speed. [ABSTRACT FROM AUTHOR]

In this paper, a new memristor based read decoupled (RD) 8T1M non-volatile SRAM (nvSRAM) cell is introduced. It uses source switch transistor to improve the write performance of the proposed cell. This strategy effectively deals with the write '1' problem of single bitline cells. The isolated read port improves the read performance by avoiding the memristor connection with internal node. The non-volatile operation is performed using one transistor and one memristor (1T1M) structure and avoids the complexity during store/restore operations. The mathematical modelling for write delay, read delay and power consumption are put forward. The performance of the proposed cell is compared with the existing RD nvSRAM cells through simulation at 32 nm technology node. Compared with the existing RD nvSRAM cells, the proposed cell shows an improvement of 27.45%, 37.03%, 45.98% in write margin, read margin and read delay respectively. The proposed cell shows significant reductions upto 96.52% and 56.75% in write power and leakage power consumption in comparison to existing RD counterparts. The 1T1M structure avoids the discharging the read bitline RBL during store operation and reduces the store energy consumption by 28.92%. [ABSTRACT FROM AUTHOR]

As technology advances, circuit density and complexity increases in integrated circuits which make the devices vulnerable to different types of manufacturing defects. In such cases, even the occurrence of a fault may be critical. Hence, ensuring Static random access memory (SRAM) reliability and quality with high priority is essential. In this paper, an innovative approach to SRAM testing—wavelet-based transient supply current testing with modified March sequence exploiting read equivalent stress (RES) is introduced for fault detection. The main contribution of this research work is the unique testing solution that ensures a minimum test time for the detection of open defects in SRAMs. In comparison with other techniques that solely rely on the hardware implementation for fault detection, the proposed technique reduces design parameters, such as the area overhead, power consumption, hardware complexity and performance overhead. The simulation results demonstrate that the proposed technique can provide high reliability and efficiency and reduce test time (25%) compared to other methods. A complete evaluation of the proposed technique in terms of the overall memory performance is presented in this work. The main objective of this study is to investigate the efficiency of wavelet-based transient current test in detecting all open defects targeted in this work in SRAMs amidst process variations. Moreover, the conventional test time of transient current test is minimized exploiting the effects of RES. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM) cell design has undergone extensive development to achieve good performance and low power consumption. This paper introduces an SRAM cell with ten carbon nanotube field effect transistors (CNTFETs) named 10 T CNTFET SRAM cell to help with that and to address the drawback of most SRAM cells caused by their poor stability during read operation. The Schmitt-trigger (ST)-based inverter and PPN-inverter are coupled back to back to create the novel SRAM cell structure. Additionally, single-ended writing, feed-back cutting, and single-ended reading are used in this novel SRAM cell. The single-ended writing technique and feed-back cutting method are used to their full potential to increase the write static noise margin (WSNM) of this 10 T CNTFET SRAM cell. The single-ended read mode of this 10 T CNTFET SRAM cell increases the read static noise margin (RSNM) as the storage nodes are not disturbed. The hold power, read power, WSNM, hold static noise margin (HSNM), RSNM, read delay, leakage power, and VDDmin of this 10 T CNTFET SRAM cell are 0.5527 nW, 1.8087 nW, 432.4 mV, 360 mV, 360 mV, 5.0651 pS, 0.276 nW, and 32.1 mV, respectively. To understand the performance of this introduced SRAM cell and several existing SRAM cells are simulated and the parameters are compared. A comparative study shows that the introduced cell is more stable than the other cells while consuming less power during reading and holding. Furthermore, the new cell reads much faster and has less VDDmin than the other bit cells. This research also documents how SRAM cell performance changes when the CNTFET parameters change. Using the 32 nm CNTFET model from Stanford University using the Hewlett simulation program with integrated circuit emphasis (HSPICE) simulation tool, the simulation is carried out. [ABSTRACT FROM AUTHOR]

Static random-access memories (SRAMs), which are the most ubiquitous in modern system-on-chips, suffer from high power dissipation and poor stability in advanced complementary metal–oxide–semiconductor (CMOS) technology due to continuous learning, which leads to increased short-channel effects (SCEs), thereby, leading to use of new nano-devices. The fin-shaped field-effect transistor (FinFET) with lots of impressive attributes like mitigated SCEs is an efficient replacement for CMOS to overcome the aforementioned concerns. In this regard, this paper aims to explore a novel single-bitline 9-transistor (SB9T) SRAM with bit-interleaving capability appropriate for low-power near-threshold operation in 7-nm FinFET technology. The relative performance of the proposed SB9T is estimated by comparing it with other seven contemporary SRAMs such as conventional 6 T, write–read enhanced 8T (WRE8T), transmission gate read decoupled 9T (TGRD9T), one-sided Schmitt-trigger 9T (ST9T), data-independent read port 10T (DIRP10T), PMOS-PMOS-NMOS-based cell core 10T (PPN10T), and feedback-cutting 11 T (FC11T) at a near-threshold supply voltage of 0.5 V. Simulation results inferred that the SB9T offers 1.77 × /1.36 × and 2.35 × /13.13 × /1.30 × improvement in read stability and writability compared to WRE8T/ST9T and 6 T/DIRP10T/PPN10T, respectively. Furthermore, it consumes the best dynamic read power, which is at least 1.50 × , the third-best dynamic write power, and the second-best static power. The proposed SB9T SRAM offers 2.89 × /2.37 × improvement in dynamic write power/static power, at the expense of 1.742 × area overhead, compared to 6 T. [ABSTRACT FROM AUTHOR]

This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor. This improves hold stability and leakage power dissipation. The read and write operations of the proposed cell are performed with the aid of separated paths and bitlines, lowering power consumption. The strong cell core and decoupled read path eliminate the read-disturbance issue in the proposed cell, resulting in read static noise margin (RSNM) enhancement. Furthermore, the feedback-cutting write-assist technique used in the proposed design mitigates the writing '1' issue; consequently, write static noise margin (WSNM)/write margin (WM) improves. To prove the superiority of the proposed SRAM cell in various performance metrics, it is compared with state-of-the-art SRAM cells, introduced as 6T, TG9T, 10T-P1, and SB11T, using HSPICE and 16-nm CMOS technology node taking into consideration the impact of the severe process, voltage, and temperature (PVT) variations. Obtained results at VDD = 0.7 V show that the proposed design offers the highest HSNM/RSNM/WSNM (or WM). The read/write delay of the proposed cell is 3.92X/2.37X higher than that of the 6T SRAM cell due to its single-ended reading/writing structure. However, in terms of power consumption, the proposed cell exhibits 1.64X/1.54X lower than that of 6T SRAM cell. Though the proposed cell occupies a 1.24X higher area compared with the 6T SRAM cell due to its higher count of transistor, it shows the highest proposed figure of merit among all the studied SRAM cells, which is 26.90X higher than that of 6T SRAM cell. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) is an emerging technology proposed in response to the limitations of CMOS technology. Moreover, static RAM (SRAM) is crucial for memory design, and efficient RAM design can play a significant role. This paper proposes a fault-tolerant QCA SRAM cell based on QCA three- and five-input majority gates. This cell is implemented on a single layer and does not require any rotated cell, which significantly improves the manufacturability and robustness of the design. Furthermore, our design can tolerate a single omission fault. The proposed 3-input majority gate improves complexity, area, and energy dissipation, on average, by 54%, 68%, and 67% in 1 Ek, respectively, as compared to its previous counterparts. The proposed fault-tolerant SRAM cell improves the complexity, area, and total energy dissipation by almost 13%, 25%, and 35% in 1 Ek, respectively, as compared to its state-of-the-art QCA-based single-layer fault-tolerant counterpart. [ABSTRACT FROM AUTHOR]

The revolution in technology is so fast that even silicon devices are not able to meet the current demand of high speed, low power, and minimal area. The CMOS SRAM cells are the ones, affected the most by the revolutionary scaling of the devices. Due to various limitations of CMOS in deep sub-micron, new devices have emerged. One such device is the transition metal dichalcogenide field-effect transistor (TMDFET) to have prominent properties. This paper presents a novel read decoupled feedback-cutting 9T (RDFC9T) SRAM cell with high static noise margins (SNMs). The 16 nm CMOS and TMDFET devices are being used to design and compare the proposed design, showing the superiority of the TMDFET-based design. Furthermore, to evaluate the comparative performance of the proposed RDFC9T SRAM cell, it has been compared with the published SRAM cells introduced as 6T, 10T-P1, HFSE9T, and SB11T redesigned by 10 nm TMDFET device at VDD=0.7 V. The suggested cell exhibits 3.20X and 1.71X/1.15X/5.26X higher read SNM and write SNM as compared to the 6T and 6T/HFSE9T/10T-P1 SRAM cells, respectively. The cell exhibits 1.11X/2.10X and 1.06X/1.30X smaller read delay (TRA) and write delay (TWA) than that of the HFSE9T/SB11T SRAM design, correspondingly. In terms of power performance, the RDFC9T cell shows 0.86X/0.68X and 0.56X/0.37X/0.35X less read power and write power than the SB11T/6T and SB11T/10T-P1/6T cell, respectively. Moreover, the proposed design shows robustness against harsh process variations and mitigates the half-select issues to support bit-interleaving architecture. Here, we have also shown the layout of the projected RDFC9T cell and a comparison with the published designs. [ABSTRACT FROM AUTHOR]

This paper presents a novel 9T static random access memory (SRAM) cell consisting of a single ended isolated read bit line with 2T read port for improving stability and a tail transistor for saving power. In the proposed design owing to the use of separate bitlines, the storing node voltage has not been affected during active mode operation. In the idle (hold) mode the static power dissipation of SRAM cell has been drastically reduced due to the formation of stack between tail transistor and internal latch. The proposed design has been verified by cadence virtuoso tool using UMC 65 nm CMOS technology. It provides a 42% and 34% improvement in write stability when compared to basic 6T and ultralow voltage (UV) 9T SRAM cells respectively. It has been observed that, the read stability is improved by 12% when compared to basic 6T SRAM cell and penalty of 10% when compared to UV 9T SRAM cell. A reduction of 22% in static power dissipation has also been observed in proposed design as compared to basic 6T SRAM cell when designed at same technology. This paper has also been proposed a mathematical modelling for validating the proposed design. [ABSTRACT FROM AUTHOR]

The technology advances from the micron level to the Nanometer level. This striking change in the technology with so many factors might influence the embedded device design and its performance. In the fast-growing technology, it is very difficult to find suitable algorithms to test embedded SRAM. It is noticed that while going to deep sub-nano technologies, the existing test methods may not fully satisfy the test results due to the increased number of faults and defects. Scale-down technologies have an impact on the parasitic effects, creating an additional source of faulty behavior, and making the existing test techniques less effective in detecting them. In this paper we propose a new method, taking the parasitic effect into the consideration, which gives the fault information along with its location. In the proposed method we have considered node-to-node open and short defects for different technologies (45 nm, 32 nm, and 7 nm). It is observed that the proposed test method gives 100% fault coverage which is independent of technology variation. [ABSTRACT FROM AUTHOR]

This paper presents an efficient and low-power quaternary static random-access memory (SRAM) cell based on a new quaternary inverter. For implementation, carbon nanotube field-effect transistors (CNTFETs) are used. Stacked CNTFETs are appropriately used in the proposed design to achieve a considerably low static power dissipation. The proposed SRAM has a more significant static noise margin due to its single quaternary digit line, and it is appropriate for MVL SRAM design as there are more than two stable states. The simulation results using Synopsys HSPICE with 32 nm Stanford comprehensive CNTFET model demonstrate the correct and robust operation of the proposed designs even in the presence of major process variations. In addition, the proposed SRAM cell is applied in a 4 × 4 SRAM array structure to demonstrate the efficiency of the proposed SRAM. The results indicate that the proposed design significantly lowers the power consumption and provides comparable static noise margins compared to the other state-of-the-art CNTFET-based circuits. [ABSTRACT FROM AUTHOR]

Static random access memory is a key component for most microprocessor-based digital devices. With the declining technology node and reducing supply voltage, it is essential to improve its performance. This paper proposes a seven transistor, single-ended, bit cell configuration. The performance of the cell are evaluated at 300 mV supply voltage. The hold/read noise margins for the proposed bit cell is fairly high at 98 mV each, while the write margin is 154 mV. The reliability of the cell is measured using Monte Carlo process variation and temperature variation analysis. The results obtained for the proposed cell are compared against various pre-existing 5T, 6T, 7T, and 8T cells to showcase the improvements achieved by the proposed 7T cell. The power consumption for the proposed cell is minimal amongst others and requires a pulse width of 13 and 5 ns to perform successful write and read operations, respectively. The above-stated enhancement is achieved for the layout area of 0.65 μm2. While the layout footprint for 5T, 6T1, 6T2, 7T1, 7T2, 7T3, 8T1, 8T2, and 10T cell are 0.66, 0.82, 0.048, 0.74, 0.82, 0.8, 0.84, 1.34, and 1.27 µm2, respectively. [ABSTRACT FROM AUTHOR]

In Static Random Access Memory (SRAM) that is most ubiquitous of portable devices, the power consumption is a major concern. The emerging nonvolatile device-based SRAM designs have shown reduced power consumption by enabling power down mode without the loss of data. This paper presents a novel nonvolatile SRAM cell that employs eight transistors and a single TiO2 memristor as a nonvolatile device. The proposed 8T1M has low write power consumption, low store/restore energy and does not require reset phase. The performance of the proposed cell is compared with existing 8 T nvSRAM cells to demonstrate its versatility over others. The proposed cell shows 99.7% and 47% reductions in write '0' power consumption and store/restore energy, respectively, with respect to existing 8 T nvSRAM counterparts, while the corresponding improvement in write margins and average store/restore delay is 69% and 70%. The results at different power supply and technology nodes are also captured to validate the impeccable performance of the proposed cell. [ABSTRACT FROM AUTHOR]

This paper presents Carbon Nanotube FET (CNFET) based ultra-low-power Schmitt trigger SRAM designs which can operate at voltage levels as low as 200 mV, with high Static Noise Margins (STM) of 100–120 mV. The hysteresis in the STM curve of the CNFET Schmitt SRAM has been achieved through proper adjustment of the threshold voltage V th of the different CNFETs used to implement the SRAM. The V th of the CNFET can be set to the required level by selecting the appropriate chiral vectors of the CNFET. The CNFET based SRAM consumes merely 3.2 pW of power as compared to 19.5 pW of power required by the same SRAM implemented with MOSFET devices. The CNFET SRAM also has an average propagation delay of 31 ps, which is significantly lower than the delay of 250 ns experienced in CMOS-based SRAM. A simplified multi- V th 6T CNFET SRAM design is also proposed, which consumes merely 0.1 pW of power, thus enabling a 99% reduction in total power consumption in contrast to the conventional CMOS SRAM design. The device characteristics of the CNFET has been benchmarked with 45 nm CMOS devices. The improvement in the performance of the CNFET based SRAMs can be attributed to the 10 times higher I ON : I OFF ratio and 18 times higher I ON : C GG ratio of the CNFET as compared to the MOSFETs. [ABSTRACT FROM AUTHOR]

All modern computational devices consist of ALU. With increase in complexity of software and the consistent shift of software towards parallelism, high speed processors with hardware support for time consuming operations such as multiplication would benefit. Smaller, compact devices such as IoT devices need to run software such as security software and be able to offload computation cost from the cloud. In this paper, a high speed 8-bit ALU using 18 nm FinFET technology is proposed. The arithmetic and logical unit consists of fast compute units such as Kogge Stone fast adder and Dadda multiplier along with basic logic gates. In this paper, an ALU with each compute unit optimized for speed is proposed, while responsibly consuming area. Dadda multiplier is of 8 × 8 architecture as opposed to conventional approach of 4 × 4 making it a true 8-bit ALU. Simulation and analysis is done using Cadence Virtuoso in Analog Design Environment. The transistor count of proposed design is 5298, the power consumption is 219 µW and maximum delay is 166.8 ps. The design is also expected to consume a maximum of one clock cycle for any computation. [ABSTRACT FROM AUTHOR]

Memory design is the most complex part of any electronic devices. There are many parameters either intrinsic or extrinsic effects the system. In the memory design some features should be focus like stability, leakage current and delay. These parameters play important role in terms of performance. There is a lot of degradation in performance while not using the system. In this paper we used MTCMOS tech for optimizing parameters like stability static power dissipation and delay. We characterized the parameters of conventional 6T, Asym8T Asym 9T. The main focus is on the Asym 9T because it had low static power dissipation low delay and high stability. We simulated Asym 9T on different values of the threshold values and β values. Asym 9T SRAM cell exhibits high stability with dual threshold voltage. [ABSTRACT FROM AUTHOR]

SRAMs are extensively used in system-on-chip designs. Embedded SRAMs occupy majority of the die area leading to increased power consumption. Although the performance of SRAM in finer technologies has remarkably improved, still cell stability and leakage power dissipation are major concerns at deep sub-micron regime. In this paper, a low leakage SRAM cell is proposed based on source-biased inverter. The source biased inverter uses two extra transistors to mitigate the leakage power without increasing the dynamic power. The proposed inverter gives leakage power reduction of 66.1 % at 100 ∘ C for 32 nm. The inverter is also simulated in 22 nm and 16 nm. The performance metrics like delay and power delay product are calculated. The source biased inverter is then used to replace the conventional inverters in 6T SRAM cell in 32 nm. The proposed 10T SRAM cell gives leakage power reduction of 86.24 % at 100 ∘ C and 90.88 % at 25 ∘ C respectively as compared to conventional 6T SRAM cell. Also, read and write bias-based assist technique is applied to improve the stability. The proposed 10T low leakage SRAM shows better stability compared to the conventional 6T SRAM cell. The performance improvement comes at the cost of four transistors. All simulations are carried out using H-spice simulator by using predictive technology models. [ABSTRACT FROM AUTHOR]

Due to the rapid technology scaling and increasing program/erase cycles, the raw bit error rate (RBER) in NAND flash memory keeps increasing rapidly. This dilemma seriously incurs reliability issues. The traditional error correction codes (ECCs) with stronger protection capability are usually equipped for all flash pages as a solution to maintain the mandatory yield and reliability levels. However, the growth of RBER is exponentially proportional to the number of induced P/E cycles and the distributions of errors are usually uneven. Therefore, the conventional uniform ECC protection based on the worst scenario of fault distributions might incur unnecessary hardware and latency overhead. Moreover, the overlong ECC check bits might be stored in two different flash pages. Therefore, two flash read/program operations are required for reading/programming a codeword. To cure these drawbacks, the ECC Caching (E3C) techniques are proposed in this paper. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. An ECC Cache containing the ECC CAM and the ECC SRAM is used for accessing and storing extra check bits, respectively. The corresponding repair flow and hardware architecture are also proposed. According to simulation results, we can enhance the reliability and yield of flash memories significantly with negligible hardware cost. [ABSTRACT FROM AUTHOR]

Optical computing, based on the photonic CMOS technology, may substantially improve the analog or digital processing capabilities, and expand silicon photonics markets. There are two types of optical computing: photon-assisted optoelectronic computing and quantum optical computing. The former requires no change in existing circuit designs. The latter may require new features in logic designs, so is suitable for newly developed sections that are connected and fully compatible with existing sub-5nm ULSI circuits. In this paper, we will discuss how to implement the coherent micro-holographic effects, generated by photonic CMOSFETs, for optical computers. [ABSTRACT FROM AUTHOR]

This paper introduces a 10T single-ended SRAM cell with high stability and low static power. The read static noise margin is augmented by using a Schmitt-trigger inverter and decoupling the storage node from the read bitline by adding one transistor. Since writing "1" is difficult in single-ended SRAM cells, using proper capacitive coupling and also extra pMOS transistor as an access transistor mitigates the problem. To evaluate read, write, and hold yields, we performed 10,000 Monto Carlo simulations in the 32-nm technology, and the results show our cell has 7.5×, 1.4×, and 1.1 × more yields than that of the conventional 6T SRAM cell. The proposed cell also has the least static power consumption. This amount is 1.5× less than the conventional 6T at the supply voltage of 0.5 V. [ABSTRACT FROM AUTHOR]

In aerospace applications, the conventional Static Random Access Memories (SRAMs) are facing high soft error problems like a single event upset. Several radiation-hardened based design (RHBD) like twelve-transistor (12T) Dice, 12T We-Quatro SRAM cells, etc., had been developed to address the soft error problems. But they all are consuming comparatively more total and static power with more delay and area. The 10T SRAM cell had been developed to reduce the power dissipation and area overhead. But the analysis of 10T cell shows a write failure at high-frequency. An RHBD 12T SRAM cell has been proposed in this paper. The proposed 12T SRAM cell consumes less total, and static power dissipation compared to 12T We-Quatro and 12T Dice cell, respectively. The critical charge and hold noise margin of the proposed SRAM cell have been improved compared to We-Quatro and Dice cell. The simulated result shows that the proposed SRAM cell has provided the less and comparable area, high write speed, and good writability under process variations. Finally, the Monte Carlo Simulation of SRAM cells under 45 nm CMOS technology validates the efficiency of the 12T proposed cell. [ABSTRACT FROM AUTHOR]

In this paper, eight different SRAM cells are studied and evaluated with a 65nm CMOS technology. The cells were designed with radiation-hardening-by-design approaches including schematic and layout techniques. The eight types of cells were placed into eight pages of an SRAM test chip. The alpha and proton irradiation demonstrated that the Dual Interlocked Cell (DICE) has the best radiation-tolerant performance, but requires the largest area. The 6T and 11T cells designed with charge cancellation techniques can reduce soft errors up to 2-3 times with less area overhead. Several DICE variants were developed with reduced area overhead and showed SEU resilience performance equivalent to DICE. Simulation results are also presented in this paper to validate the findings. [ABSTRACT FROM AUTHOR]

Static Random-Access Memories (SRAMs) have flourished in the memory market relying on their speed, power consumption and compatibility with standard CMOS process technology. Conventional SRAMs are characterized by volatility, limiting their role in applications where non-volatility is essential. Non-Volatile SRAMs (NVSRAMs) represent an appealing solution, where Resistive RAM (RRAM) can act as a non-volatile element for SRAM. RRAM relies on the basic physical phenomenon of operation called resistive switching. This paper presents different NVSRAM structures, while exploring their principle of operation. Also, a comparison in terms of area, speed, power consumption and design complexity is presented for three NVSRAM memory cells implemented in a 130-nm high voltage CMOS technology from STMicroelectronics. [ABSTRACT FROM AUTHOR]

Downlink (DL)-uplink (UL) coupled cell association scheme was adopted in 3rd generation (3G) homogeneous network and 4th generation (4G) heterogeneous network (HetNet). In the coupled cell association scheme, a user is associated to single base station (BS) in DL & UL based on the strongest received signal power (SRSP) in DL from a macro base station (MBS) and multiple small base stations (SBS) in HetNet. This is a sub-optimal solution for cell association as most of the users are associated to a MBS due to dominant transmit power and brings challenges like multiple interference issues and imbalanced user traffic load which leads to a degraded throughput in HetNet. In this paper, we investigate downlink uplink decoupled cell association scheme to address these issues and formulate a sum-rate maximization problem in terms of admission control, cell association and power allocation for MBS only, coupled and decoupled HetNet. The formulated optimization problem falls into class of a mixed integer non linear programming (MINLP) problem which is NP-hard and requires exhaustive search to find the optimal solution. However, computational complexity of the exhaustive search increases exponentially with the increase in number of users. Therefore, an outer approximation algorithm (OAA) is proposed as a solution to find near optimal solution with less computation complexity. Extensive simulations work has been done to evaluate the decoupled cell association scheme in HetNet vs the coupled cell association scheme in traditional MBS only and HetNet. Results show the effectiveness of decoupled cell association scheme in terms of KPIs, such as throughput, addressing user traffic load imbalances and number of users attached. [ABSTRACT FROM AUTHOR]

This paper presents a low leakage power 10T single-ended SRAM cell in the sub-threshold region that improves read, write, and hold stability. While at low voltages, the write-ability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the data-storage node from the read bit line by using only a single transistor. According to Simulations using HSPICE software in 10 nm FinFET technology, the read stability of the proposed cell is approximately 4.8× higher than the conventional 6T at 200 mV. Furthermore, the proposed cell is found to have the lowest static power dissipation, as it tends to be 4% lower than the standard six-transistor cell at this voltage. This study shows that the yield of the proposed cell is higher than 6σ in all operations, and supply voltages down to 200 mV. [ABSTRACT FROM AUTHOR]

Reading the memristor memory cell without changing its resistance state is one of the potential problems to be addressed in the memristor-based memory design. This paper presents a novel read scheme that achieves a non-destructive read operation, consumes less power, provides high endurance and adapts itself based on the process variations. The proposed scheme uses built-in self-tuning circuitry to obtain the optimum amplitude and width of the refresh pulse required to completely retrieve the state of the memristor after the read cycle. As the scheme uses refresh pulse only when needed, the scheme saves nearly 50% of average power when compared with a conventional fixed pulse read method. The self-tuning circuits are validated by a generic, accurate, and efficient "voltage threshold adaptive memristor" model. The validation results prove that the proposed tuning circuitry achieves optimum refresh pulse size under various read disturbance faults. [ABSTRACT FROM AUTHOR]

A novel 9T-SRAM architecture is proposed in this paper. It smartly integrates the source biasing and body-bias control schemes in designing an SRAM cell. The proposed cell consists of nine transistors with separate read/write ports. It uses a read word-line based body bias controller and two tail transistors in pull-down path to improve the design metrics. The main objective of the proposed architecture is to minimize the leakage current in an SRAM cell while improving the stability and reducing the read/write delays. The above design metrics of the circuit are compared with the conventional 6T, LP10T and WRE8T SRAM cells under process and temperature variations. It is observed that as compared to conventional SRAM, the proposed 9T SRAM architecture (8 × 16 arrays) reduces static power consumption by 98%, improves the read and write stability by 66.07 and 10.51% respectively. Again, the write delay is reduced to about 95% while read delay is minimized to about 64.1% under different body-bias voltages. [ABSTRACT FROM AUTHOR]

A hybrid on-chip approach based on the variants of soft computing techniques is proposed in this work to evaluate the performance metrics of a 6T static random access memory (SRAM) cell in 45-nm technology. The performance metric evaluated for the SRAM cell is the data retention voltage (DRV) with optimal memory requirements. Each of the SRAM memory cells intends the chip to possess low density but operates at high speed. This paper formulates a hybrid soft computing framework comprising a deep backpropagation neural network which trains the fuzzy inference system to determine the performance metrics of 6T SRAM cell. The weight and bias parameters of the deep learning neural framework are optimized through a cat swarm optimization algorithm so as to reduce the elapsed convergence time of the new hybrid soft computing model. Evaluation process is executed based on the driven outputs from deep learning model to the fuzzy inference system (FIS) module so as to achieve the best values of DRV. Data retention voltage plays a major role in reducing the substantial leakage current and static noise margin intends to retain the data without losing them. Deep backpropagation neural network gets trained with deep learning procedures and optimizes the rule parameters and membership parameters of the FIS design structure. The performance metric DRV under various constraints prove to be better and effective in comparison with the solutions from the existing literature works for the same configuration of 6T SRAM cell using 45-nm technology. [ABSTRACT FROM AUTHOR]

A Fully Differential Write Assist 10T (FDWA10T) SRAM cell has been proposed in this work. The various design metrics and their behavior under severe process variation have been analyzed in this paper and have been compared with other state-of-the-art designs - FD8T, SEDF9T, BI11T, WWL12T and D12T cells. The FDWA10T cell shows 1.47 × / 1.73 × / 2.09 × shorter T RA than that of D12T/BI11T/SEDF9T and 1.20 × / 1.59 × / 1.86 × / 4.33 × shorter T WA than that of D12T/WWL12T/SEDF9T/BI11T. In addition, it shows 1.05 × narrower spread in T RA than that of BI11T and 3.94 × higher RSNM than that of FD8T. A 4.10 × improvement in WSNM is also observed when compared to SEDF9T/D12T/WWL12T. The FDWA10T cell also exhibits 1.03 × / 1.03 × / 1.06 × / 2.09 × lower hold power ( H PWR ) consumption than that of D12T/FD8T/SEDF9T/WWL12T and consumes 1.14 × / 1.26 × / 1.23 × lesser area when compared to BI11T/WWL12T/D12T. These improvements are obtained at the cost of 1.50 × / 2.42 × longer T RA / T WA than that of FD8T, 6.4 × higher H PWR dissipation than that of BI11T and 1.10 × / 1.15 × higher area consumption than that of FD8T/SEDF9T. [ABSTRACT FROM AUTHOR]

We present a circuit-level technique of designing a lower write-power along with variability-resistant 9-MOFTET static random-access memory cell. Our proposed bitcell exhibits lower write-power consumption owing to reduction of activity factor and breakup of feedback path between the cross-coupled inverters during write operation. It exhibits higher read static noise margin (by 3.09 ×) compared with standard 6T SRAM cell @ minimum-area. LP9T shows higher static margin for write operation (by 41%) compared with 8T (S6T) @ iso-area (minimum-area). These improvements are achieved due to breakup of feedback path during the process of writing a bit on to the storage node. The paper investigates in detail the influence of variation in process related parameters, environmental parameters such as supply voltage and temperature on most of the important design parameters of the bitcell and compares the obtained simulation results with conventional 6-MOSFET (6T) and 8-MOSFET (8T) bitcells. It demonstrates its invariableness by showing 1.5 × tighter disperse in read time variability with a cost of 1.41 × higher read time compared with S6T @ minimum-area. It also exhibits 39% narrower disperse in read time variability in comparison to 8T @ iso-area. It draws lower power (2.06 ×) from supply voltage while flipping of stored data during write mode compared with standard 8T SRAM cell @ iso-area. It also compares key design metrics of LP9T with those of few other 9T SRAM cells found in the literature. This work also realizes the proposed design using CNFET. The CNFET-based design outperforms its CMOS counterpart in all respect. [ABSTRACT FROM AUTHOR]