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A 650-V/84-mΩ normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally-off gate control, and a 650-V normally-on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QG×RON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs. [ABSTRACT FROM AUTHOR]

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this article, we demonstrate a GaN-based gate driver with an overcurrent (OC) protection circuit and an undervoltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, the OC protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power devices. The OC protection is implemented with a separated sensing branch and blanking time controller, and the response time to an OC event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V, and its threshold voltage is especially tailored for the GaN integrated circuits. [ABSTRACT FROM AUTHOR]

The short circuit (SC) behavior of a newly developed GaN-HEMT/SiC-JFET cascode device is investigated in this work. The reverse leakage current through the drain-side PN junction (IR) of the SiC JFET under SC conditions is measured simultaneously during the SC event. IR of the SiC JFET increases to 6.4 A at the end of a 5-μs nondestructive SC pulse. The increase of IR during the SC pulse induces a turning point in the SC current waveform and a dramatic negative threshold voltage shift (>30 V) in the SiC JEFT, resulting in high transient drain-to-source voltage in the GaN HEMT. The underlying mechanism is associated with the increase of local potential in the P-type layer of the SiC JFET with inevitable spread resistance (RSPD). It is suggested that reducing RSPD can improve SC capability and high IR should be considered in SC failure mechanism analysis and the design of external gate resistance of the SiC JFET. [ABSTRACT FROM AUTHOR]

The threshold voltage (VTH) of an enhancement-mode Schottky-type p-GaN gate high-electron-mobility transistor (HEMT) is found to have a special dependence on the drain bias. The device commonly requires higher gate voltage to switch on the transistor from a high-drain-voltage off-state than what is expected from the static device characteristics. The reason behind the dynamic VTH has been proved to be the floating p-GaN layer, where charges could be stored and further influence VTH under different drain bias. In this article, a SPICE-compatible equivalent circuit model is presented according to the structure of Schottky-type p-GaN gate HEMTs. It features a floating node to imitate the charge storage process within the gate stack. Compared to conventional models, the proposed model could accurately predict the dynamic VTH characteristics and switching behaviors of power electronics circuits, where Schottky-type p-GaN gate HEMTs are deployed as power transistors. The phenomena related to the dynamic VTH, including the disappearance of Miller plateau, the overestimated false-turn-on problem, and the higher reverse conduction loss are evaluated with a half-bridge circuit and the merits of the proposed model are verified. [ABSTRACT FROM AUTHOR]

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p-GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on-resistance (RON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage (VTH), and no dynamic RON degradation. To identify its safe operation in the off-state with a high drain bias, the off-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. A relatively low off-state VM is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic VTH shift; and 2) suppress the increased dynamic off-state leakage current (IOFF) induced by on-state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn-on and 121 V/ns during turn-off is achieved. [ABSTRACT FROM AUTHOR]

A 1200-V/100-mΩ silicon carbide (SiC) junction field-effect-transistor (JFET)/ gallium nitride (GaN) high-electron-mobility-transistor (HEMT) hybrid power switch is demonstrated, which features a flip-chip copackaged cascode configuration incorporating a vertical SiC JFET and a lateral GaN-HEMT. The high-voltage SiC-JFET provides the high-voltage blocking capability while the low-voltage GaN-HEMT enables the normally-off gate control with superior switching characteristics. Compared to conventional SiC-JFET/Si-mosfet cascode devices, the SiC-JFET/GaN-HEMT cascode device exhibits fast switching speed, which has been validated by systematic characterizations including static/dynamic device-level measurements and board-level hard-switching tests. Meanwhile, the device is free from several notorious issues of high-voltage GaN power transistors such as dynamic on-state resistance degradation and threshold voltage shift. Such a wide-bandgap semiconductor-based hybrid switch is suitable to be deployed in high-power and high-efficiency power conversion systems. [ABSTRACT FROM AUTHOR]

We conducted reliability characterization under reverse-bias stress (i.e., stress at OFF-state with high VDS) on the E-mode GaN metal–insulator–semiconductor field-effect-transistors (MIS-FETs) with various substrate terminations. The MIS-FETs with floating substrate (FS) show worse threshold voltage (VTH) stability than that with a grounded substrate. A non monotonic dependence of VTH shifts and OFF-state time-to-breakdown (tbd) on the positive substrate bias (Vsub) was also observed. The underlying mechanisms are the different impacts of positive Vsub on the drift of electrons and holes during the long-term stress. An important indication is that positive-biased and FS terminations should be restricted at OFF-state in order to obtain good VTH stability in applications of the GaN MIS-FET. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage (I–V) characteristics and threshold voltage (${V}_{\text {TH}}$) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier. [ABSTRACT FROM AUTHOR]

Low-loss reverse-conducting normally- OFF double-channel AlGaN/GaN power transistor with the built-in Schottky barrier diode (SBD) has been systematically studied. This device features the MOS-gate section and SBD-anode section paralleled to an interdigital layout along the gate width direction. A common access region that conducts current at both forward and reverse ON-states is employed, which is beneficial to reduce the conduction loss. With a MOS-HEMT/SBD finger width of ${4}~\mu \text{m}/2~\mu \text{m}$ and a total width ratio of 2:1, the device exhibits a threshold voltage of +0.8 V at a drain current of ${10}~\mu \text{A}$ /mm and a low forward ON-resistance of $12.1~\Omega \cdot \text {mm}$. The Schottky metal contacts 2-DEG directly, which results in a low reverse turn-on voltage of −0.6 V (at −1 mA/mm) and low reverse ON-state voltage of −1.7 V (at −50 mA/mm). A leakage suppression MOS field plate (FP) is applied to shield the Schottky contact from the strong electric field, leading to a low OFF-state leakage current of 14 nA/mm at +100-V drain bias and a high breakdown voltage (BV) of +698 V. The finger width and the number of fingers should be optimized. A narrow finger width benefits the current sharing at the access region, while the increasing number of fingers introduces more Schottky depletion regions along the gate width direction that degrade ${R}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth. [ABSTRACT FROM AUTHOR]

We experimentally demonstrate a high-voltage low-standby power startup circuit for powering up the off-line switched-mode power supply (SMPS) during the startup period by exploiting monolithically integrated enhancement/depletion-mode metal–insulator–semiconductor high electron mobility transistors (E/D-mode MIS-HEMTs) fabricated on a GaN-on-Si power device platform. The E/D-mode MIS-HEMTs exhibit a threshold voltage of +1.2 and -11~V, respectively. The high-voltage D-mode device used in the demonstration features an OFF-state breakdown voltage of 640 V and a safe operating area with a thermal limitation of 11.6 W/mm, whereas the low-voltage E-mode device features a source-gate breakdown voltage of 98 V, satisfying the requirement of the startup circuit. The functionality of the startup circuit is successfully achieved with an input voltage range 10–200 V and a startup current of 1.08 mA. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the enhancement-mode (E-mode) LaLuO3 (LLO)-AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) fabricated using fluorine (F) plasma ion implantation with a gate-dielectric-first planar process. The E-mode MIS-HEMTs exhibit a threshold voltage (VTH) of 0.6 V, a peak transconductance of \sim193~mS/mm, a small hysteresis of 0.04 V in linear region characterized by a pulse-mode current-voltage measurement, and significantly suppressed current collapse under high-drain-bias switching conditions. X-ray photoelectron spectroscopy and secondary ion mass spectrometry analyses manifest that the negatively charged F ions penetrating into the (Al)GaN barrier layer serve as the primary VTH modulation mechanism, whereas the F ions in the fluorinated LLO film form chemical bonds with La/Lu atoms and become charge-neutral. The suppressed current collapse is verified as an advantageous byproduct of the F plasma ion implantation that also fluorinated the SiNx sidewalls in the vicinity of the gate electrode, and therefore, suppress electron injection to the gate-drain access region. [ABSTRACT FROM AUTHOR]

This paper presents a method with an accurate control of threshold voltages (Vth) of AlGaN/GaN high-electron mobility transistors (HEMTs) using a fluoride-based plasma treatment. Using this method, the Vth of AlGaN/GaN HEMTs can be continuously shifted from 4 V in a conventional depletion-mode (D-mode) AlGaN/GaN HEMT to 0.9 V in an enhancement-mode AlGaN/GaN HEMT. It was found that the plasma-induced damages result in a mobility degradation of two-dimensional electron gas. The damages can be repaired and the mobility can be recovered by a post-gate annealing step at 400 °C. At the same time, the shift in Vth shows a good thermal stability and is not affected by the post-gate annealing. The enhancement-mode HEMTs show a performance (transconductance, cutoff frequencies) comparable to the D-mode HEMTs. Experimental results confirm that the threshold-voltage shift originates from the incorporation of F ions in the AlGaN barrier. In addition, the fluoride-based plasma treatment was also found to be effective in lowering the gate-leakage current, in both forward and reverse bias regions. A physical model of the threshold voltage is proposed to explain the effects of the fluoride-based plasma treatment on AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

High-performance enhancement-mode AIGaN/GaN HEMTs (E-HEMTs) were demonstrated with samples grown on a low-cost silicon substrate for the first time. The fabrication process is based on a fluoride-based plasma treatment of the gate region and postgate annealing at 450 °C. The fabricated E-HEMTs have nearly the same peak transconductance (Gm) and cutoff frequencies as the conventional depletion-mode HEMTs fabricated on the same wafer, suggesting little mobility degradation caused by the plasma treatment. [ABSTRACT FROM AUTHOR]

Normally-off AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) on Si substrate were fabricated with the fluorine-based treatment technique. By employing a 20nmthick Al2O3 gate dielectric deposited by atomic layer deposition, the fabricated MOS-HEMT exhibits a large positive threshold voltage of + 3.5V, a maximum gate input voltage of 15V, a maximum saturate drain current of 5.3A and an off-state breakdown voltage of 402V. The high threshold voltage and the large input voltage swing is expected to improve the electromagnetic interference immunity and safety of AlGaN/GaN MOS-HEMT power switches. [ABSTRACT FROM AUTHOR]