Search

Improvement of the AlGaN/GaN high-electron mobility transistor's (HEMT's) off -state breakdown voltage is achieved by implanting ^19\F^+ ions at an energy of 50 keV and dose of \1 \times \10^12\ \cm^-2 under the gate region using \BF3 as the source. The charge state of the implanted fluorine ions changes from positive to negative in the AlGaN/GaN structure because of fluorine's strong electronegativity. The negative-charged fluorine ions at the back side of the two-dimensional electron gas can raise the energy barrier of the GaN buffer layer under the channel, effectively blocking the current injected from the source to the high-field region of the GaN channel when the HEMT is biased at off-state. The source-injected electrons, if not blocked, could flow to the high-field region and initiate a premature three-terminal off-state breakdown in a conventional AlGaN/GaN HEMT. A 38% improvement of the three-terminal off-state breakdown voltage and 40% improvement of the power figure-of-merit VBD-off^2/Ron are achieved in the enhanced back barrier HEMT. [ABSTRACT FROM AUTHOR]

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this article, we demonstrate a GaN-based gate driver with an overcurrent (OC) protection circuit and an undervoltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, the OC protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power devices. The OC protection is implemented with a separated sensing branch and blanking time controller, and the response time to an OC event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V, and its threshold voltage is especially tailored for the GaN integrated circuits. [ABSTRACT FROM AUTHOR]

In this article, the impacts of the off-state gate bias (VGS,OFF) on dynamic on-resistance (RON) are systematically investigated in commercial Schottky-type p-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed I–V system are adopted to evaluate the dynamic RON with various off-state gate and drain bias (VDS,OFF) under hard- and soft-switching conditions. More negative VGS,OFF can aggravate the dynamic RON degradation under both soft- and hard-switching, especially when switching with a high VDS,OFF. The impacts of VGS,OFF on switching transients and off-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The off-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

Short circuit (SC) capability of 650-V Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under single and repetitive tests is characterized in this article. The investigated devices exhibit strong capability under a single SC test, but weak capability under repetitive SC tests with a bus voltage of 400 V and a gate drive voltage of 6 V. The failure mechanism under repetitive SC tests is revealed through electrothermal simulation and microscale failure spot analysis. Thermal fatigue cracks are formed due to the high temperature spike and local temperature fluctuations in the narrow GaN channel and buffer layers, leading to weak repetitive SC capability. The unique heat confinement effect in the GaN layer plays an important role in the formation of high temperature spike and fatigue cracks. The withstand time in a single SC test is several hundred microseconds due to fast drain current drop that results from high temperature and, to a lesser degree, the dynamic threshold voltage shift during the SC transient. The device failure in a single-event SC test is related to heat diffusion to a wider region. Some guidelines are proposed for handling and improving the repetitive SC capability. [ABSTRACT FROM AUTHOR]

The threshold voltage (VTH) of an enhancement-mode Schottky-type p-GaN gate high-electron-mobility transistor (HEMT) is found to have a special dependence on the drain bias. The device commonly requires higher gate voltage to switch on the transistor from a high-drain-voltage off-state than what is expected from the static device characteristics. The reason behind the dynamic VTH has been proved to be the floating p-GaN layer, where charges could be stored and further influence VTH under different drain bias. In this article, a SPICE-compatible equivalent circuit model is presented according to the structure of Schottky-type p-GaN gate HEMTs. It features a floating node to imitate the charge storage process within the gate stack. Compared to conventional models, the proposed model could accurately predict the dynamic VTH characteristics and switching behaviors of power electronics circuits, where Schottky-type p-GaN gate HEMTs are deployed as power transistors. The phenomena related to the dynamic VTH, including the disappearance of Miller plateau, the overestimated false-turn-on problem, and the higher reverse conduction loss are evaluated with a half-bridge circuit and the merits of the proposed model are verified. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage (I–V) characteristics and threshold voltage (${V}_{\text {TH}}$) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier. [ABSTRACT FROM AUTHOR]

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations. [ABSTRACT FROM AUTHOR]

(Al)GaN recess-free normally OFF technology is developed for fabrication of high-yield lateral GaN-based power devices. The recess-free process is achieved by an ultrathin-barrier (UTB) AlGaN/GaN heterostructure that features a natural pinched-off 2-D electron gas channel. The top–down manufacturing technique overcomes the challenges in etching of AlGaN barrier with well-controlled depth and uniformity, which is especially attractive for fabrication of normally OFF GaN-based high-electron-mobility transistors (HEMTs) and metal–insulator–semiconductor HEMTs (MIS-HEMTs) on large-size Si substrate. With SiNx passivation grown by low-pressure chemical-vapor deposition, on-resistance of the UTB-AlGaN/GaN-based power devices can be significantly reduced. High-uniformity low-hysteresis normally OFF HEMTs and Al2O3/AlGaN/GaN MIS-HEMTs are successfully demonstrated on the UTB AlGaN/GaN-on-Si platform. It is also a compelling technology platform for manufacturing high-performance GaN-based lateral power diodes, and normally OFF p-(Al)GaN heterojunction field-effect transistors. [ABSTRACT FROM PUBLISHER]

Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance (RON) of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been investigated by using ramped and transient back-gating characterizations as well as TCAD simulations. High voltage applied to the conductive Si substrate can modulate 2DEG conductivity through the back-gate effect, whereby the dynamics of both acceptor and donor buffer traps are identified. Distinct buffer trapping and asymmetric vertical leakage under opposite top-to-substratebias polarities have been observed, which are attributed to the fundamentally different carrier injection/transport mechanisms. It is suggested that the energy barrier at the nucleation-layer/Si interface can limit the electron injection from Si substrate into the buffer stack and consequently influence the bufferrelated current collapse. [ABSTRACT FROM AUTHOR]

The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance $R_{{\rm{ON}}}$ and threshold voltage $V_{{\rm{TH}}}$ are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic RON is found to exhibit different dependence on the gate drive voltage $V_{{\rm{GS}}}$ from the static $R_{{\rm{ON}}}$. While reasonably suppressed at higher $V_{{\rm{GS}}}$ of 5 and 6 V, the degradation in dynamic RON is significantly larger at lower $V_{{\rm{GS}}}$ of 3–4 V, which is attributed to the positive shift in $V_{{\rm{TH}}}$ under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the $V_{{\rm{TH}}}$ shift on the dynamic $R_{{\rm{ON}}}$; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices. [ABSTRACT FROM AUTHOR]

We report the first gallium nitride (GaN)-based pulse width modulation (PWM) integrated circuit (IC) featuring monolithically integrated enhancement- and depletion-mode high electron mobility transistors and lateral field-effect rectifiers on the GaN smart power technology platform. The PWM IC is able to generate 1-MHz PWM signal with its duty cycle modulated effectively by a reference voltage ( Vc) over a wide range with good linearity. It features a 5 V supply voltage and is composed of a sawtooth generator and a comparator, both of which can be operated at 1 MHz and exhibit proper functionality over a wide temperature range (from 25 °C to 250 °C). This circuit demonstration further proves the feasibility of an all-GaN solution that features monolithically integrated peripheral gate control circuits and power switches for GaN power converters. An all-GaN solution would lead to a compact system with improved efficiency and enhanced reliability. [ABSTRACT FROM AUTHOR]

We investigate in detail the influence of AlN passivation on dynamic ON-resistance ( \(R_{\mathrm{{\scriptstyle ON}}}\) ) and electric field ( \(E\) -field) distribution in high-voltage AlGaN/GaN high electron mobility transistors (HEMTs) on a Si substrate based on pulsed \(I\) – \(V\) measurements, electroluminescence (EL) microscopy, and 2-D physics-based numerical device simulations. It is found that the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) increase has been significantly suppressed to below 10% at various temperatures ranging from −50 to 200 °C owing to the effective and robust compensation of deep acceptor-like trap states at the AlN/GaN (passivation/cap) interface by the additional positive polarization charges induced in the epitaxial AlN thin passivation layer grown in a plasma-enhanced atomic layer deposition system. To the best of our knowledge, this is the first time that highly suppressed current collapse in an AlGaN/GaN HEMT on a Si substrate within a wide temperature range is ever reported. By monitoring the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) for 100 consecutive 133-kHz switching cycles, its variation is observed to be less than 2.5%, indicating excellent stability of the passivation effectiveness. The electric field in an AlN-passivated device is found to be well confined at the drain-side gate edge, as shown in EL measurement and numerical simulation results. This phenomenon directly suggests that the virtual gate effect arising from surface trap charging has been effectively alleviated by the AlN passivation technique. [ABSTRACT FROM AUTHOR]

In this paper, a surface potential-based terminal charge and capacitance model, including parasitic components for AlGaN/GaN HEMTs is developed. First, by solving the charge control equations, the sheet charge density in the channel is modeled with a close-form expression. Then, using this result, based on the surface potential definition, the intrinsic terminal charges and capacitances are derived consistently with current model. Finally, by introducing parasitic components, the capacitances for the full structure of the HEMT devices are given. The model is evaluated step-by-step with good agreements compared with the TCAD simulations and the experimental data. Meanwhile, the effects of bulk traps and surface traps in the capacitances are analyzed. The complete model, including currents and capacitances has been implemented in i-MOS platform for evaluations and circuit simulations. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the enhancement-mode (E-mode) LaLuO3 (LLO)-AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) fabricated using fluorine (F) plasma ion implantation with a gate-dielectric-first planar process. The E-mode MIS-HEMTs exhibit a threshold voltage (VTH) of 0.6 V, a peak transconductance of \sim193~mS/mm, a small hysteresis of 0.04 V in linear region characterized by a pulse-mode current-voltage measurement, and significantly suppressed current collapse under high-drain-bias switching conditions. X-ray photoelectron spectroscopy and secondary ion mass spectrometry analyses manifest that the negatively charged F ions penetrating into the (Al)GaN barrier layer serve as the primary VTH modulation mechanism, whereas the F ions in the fluorinated LLO film form chemical bonds with La/Lu atoms and become charge-neutral. The suppressed current collapse is verified as an advantageous byproduct of the F plasma ion implantation that also fluorinated the SiNx sidewalls in the vicinity of the gate electrode, and therefore, suppress electron injection to the gate-drain access region. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a 253% improvement in the off-state breakdown voltage (BV) of the lattice-matched \In0.17\Al0.83 \N/GaN high-electron-mobility transistors (HEMTs) by using a new Schottky-contact technology. Based on this concept, the Schottky-source/drain and Schottky-source (SS) InAlN/GaN HEMTs are proposed. The proposed InAlN/GaN HEMTs with an LGD of 15 \mu\m showed a three-terminal BV of more than 600 V, while the conventional InAlN/GaN HEMTs of the same geometry showed a maximum BV of 184 V. Without using any field plate, the BV of 650 V was measured in the SS InAlN/GaN HEMTs with LGD = \15\ \mu\m, which is the highest BV ever achieved on InAlN/GaN HEMT. The corresponding specific on-resistance (Rsp, on) is as low as 3.4 \m\Omega \cdot \cm^2. A BV of 118 V was also obtained in SS InAlN/GaN HEMTs with LGD = \1\ \mu\m, which is the highest BV in GaN-based HEMTs featuring such a short LGD with GaN buffer. The improvement of the BV relies on the effective suppression of source carrier injection into the GaN buffer under the SS due to the smooth metal morphology and elimination of metal spikes in the Schottky metallization. [ABSTRACT FROM AUTHOR]