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This brief discusses the limitation of previously published statistical decision feedback equalizer (DFE) models when residual inter-symbol interference (ISI) is present and proposes a method that overcomes this limitation. The paper presents an accurate closed-form expression for the DFE with residual ISI and additive white Gaussian noise (AWGN). The analysis is extended to 4-level pulse amplitude modulation (PAM-4) to cover serial links of current interest. The results verify that the proposed model estimates an accurate bit error rate (BER). [ABSTRACT FROM AUTHOR]

This work presents a RISC-V system-on-chip (SoC) with eight application cores containing programmable-precision vector accelerators. The SoC is built by using a generator-based design methodology, which enables the integration of open-source and project-specific building blocks to develop differentiated functionality. The digital component generators use Chisel, the analog component generators use the Berkeley Analog Generator (BAG), and the physical design flow is implemented with Hammer. The chip totals 125 M gates and is implemented in a 16-nm finFET process. The vector accelerator achieves peak energy efficiency per task of 209 half-precision, 92 single-precision, and 56 double-precision GFLOPs/W for a matrix multiplication kernel at 0.55 V and 339 MHz. [ABSTRACT FROM AUTHOR]

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process. [ABSTRACT FROM AUTHOR]

This article presents a 71–86 GHz 16-element array receiver application-specified integrated circuit (ASIC) for Massive multiple-input–multiple-output (MIMO) wireless uplink, featuring a multiple-output analog beamformer (BF) supporting up to 16 spatially multiplexed users at the same time. The ASIC includes 16 direct-conversion mixer-first RX front-ends, local oscillator (LO) generation and distribution, and a $16\times 16$ fully connected baseband analog beamformer, which derives each user stream as a linear combination of all the 16 antennas. The 16 mm2 28 nm CMOS ASIC is packaged on an organic interposer including a linear patch antenna array. Over-the-air measurements demonstrate up to 2 Gb/s single-user data-rate, and four simultaneous links at 500 Mb/s each, with number of users and data rate only limited by setup constraints. Circuits are optimized for low power consumption in order to enable scaling to massive arrays, and consumes 1.7 W total power, for a power figure of 7 mW/antenna/user. [ABSTRACT FROM AUTHOR]

A 61-MHz Pierce oscillator constructed in 0.35- $\mu \text{m}$ CMOS technology and referenced to a polysilicon surface-micromachined capacitive-gap-transduced wine-glass disk resonator has achieved phase noise marks of −119 dBc/Hz at 1-kHz offset and −139 dBc/Hz at far-from-carrier offsets. When divided down to 13 MHz, this corresponds to −132 dBc/Hz at 1-kHz offset from the carrier and −152 dBc/Hz far-from-carrier, sufficient for mobile phone reference oscillator applications, using a single MEMS resonator, i.e., without the need to array multiple resonators. Key to achieving these marks is a Pierce-based circuit design that harnesses a MEMS-enabled input-to-output shunt capacitance more than $100\times $ smaller than exhibited by macroscopic quartz crystals to enable enough negative resistance to instigate and sustain oscillation while consuming only $78~\mu \text{W}$ of power—a reduction of $\sim 4.5\times $ over previous work. Increasing the bias voltage of the resonator by 1.25 V further reduces power consumption to $43~\mu \text{W}$ at the cost of only a few decibels in far-from-carrier phase noise. This oscillator achieves a 1-kHz-offset figure of merit (FOM) of −231 dB, which is now the best among published chip-scale oscillators to date. A complete linear circuit analysis quantifies the influence of resonator input-to-output shunt capacitance on power consumption and predicts further reductions in power consumption via reduction of electrode-to-resonator transducer gaps and bond pad sizes. The demonstrated phase noise and power consumption posted by this tiny MEMS-based oscillator are attractive as potential enablers for low-power “set-and-forget” autonomous sensor networks and embedded radios. [ABSTRACT FROM AUTHOR]

A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of $25\times $ , $27\times $ , and $32\times $ subsampling successive approximation register (SAR) ADCs acquire signal with ~5.4–6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal location estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW. [ABSTRACT FROM AUTHOR]

A single-output, band selecting interposer is designed to combine three identical all-digital CMOS transmitter (Tx) chips. The open-drain CMOS Txs are flip-chip connected to the primary windings of three frequency selecting transformers realized on a single PCB interposer. The secondary windings of the three transformers are connected in series and they share a single output. Across 0.4 to 4 GHz, a peak power higher than 22.9 dBm is achieved collectively by the three sub-Txs with a drain efficiency (DE) better than 25%. The peak powers/DE of the three sub-Txs are 28.6 dBm/50%, 27.4 dBm/49%, and 24.7 dBm/34%, at 0.85, 2.1, and 3 GHz, respectively. This paper further demonstrates that the band selection can be achieved via reconfiguring the CMOS inverse Class-D switching power amplifiers. As demonstrated via continuous wave and 64-quadratic-amplitude modulation, WLAN, and LTE modulation tests, the reconfigurable Tx package exhibits high power and efficiency across all supported bands. [ABSTRACT FROM AUTHOR]

A 700-MHz to 1.6-GHz RF power digital-to-analog converter with programmable integrated harmonic cancellation and mixed-signal filtering is presented. Harmonic cancellation is implemented by splitting the power amplifier (PA) into segments, driving different segments of the PA with phase-shifted versions of the local oscillator (LO) signals, and summing at the output. Mixed-signal filtering is realized in a similar fashion but with segments driven with delayed versions of the input data. The phase shift and data delays are reconfigurable and implemented to operate across a wide frequency range. To boost efficiency, 25% duty cycle LO signals are used. A technique to correct for IQ constellation distortion induced by these 25% duty cycle LO signals is introduced and verified in measurements. The transmitter (TX) operates at a maximum sample rate of 500 MSa/s and achieves an output power of 25.6 dBm for an output load of 100 $\Omega $ when harmonic cancellation is enabled. The TX demonstrates 24–42 dB of 3rd harmonic cancellation for continuous wave signals across a 700-MHz to 2-GHz frequency range, achieving an HD3 as low as −57 dB. The TX achieves an HD3 reduction of 33 dB and an 18-dB notch at 40-MHz offset with 20-MHz long-term evolution data. [ABSTRACT FROM AUTHOR]

Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset, and the resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The proposed 65-nm CMOS transceiver operates at 60 Gb/s with an eye opening of 30% UI and consumes 288 mW while equalizing 21 dB of loss at 30 GHz over a 0.7-m Twinax cable. [ABSTRACT FROM AUTHOR]

This paper demonstrates a wideband CMOS all-digital polar transmitter with flip-chip connection to three high-density-interconnection PCB interposers. The interposers are designed to extract power from a CMOS open-drain inverse Class-D power amplifier core. For a wide frequency range from 0.7 to 3.5 GHz, continuous-wave output power higher than 25.5 dBm and drain efficiency (DE) above 40% are demonstrated. The low-band package achieves a peak power of 29.2 dBm at 1.1 GHz with DE of 60%, the mid-band package outputs 28.8 dBm at 1.5 GHz with DE of 56%, and the high-band package generates 26 dBm at 3 GHz with DE of 49%. The amplitude modulation (AM) is achieved by digitally modulating the switch conductance of the inverse Class-D core, and the on-chip phase modulation is achieved by digitally weighing the in-phase and quadrature bias currents in the IQ mixer. Detailed modulation tests, involving 64 quadrature amplitude modulation (QAM) and 20-MHz WLAN and LTE signals, exhibit excellent power and efficiency at 0.6, 1.2, 1.8, 2.4, 3, and 3.6 GHz. The associated specifications on spectral masks and error vector magnitudes are satisfied. [ABSTRACT FROM AUTHOR]

This paper demonstrates a wideband CMOS all-digital polar transmitter with flip-chip connection to three high-density-interconnection PCB interposers. The interposers are designed to extract power from a CMOS open-drain inverse Class-D power amplifier core. For a wide frequency range from 0.7 to 3.5 GHz, continuous-wave output power higher than 25.5 dBm and drain efficiency (DE) above 40% are demonstrated. The low-band package achieves a peak power of 29.2 dBm at 1.1 GHz with DE of 60%, the mid-band package outputs 28.8 dBm at 1.5 GHz with DE of 56%, and the high-band package generates 26 dBm at 3 GHz with DE of 49%. The amplitude modulation (AM) is achieved by digitally modulating the switch conductance of the inverse Class-D core, and the on-chip phase modulation is achieved by digitally weighing the in-phase and quadrature bias currents in the IQ mixer. Detailed modulation tests, involving 64 quadrature amplitude modulation (QAM) and 20-MHz WLAN and LTE signals, exhibit excellent power and efficiency at 0.6, 1.2, 1.8, 2.4, 3, and 3.6 GHz. The associated specifications on spectral masks and error vector magnitudes are satisfied. [ABSTRACT FROM PUBLISHER]

An active transmitter (TX) cancellation scheme enabling integration of the antenna interface for frequency division duplex systems is presented. A replica of the TX current is synthesized in shunt with the receiver (RX) by a digital-to-analog converter (DAC). The replica DAC virtually shorts out the TX signal at the RX input while having minimal impact on the TX insertion loss. Propagation of the TX phase noise in the RX band is analyzed and shown to be feed-forward cancelled in the proposed system. A prototype chip including integrated TX, measurement RX, and cancellation circuits, operating on a single-shared antenna, is implemented in 65-nm CMOS. The cancellation replica demonstrates > 50 dB cancellation of a +12.6 dBm peak 20-MHz TX signal across a wide range of center frequencies and up to 5:1 voltage standing-wave ratio at the antenna interface. The RX is able to down-convert the RX signal at 40-MHz offset with < 4.3 dB noise figure degradation in the presence of the residual TX signal. [ABSTRACT FROM PUBLISHER]

Time-division duplex (TDD) systems rely on off-chip transmit/receive (T/R) switches to isolate the RX from the high-output power of the TX, while existing on-chip T/R switching solutions are narrow-band or high loss. This paper presents a wideband integrated T/R switching technique that eliminates the conventional, lossy series T/R switch from the signal path. The system reconfigures the PA as an LNA during the receive mode, and utilizes only DC mode control switches to enable TDD co-existence. To demonstrate this technique, a polar transmitter that can be re-purposed into a common-gate LNA is implemented in 65-nm CMOS. With an integrated front-end balun transformer, the transmitter achieves 20-dBm peak output power with 32.7% peak drain efficiency. In the receive mode, the PA is reconfigured into a wideband 3.4–5.4-GHz LNA achieving −6.7-dBm P1dB, and 5.1-dB noise figure. [ABSTRACT FROM AUTHOR]

This paper presents a RISC-V system-on-chip (SoC) with integrated voltage regulation, adaptive clocking, and power management implemented in a 28 nm fully depleted silicon-on-insulator process. A fully integrated simultaneous-switching switched-capacitor DC–DC converter supplies an application core using a clock from a free-running adaptive clock generator, achieving high system conversion efficiency (82%–89%) and energy efficiency (41.8 double-precision GFLOPS/W) while delivering up to 231 mW of power. A second core serves as an integrated power-management unit that can measure system state and actuate changes to core voltage and frequency, allowing the implementation of a wide variety of power-management algorithms that can respond at submicrosecond timescales while adding just 2.0% area overhead. A voltage dithering program allows operation across a wide continuous voltage range (0.45 V–1 V), while an adaptive voltage-scaling algorithm reduces the energy consumption of a synthetic benchmark by 39.8% with negligible performance penalty, demonstrating practical microsecond-scale power management for mobile SoCs. [ABSTRACT FROM AUTHOR]

This review focuses on recent directions stemming from work by the authors and collaborators in the emerging field of neurotechnology. Neurotechnology has the potential to provide a greater understanding of the structure and function of the complex neural circuits in the brain, as well as impacting the field of brain–machine interfaces (BMI). We envision ultralow-power wireless neural interface systems that are life-lasting, fully integrated, and that supports bidirectional data flow with high bandwidth. Moreover, we believe in the importance of building neural interface technology that is truly tetherless, has a very small recording footprint, and little to no mechanical coupling between the sensor and the external world. We believe these developments will impact both neuroscience and neurology, revealing fundamental insight about how the nervous system functions in health and disease. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to the best papers taken from the analog, data converter, RF, wireless, and wireline communications sessions at the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, in 2016. Selecting a subset of papers from these high-quality sessions proved to be a difficult task. However, we believe that the papers included in this issue highlight interesting innovations seen at the conference. [ABSTRACT FROM AUTHOR]

Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals—this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies. [ABSTRACT FROM PUBLISHER]

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC–DC switches, DC–DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices. [ABSTRACT FROM PUBLISHER]

The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to complete large, complex designs on schedule using traditional rigid development flows. This article presents an agile hardware development methodology, which the authors adopted for 11 RISC-V microprocessor tape-outs on modern 28-nm and 45-nm CMOS processes in the past five years. The authors discuss how this approach enabled small teams to build energy-efficient, cost-effective, and industry-competitive high-performance microprocessors in a matter of months. Their agile methodology relies on rapid iterative improvement of fabricatable prototypes using hardware generators written in Chisel, a new hardware description language embedded in a modern programming language. The parameterized generators construct highly customized systems based on the free, open, and extensible RISC-V platform. The authors present a case study of one such prototype featuring a RISC-V vector microprocessor integrated with a switched-capacitor DC-DC converter alongside an adaptive clock generator in a 28-nm, fully depleted silicon-on-insulator process. [ABSTRACT FROM AUTHOR]

Large arrays of radios have been exploited for beamforming and null steering in both radar and communication applications, but cost and form factor limitations have precluded their use in commercial systems. This paper discusses how to build arrays that enable multiuser massive multiple-input–multiple-output (MIMO) and aggressive spatial multiplexing with many users sharing the same spectrum. The focus of the paper is the energy- and cost-efficient realization of these arrays in order to enable new applications. Distributed algorithms for beamforming are proposed, and the optimum array size is considered as a function of the performance of the receiver, transmitter, frequency synthesizer, and signal distribution within the array. The effects of errors such as phase noise and synchronization skew across the array are analyzed. The paper discusses both RF frequencies below 10 GHz, where fully digital techniques are preferred, and operation at millimeter (mm)-wave bands where a combination of digital and analog techniques are needed to keep cost and power low. [ABSTRACT FROM PUBLISHER]

We present a miniaturized portable ultrasonic imager that uses a custom ASIC and a piezoelectric transducer array to transmit and capture 2-D sonographs. The ASIC, fabricated in 0.18 \mum 32 V CMOS process, contains 7 identical channels, each with high-voltage level-shifters, high-voltage DC-DC converters, digital TX beamformer, and RX front-end. The chip is powered by a single 1.8 V supply and generates 5 V and 32 V internally using on-chip charge pumps with an efficiency of 33% to provide 32 V pulses for driving a bulk piezoelectric transducer array. The assembled prototype can operate up to 40 MHz, with beamformer delay resolution of 5 ns, and has a measured sensitivity of 225 nV/Pa , minimum detectable signal of 622 Pa assuming 12 dB SNR (4\sigma larger than the noise level), and data acquisition time of 21.3 ms. The system can image human tissue as deep as 5 cm while consuming less than 16.5 \muJ per pulse-echo measurement. The high energy efficiency of the imager can enable a number of consumer applications. [ABSTRACT FROM PUBLISHER]

Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc-dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion efficiency. We propose a dynamic voltage and frequency scaling scheme with SC converters that achieves high converter efficiency by allowing the output voltage to ripple and having the processor core frequency track the ripple. Minimum core energy is achieved by hopping between different converter modes and tuning body-bias voltages. A multicore processor model based on a 28-nm technology shows conversion efficiencies of 90% along with over 25% improvement in the overall chip energy efficiency. [ABSTRACT FROM AUTHOR]

A 65 nm CMOS 4.78 mm 2 integrated neuromodulation SoC consumes 348 µA from an unregulated 1.2 V to 1.8 V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50 Hz and engaging two stimulators with a pulse width of 250 µs/phase, differential current of 150 µA, and a pulse frequency of 100 Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date. [ABSTRACT FROM AUTHOR]

Emerging applications in brain–machine interface systems require high-resolution, chronic multisite cortical recordings, which cannot be obtained with existing technologies due to high power consumption, high invasiveness, or inability to transmit data wirelessly. In this paper, we describe a microsystem based on electrocorticography (ECoG) that overcomes these difficulties, enabling chronic recording and wireless transmission of neural signals from the surface of the cerebral cortex. The device is comprised of a highly flexible, high-density, polymer-based 64-channel electrode array and a flexible antenna, bonded to 2.4 mm × 2.4 mm CMOS integrated circuit (IC) that performs 64-channel acquisition, wireless power and data transmission. The IC digitizes the signal from each electrode at 1 kS/s with 1.2 μV input referred noise, and transmits the serialized data using a 1 Mb/s backscattering modulator. A dual-mode power-receiving rectifier reduces data-dependent supply ripple, enabling the integration of small decoupling capacitors on chip and eliminating the need for external components. Design techniques in the wireless and baseband circuits result in over 16× reduction in die area with a simultaneous 3× improvement in power efficiency over the state of the art. The IC consumes 225 μW and can be powered by an external reader transmitting 12 mW at 300 MHz, which is over 3× lower than IEEE and FCC regulations. [ABSTRACT FROM PUBLISHER]

We report a mechanically enhanced inkjet-printed microelectromechanical (MEM) relay with a U-bar-shaped cantilever by exploiting the coffee-ring effect. The printed cantilever shape, especially the effective thickness caused by the elevated walls, can be controlled during the drying process by outward convective flow of silver nanoparticles. This enhances mechanical stiffness to efficiently produce a strongly suspended cantilever that is immune to collapse- and curling-related failures. This approach to enhancing cantilever stiffness is unique to printing-based processes using metalnanoparticle inks and is not feasible for conventional photolithography processes. The resulting printed MEM relays show a pull-in voltage of only 6.6 V and an on/off ratio of 108 with extremely low on-state resistance (~14.3 Ω) and off-state leakage that is comparable to those of conventional silicon-based MEM relays. [ABSTRACT FROM AUTHOR]

This paper describes a mixed-signal I/Q 32-coefficient receive-side feedforward equalizer (RX-FFE) and 100-coefficient decision feedback equalizer (DFE) for a 60 GHz baseband. Integrated in 65 nm LP CMOS with variable gain amplifiers (VGA), analog phase rotator (PR), and clock generation and phase adjustment circuits, the I/Q equalizer supports 60 GHz WiGig non-line-of-sight (NLOS) channels with > 12 ns of delay spread while consuming 66 mW from a 1.2 V supply at 8 Gb/s. Energy-efficient equalization is achieved by the RX-FFE using a proposed switching matrix architecture, and by implementing the multi-coefficient FFE-DFE summing with cascoded current integration. [ABSTRACT FROM AUTHOR]

This paper presents a 12.8 GS/s 32-way hierarchically time-interleaved SAR ADC with 4.6 ENOB in 65 nm CMOS. The prototype utilizes hierarchical sampling and cascode sampler circuits to enable greater than 25 GHz 3 dB effective resolution bandwidth (ERBW). We further employ a pseudo-differential SAR ADC to save power and area. The core circuit occupies only 0.23 mm 2 and consumes a total of 162 mW from dual 1.2 V/1.1 V supplies. The design achieves a SNDR of 29.4 dB at low frequencies and 26.4 dB at 25 GHz, resulting in a figure-of-merit of 0.79 pJ/conversion-step. As will be further described in the paper, the circuit architecture used in this prototype enables expansion to 25.6 GS/s or 51.2 GS/s via additional interleaving without significantly impacting ERBW. [ABSTRACT FROM AUTHOR]

A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A flat signal transfer function is chosen to support wide-frequency-range radios. A multilevel (two-bit) nonreturn-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier, guarantees a highly linear front end. For a 4 MHz signal, the peak SNDR of the receiver exceeds 68 dB and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of +10 dBm is achieved while dissipating only 40 mW from 1.1 V/1.5 V supply voltages. [ABSTRACT FROM AUTHOR]