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This brief presents four small-area SAR ADCs with a resolution from 8 to 11 bits. Two area-saving techniques are utilized. First, the DAC layout is implemented with custom designed unit-length capacitors, which are optimized for each resolution to minimize the chip area. Second, dynamic logic is applied to the 8-bit design to further reduce the number of transistors and save area. Fabricated in 65 nm CMOS, the 8/9/10/11-bit SAR ADCs only occupy $20\times 21\,\,\mu \text{m}$ , $20\times 36\,\,\mu \text{m}$ , $36\times 36\,\,\mu \text{m}$ and $36\times 36\,\,\mu \text{m}$ , respectively. At 10 MHz sampling rate, their measured ENOB is 7.5, 8.3, 9.1 and 9.8 bits with an SFDR of 65.4 dB, 67.4 dB, 78.0 dB and 76.5 dB, respectively. Compared to prior-art, these designs achieve the smallest areas for the achieved ENOBs. [ABSTRACT FROM AUTHOR]

This article presents a bioinspired, event-driven neuromorphic sensing system (NSS) capable of performing on-chip feature extraction and “send-on-delta” pulse-based transmission, targeting peripheral nerve neural recording applications. The proposed NSS employs event-based sampling which, by leveraging the sparse nature of electroneurogram (ENG) signals, achieves a data compression ratio of $> 125\times $ , while maintaining a low normalized rms error (NRMSE) of 4% after reconstruction. The proposed NSS consists of three sub-circuits. A clockless level-crossing (LC) analog-to-digital converter (ADC) with background offset calibration has been employed to reduce the data rate, while maintaining a high signal to quantization noise ratio (SQNR). A fully synthesized spiking neural network (SNN) extracts temporal features of compound action potential (CAP) signals and consumes only 13 $\mu \text{W}$. An event-driven, pulse-based body channel communication (Pulse-BCC) with serialized address-event representation (AER) encoding schemes minimizes transmission energy and form factor. The prototype is fabricated in 40-nm CMOS occupying a 0.32-mm2 active area and consumes in total 28.2 and 50 $\mu \text{W}$ power in feature extraction and full diagnosis mode, respectively. The presented NSS also extracts temporal features of CAP signals with 10- $\mu \text{s}$ precision. [ABSTRACT FROM AUTHOR]

This brief presents a 10.5-bit 10 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) with $1.5\times $ input range (IR). By pre-setting and resetting the most significant bit (MSB) of the digital-to-analog converter (DAC) to shift the input signal accordingly, the input range of the ADC is enhanced by a factor of 1.5. This effectively relaxes the noise requirement and thus improves the power efficiency of the ADC. The prototype implemented in 65-nm CMOS technology achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.37 dB and a spurious-free dynamic range (SFDR) of 82.2 dB. It consumes $18.65~\mu \text{W}$ at 10 MS/s with a 0.8V supply and only occupies an area of 0.0013 mm2. The resulting Walden figure of merit (FoM $_{W}$) is 2.2 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This article presents a second-order noise-shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) that employs a duty-cycled amplifier and digital-predicted mismatch error shaping (MES). The loop filter is composed of an active amplifier and two cascaded passive integrators to provide a theoretical 30-dB in-band noise attenuation. The amplifier achieves $18\times $ gain in a power-efficient way thanks to its inverter-based topology and duty-cycled operation. The capacitor mismatch in the digital-to-analog converter (DAC) array is mitigated by first-order MES. A two-level digital prediction scheme is adopted with MES to avoid input range loss. Fabricated in 65-nm CMOS technology, the prototype achieves 80-dB peak signal-to-noise-and-distortion-ratio (SNDR) and 98-dB peak spurious-free-dynamic-range (SFDR) in a 31.25-kHz bandwidth with $16\times $ oversampling ratio (OSR), leading to a Schreier figure-of-merit (FoM) of 176.3 dB and a Walden FoM of 14.3 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This brief presents the analysis, design, and measurements of a compact analog frontend for a catheter-integrated ultrasound imaging digitizer. This frontend requires several functions, including single-ended-to-differential conversion, AC coupling, amplification, anti-aliasing, and the capability to drive the subsequent ADC. To minimize chip area and to maximize power efficiency, a 2-stage frontend was designed, where the active stages are built using self-biased inverter-based amplifiers. The measured prototype in 40nm CMOS offers a gain of up to 15dB and a bandwidth up to 20MHz, while consuming up to $162\mu \text{W}$ from a 1.1V supply. The peak FoM of 158dB(J−1) and chip area of 0.0054mm2 are in line with state-of-the-art filters, while the proposed design includes the aforementioned extra functionalities as well. [ABSTRACT FROM AUTHOR]

This work presents a prototype system based on a multichannel receiving (RX) integrated circuit (IC) for contrast-enhanced ultrasound (CEUS) imaging. The RX IC is implemented in a 40-nm low-voltage CMOS technology and is designed to interface to a capacitive micromachined ultrasonic transducer array. To enable a direct connection of the RX electronics to the transducer, an analog multiplexer with on-chip protection circuitry is developed. Stress tests confirm the reliability of this arrangement when combined with a high-voltage pulser. The RX IC is equipped with a highly programmable bandpass filter to capture harmonic signals from ultrasound contrast agents (UCAs) while suppressing fundamental components. In order to examine the impact of analog front-end (AFE) bandpass filtering, in vitro acoustic experiments are performed with UCAs. A spatial resolution analysis suggests that the AFE bandpass filtering combined with a pulse inversion (PI) technique can improve the lateral resolution by 38% or 9% compared to the original full-bandwidth approach or a stand-alone PI approach, respectively, while the impact on axial resolution is negligible. A phantom study shows that compared to digital bandpass filtering, the AFE bandpass filtering enables better use of the dynamic range of the RX electronics, resulting in better generalized contrast-to-noise ratio from 0.44/0.53 to 0.57/0.68 without or with PI. [ABSTRACT FROM AUTHOR]

This paper presents a front-end integrated circuit for ultrasound (US) harmonic imaging, interfacing to a one-dimensional capacitive micromachined ultrasonic transducer (CMUT). It contains a complete ultrasound receiving chain, from analog front-end (AFE) to gigabit/s data link. A two-stage self-biased inverter-based transimpedance amplifier (TIA) is proposed in this work to improve tradeoffs between power, noise, and linearity at the first stage. To improve harmonic imaging performance, the design is further equipped with a 4 $^\text {th}$ -order highly programmable bandpass filter, which has a tunable bandwidth from 2 MHz to 15 MHz. An 8 b 80 MS/s SAR ADC digitizes the signal, which is further encoded and serialized into an LVDS data link, enabling a reduction in the number of output cables for future systems with multiple ADCs. The design is realized in a 40 nm CMOS technology. Electrical measurements show it consumes 2.9 mW for the AFE and 2.1 mW for the ADC and digital blocks. Its overall dynamic range varies from 61 dB to 69 dB, depending on the reception bandwidth. The imaging capability of this design is further demonstrated in a US transmission and reception imaging system. The acoustic measurements prove successful ultrasound harmonic acquisition, where the on-chip bandpass filter can improve the lateral resolution by more than 30%. [ABSTRACT FROM AUTHOR]

Long-term ambulatory monitoring of the fetal heart rate (fHR) can greatly increase insight into fetal well-being and reduce pregnancy risks. Unfortunately, the existing solutions using wet or dry electrodes are unsuitable for long-term fHR monitoring due to the use of a gel or direct skin contact. Capacitive electrodes can measure an electrocardiographic (ECG) signal through clothes and, therefore, are perfectly suitable for long-term monitoring of the fHR. However, capacitive fetal ECG (fECG) measurements are challenging due to the high sensitivity of capacitive sensors to motion artifacts (MAs) and the low amplitude of the fECG. This article aims at investigating the feasibility of fECG measurements using capacitive electrodes with dedicated postprocessing algorithms for signal-to-noise ratio (SNR) improvement and MA reduction. To this end, a novel simulator of the full measurement chain is realized that generates multichannel capacitive fECG data with artificial MAs and system noise. A dedicated blind source separation (BSS) algorithm is then employed for MA removal and fECG extraction. The extracted fECG is evaluated by SNR calculation and R-peak detection. Our results show that the BSS algorithm may extract the fECG signal from noisy capacitive data. In addition, lower system noise or higher number of channels may lead to better fECG extraction. A maximum increase of 0.5 dB in the SNR and decrease of 80.7 % in the R-peak detection error are observed with increased electrode number from 8 to 20. Our findings provide useful insights for the hardware design of a capacitive fECG measurement system. [ABSTRACT FROM AUTHOR]

In this work is presented a gravure-printed unipolar Organic Thin-Film Transistor (OTFT) technology able to achieve state-of-the-art yield performance. A multilayer cross-linked dielectric is printed to reduce gate-leakage defects, which have been found to be one of the main failure mechanisms in previous printed OTFTs. The defectivity analysis performed at transistor level reveals 99.8% defect-free devices in a sample of 540 OTFTs, manufactured on 6 successive foils. A novel row driver circuit for matrix-addressing applications has been designed and fabricated using the improved technology. The experimental characterization of the proposed 8-stage row drivers reveals a circuit yield as high as 100%, over 15 samples in 5 successive foils, corresponding to a total number of 2085 fully functional OTFTs. The availability of a printed organic technology compatible with mass production is expected to enable innovative Internet of Things (IoT) applications characterized by extremely low production cost. [ABSTRACT FROM AUTHOR]

Electrocardiography (ECG) measurements are esse- ntial components in clinical diagnosis and monitoring. Conventional ECG measurements produce discomfort to the patients due to the use of gel and direct skin contact. Capacitive electrodes can measure ECG signals through an isolation layer; they are especially suitable for long-term ambulatory monitoring. However, capacitive ECG measurements are severely affected by motion artifacts (MAs) due to variable coupling distance. Adaptive filtering has been widely used for MA reduction in ECG measurements. Unfortunately, a reference signal recorded by additional sensors is required for the existing adaptive-filtering methods, limiting their applicability in ambulatory settings. In this paper on capacitive ECG recordings, a novel adaptive-filtering method is proposed for MA removal, where the reference signal is extracted from the power-line interference (PLI). PLI is particularly evident in a capacitive ECG due to unbalanced coupling capacitance. Along with MAs, electrode movement causes variations in the PLI amplitude. By demodulating the PLI, a reference signal reflecting variations in the coupling capacitance can be extracted for adaptive MA removal. The proposed method was evaluated both by simulations and real data and compared with the acceleration-based adaptive-filtering method. Comparable or higher ECG signal-to-noise ratio was achieved by the proposed method with a computational cost of $79~\mu \text{s}$ /iteration, indicating effective MA removal. The proposed method may, therefore, lead to improved analysis of capacitive ECG signals in ambulatory settings. [ABSTRACT FROM AUTHOR]

A versatile, low-power, and energy-efficient capacitance-to-digital converter (CDC) for Internet-of-Things (IoT) is presented, based on an all-dynamic architecture with adaptable speed, resolution, and range. The proposed CDC includes a single-armed capacitive bridge and a differential switched-capacitor 10-b asynchronous successive approximation register (SAR) analog-to-digital-converter (ADC). The bridge output is directly sampled by the ADC through fully passive correlated-double-sampling (CDS) approach, which enables a fully dynamic operation. The design is fabricated in a 65-nm CMOS technology. Thanks to the dynamic nature of the CDC, sampling rates from 1 S/s up to 100 kS/s are supported and capacitances from 1.23 to 24.59 pF can be digitized, while the power scales inherently from 0.1 nW to $1~\mu \text{W}$. Optionally, the range can be further extended to >100 pF, and oversampling can be used to enhance resolution. This makes the design versatile to efficiently deal with a variety of sensors having different speed and resolution requirements and different capacitance values. The 0.1 nW lowest absolute power is $> 20\times $ smaller than the prior art, and the figure of merit (FoM) from 18 to 59 fJ/conv-step is also the lowest among prior designs. To provide application examples, this chip is further verified with a microelectromechanical (MEMS) pressure sensor and a MEMS accelerometer. It can measure environmental pressure consuming only 0.8 nW at a speed of 100 S/s, and measure acceleration using 1.4 nW at a speed of 200 S/s. [ABSTRACT FROM AUTHOR]

This paper presents a compact 10-b successive approximation register analog-to-digital converter (SAR ADC) in 65-nm CMOS with an integrated passive finite impulse response (FIR) filter for anti-aliasing. Conventional switched-capacitor digital-to-analog converters (DACs) are usually implemented with unit elements for the best matching performance, at the cost of increased chip area. Instead, this paper proposes a unit-length capacitor implementation, which minimizes the number of components and thus minimizes area, while also achieving good linearity (integral non-linearity of 0.39 LSB, differential non-linearity of 0.55 LSB, and SFDR of 75 dB) despite using a small LSB capacitor of 125 aF. The 10-b SAR ADC occupies only $36 \times 36\,\,\mu \text{m}$ , thanks to the small-size DAC, and by placing the ADC circuits directly under the capacitors. The ADC was tested at 10 and 30 MS/s and achieves an effective number of bits of 9.18/9.10 bit with an figure-of-merit of 4.1/4.4 fJ per conversion-step, respectively. Besides the ADC, a passive analog FIR filter is added to implement an anti-aliasing filter. The topology is based on a passive charge-sharing network and thus only consumes power for the clock phase generation and switch drivers. A 4 $\times $ time-interleaved 15-tap passive FIR filter is implemented, which can realize >42 dB out-of-band rejection and 4 $\times $ decimation while occupying only $53\times 90\,\,\mu \text{m}$. The filter and the ADC together consume 39.2 $\mu \text{W}$ for an output rate of 10 MS/s. [ABSTRACT FROM AUTHOR]

Successive approximation register (SAR) analog-to-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area. This paper presents a CR SAR ADC with an integrated low-power and area-efficient discrete-time reference driver. An on-chip capacitor is pre-charged to the reference voltage during the tracking phase and drives the DAC of the SAR ADC passively during the conversion phase. The charge sharing between the driving capacitor and the DAC will cause reference voltage drop and code-dependent non-binary DAC switching steps. This is compensated by switching an auxiliary DAC array together with the regular binary DAC array according to each specific code. The compensation relaxes the required decoupling capacitor and introduces little overhead in power or chip area. The above-mentioned driving scheme is applied to a 10-b 20-MS/s successive approximation register (SAR) ADC fabricated in 65-nm CMOS, where the first three DAC switching steps are compensated. Moreover, redundancy is utilized to reduce the impact of reference voltage drop further. With a near-Nyquist input tone, the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SAR ADC with the uncompensated reference driver are 54.4 and 58.9 dB, respectively. After enabling the compensation, the SNDR and SFDR are increased to 56.8 and 72.4 dB, achieving 2.4 and 13.5 dB improvement, respectively. The SAR ADC consumes a total power of 133.1 $\mu \text{W}$ while the discrete-time reference driver with and without compensation add 17.2 and 14.0 $\mu \text{W}$ , respectively. The SAR ADC with integrated reference driver occupies a chip area of 0.081 mm2 where 8.6% is occupied by the reference driver. [ABSTRACT FROM AUTHOR]

In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and template-based design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and $16.7~\mu \text{W}$ at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively. [ABSTRACT FROM AUTHOR]

The digital-to-analog converter (DAC) in SAR anolog-to-digital converters (ADCs) is often dominant for both power consumption and linearity. Dedicated switching schemes can save power, but mostly focus on conversion energy, whereas the DAC reset can consume significant energy as well. This paper presents an energy-free DAC reset scheme, “swap to reset,” for charge-redistribution SAR ADCs. It is widely applicable to existing low-power switching schemes. Additionally, to limit complexity while maintaining most of the energy savings, it can be utilized for the MSBs of the DAC only while the LSBs use conventional reset. To demonstrate the scheme, it is applied to the 2 MSBs of a 12-b SAR ADC using a split-monotonic DAC in 65-nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC. Besides the “swap to reset,” a rotation is also applied to the 2 MSBs, hence enhancing the linearity to 88-dB spurious free dynamic range. The SAR ADC operates at 0.8-V power supply and 40 kS/s, achieving an signal to noise and distortion ratio of 64.2 dB and a Figure of Merit of 7.1-fJ/conversion step. [ABSTRACT FROM AUTHOR]

A 6.4 MS/s 13 b ADC with a low-power background calibration for DAC mismatch and comparator offset errors is presented. Redundancy deals with DAC settling and facilitates calibration. A two-mode comparator and 0.3 fF capacitors reduce power and area. The background calibration can directly detect the sign of the dynamic comparator offset error and the DAC mismatch errors and correct both of them simultaneously in a stepwise feedback loop. The calibration achieves 20 dB spur reduction with little area and power overhead. The chip is implemented in 40 nm CMOS and consumes 46 \mu \textW from a 1 V supply, and achieves 64.1 dB SNDR and a FoM of 5.5 fJ/conversion-step at Nyquist. [ABSTRACT FROM AUTHOR]

This paper presents a noise-reconfigurable resistive feedback amplifier with current-reuse technique for fetal ECG monitoring. The proposed amplifier allows for both tuning of the noise level and changing the power consumption according to the signal properties, minimizing the total power consumption while satisfying all application requirements. The amplifier together with its amplitude detector and dynamical biasing circuit is implemented in a standard 0.18- \mu \textm CMOS process. Measurements demonstrate that the proposed current-reuse resistive feedback topology improves the power efficiency of the conventional resistive feedback amplifier, achieving at the same time a good noise efficiency factor (NEF =2.8 ) and an input impedance of 20 \text{M}\Omega . The amplitude detector and the dynamical biasing circuit, which tunes the current in the amplifier according to the signal amplitude, save up to 40% of the total power consumption. The amplifier achieves a measured noise level of 0.34 \mu \text{V}_{\mathrm{ rms}}$ in a 0.6–175-Hz band, consuming 6.3- \mu \text{W} power. [ABSTRACT FROM PUBLISHER]

This paper presents a 10 b 80 kS/s SAR ADC with low-power duty-cycled reference generation. It generates a stable reference voltage on chip for the SAR ADC and imparts very good immunity against power supply interference to the ADC. A 0.62 V-VDD 25 nW CMOS reference voltage generator (RVG) is presented, which has only ±1.5% variation over process corners. A duty-cycling technique is applied to enable 10% duty-cycling of the RVG, resulting in negligible power consumption of the RVG compared to that of the ADC. Furthermore, a bi-directional dynamic preamplifier is adopted in the SAR ADC, which consumes about half the power compared with a regular dynamic structure and maintains noise and gain performance. Compared with prior-art low-power ADCs, this work is the first to integrate the reference generation and include it in the power consumption while maintaining a competitive 2.4 fJ/conversion-step FoM. The chip is fabricated in 65 nm CMOS technology. [ABSTRACT FROM PUBLISHER]

Miniature \textmm^3-sized sensor nodes have a very tight power budget, in particular, when a long operational lifetime is required, which is the case, e.g., for implantable devices or unobtrusive IoT nodes. This paper presents a fully integrated signal acquisition IC for these emerging applications. It integrates an amplifier with 32 dB gain and 370 Hz bandwidth that includes positive feedback to enhance input impedance and dc offset compensation. The IC includes also a 10 bit 1 kS/s SAR ADC as well as a clock generator and voltage and current biasing circuits. The overall system achieves an input noise of 27\;\upmu \text V{\text{rms}}, consumes 3 nW from a 0.6 V supply, occupies 0.20\;\text mm^2 in 65 nm CMOS, and has a single-wire data interface. The amplifier achieves an noise-efficiency factor (NEF) of 2.1 and the ADC has a figure-of-merit (FoM) of 1.5 fJ/conversion-step. Measurements confirm reliable operation for supplies from 0.50 to 0.70 V and temperatures in the range of 0–85 °C. As an application example, an ECG recording is successfully performed with the system while a 0.69\; \textmm^2 photodiode array provides its power supply in indoor lighting conditions. [ABSTRACT FROM PUBLISHER]

This paper presents a low-voltage current-reuse chopper-stabilized frontend amplifier for fetal ECG monitoring. The proposed amplifier allows for individual tuning of the noise in each measurement channel, minimizing the total power consumption while satisfying all application requirements. The low-voltage current reuse topology exploits power optimization in both the current and the voltage domain, exploiting multiple supply voltages (0.3, 0.6 and 1.2 V). The power management circuitry providing the different supplies is optimized for high efficiency (peak charge-pump efficiency = 90\%).The low-voltage amplifier together with its power management circuitry is implemented in a standard 0.18~\mum CMOS process and characterized experimentally. The amplifier core achieves both good noise efficiency factor (NEF=1.74) and power efficiency factor (PEF=1.05). Experiments show that the amplifier core can provide a noise level of 0.34~\mu Vrms in a 0.7 to 182 Hz band, consuming 1.17~\mu W power. The amplifier together with its power management circuitry consumes 1.56 ~\mu W, achieving a PEF of 1.41. The amplifier is also validated with adult ECG and pre-recorded fetal ECG measurements. [ABSTRACT FROM PUBLISHER]

A sub-\muW ECG acquisition IC is presented for a single-chamber leadless pacemaker applications. It integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor. To save ASIC power, a current-multiplexed channel buffer is introduced to drive a 7 b-to-10 b self-synchronized SAR ADC which utilizes 4 fF/unit capacitors. The ASIC consumes only 680nA and achieves CMRR >90 dB, PSRR >80 dB, an input-referred noise of 4.9 \muVrms in a 130 Hz bandwidth, and has rail-to-rail DC offset rejection. Low-power heartbeat detections are evaluated with the help of the ASIC acquiring nearly 20,000 beats across 10 different records from the MIT-BIH arrhythmia database. In the presence of muscle noise, both the average Sensitivity (Se) and Positive Predictivity (PP) show more than 90% when the input SNR >6 dB. [ABSTRACT FROM PUBLISHER]