190 results on '"Jammy, R."'
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2. Grain boundary-driven leakage path formation in HfO2 dielectrics
3. Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor
4. Effects of parasitics and interface traps on ballistic nanowire FET in the ultimate quantum capacitance limit
5. Gate-first integration of tunable work function metal gates of different thicknesses into high- k/metal gates CMOS FinFETs for multi-Vth engineering
6. Interrelationship between electrical and physical properties of subcritical Si-Ge layers grown directly on silicon for short channel high-performance pMOSFETs
7. Analyzing noise in modern MOSFETs
8. Advances in processing and characterizing Bi-based superconductors
9. Superconducting joints for silver-clad BSCCO tapes
10. Recent issues in fabrication of Ag-clad BSCCO superconductors
11. X-Ray Reflectometry Determination of Structural Information from Atomic Layer Deposition Nanometer-Scale Hafnium Oxide Thin Films
12. A Comparison of Electrical and Physical Properties of MOCVD Hafnium Silicate Thin Films Deposited using Various Silicon Precursors
13. Recent advances in bismuth-based superconductors
14. Strain-enhanced scaling of HK+MG CMOSFETs
15. Improvement of metal gate/high-k dielectric CMOSFETs characteristics by atomic layer etching of high-k gate dielectric
16. A Comparative NBTI Study of HfO(2), HfSiO(x), and SiON p-MOSFETs Using UF-OTF I(DLIN) Technique
17. A Novel Fluorine Incorporated Band Engineered (BE) Tunnel (SiO2/ HfSiO/ SiO2) TANOS with Excellent Program/Erase & Endurance to 10^5 Cycles
18. CONNECTING ELECTRICAL AND STRUCTURAL DIELECTRIC CHARACTERISTICS.
19. SILICON FINFETS AS DETECTORS OF TERAHERTZ AND SUB-TERAHERTZ RADIATION.
20. High-k metal-gate PMOS FinFET threshold voltage tuning with aluminum implantation.
21. Conformal, low-damage shallow junction technology (Xj∼5nm) with optimized contacts for FinFETs as a Solution Beyond 14nm Node.
22. Hot Forming to Improve Memory Window and Uniformity of Low-Power HfOx-Based RRAMs.
23. Emerging CMOS and beyond CMOS technologies for an ultra-low power 3D world.
24. High endurance performance of 1T1R HfOx based RRAM at low (<20μA) operative current and elevated (150°C) temperature.
25. Effects of RRAM Stack Configuration on Forming Voltage and Current Overshoot.
26. Parasitic resistance reduction technology.
27. Sub-60nm Si tunnel field effect transistors with Ion >100 µA/µm.
28. High-performance Enhancement-Mode In0.53Ga0.47As surface channels n-MOSFET with thin In0.2Ga0.8As capping and laser anneal effect.
29. Grain boundary-driven leakage path formation in HfO2 dielectrics.
30. Advanced techniques for achieving ultra-shallow junctions in future CMOS devices.
31. Correlation between dielectric traps and BTI characteristics of high-k/ metal gate MOSFETs.
32. Understanding noise measurements in MOSFETs: the role of traps structural relaxation.
33. Impact of dipole-induced dielectric relaxation on high-frequency performance in La-incorporated HfSiON/metal gate nMOSFET.
34. Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node.
35. InGaAs MOSFET performance and reliability improvement by simultaneous reduction of oxide and interface charge in ALD (La)AlOx/ZrO2 gate stack.
36. Engineering the complete MANOS-type NVM stack for best in class retention performance.
37. A novel damage-free high-k etch technique using neutral beam-assisted atomic layer etching (NBALE) for sub-32nm technology node low power metal gate/high-k dielectric CMOSFETs.
38. Mobility reduction and reliability assessment of high-k/metal gate stacks in deep sub-nanometer EOT region.
39. The challenges and progress of USJ formation & process integration for 32nm technology and beyond.
40. Effect of substrate hot carrier stress on high-k gate stack.
41. Effect of substrate hot carrier stress on high-k gate stack.
42. Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric.
43. The impact of la-doping on the reliability of low Vth high-k/metal gate nMOSFETs under various gate stress conditions.
44. A comprehensive and comparative study of interface and bulk characteristics of nMOSETs with la-incorporated high-k dielectrics.
45. Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application.
46. NIST method for determining model-independent structural information by X-ray reflectometry.
47. Formation of Shallow Junctions Using Ge-Si Heterostructures for High Mobility Channel MOSFETs.
48. Reliability Assessment on Highly Manufacturable MOSFETs with Metal Gate and Hf based Gate Dielectrics.
49. Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate.
50. High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node.
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