129 results on '"Sangsig Kim"'
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2. Binarized neural network of diode array with high concordance to vector–matrix multiplication
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Yunwoo Shin, Kyoungah Cho, and Sangsig Kim
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Binarized neural network ,Multiply-accumulate ,Vector–matrix multiplication ,Gated p+-n-p-n+ diodes ,Positive-feedback loop mechanism ,Medicine ,Science - Abstract
Abstract In this study, a binarized neural network (BNN) of silicon diode arrays achieved vector–matrix multiplication (VMM) between the binarized weights and inputs in these arrays. The diodes that operate in a positive-feedback loop in their p+-n-p-n+ device structure possess steep switching and bistable characteristics with an extremely low subthreshold swing (below 1 mV) and a high current ratio (approximately 108). Moreover, the arrays show a self-rectifying functionality and an outstanding linearity by an R-squared value of 0.99986, which allows to compose a synaptic cell with a single diode. A 2 × 2 diode array can perform matrix multiply-accumulate operations for various binarized weight matrix cases with some input vectors, which is in high concordance with the VMM, owing to the high reliability and uniformity of the diodes. Moreover, the disturbance-free, nondestructive readout, and semi-permanent holding characteristics of the diode arrays support the feasibility of implementing the BNN.
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- 2024
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3. Stateful Logic Operation of Gated Silicon Diodes for In‐Memory Computing
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Jaemin Son, Juhee Jeon, Kyoungah Cho, and Sangsig Kim
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diode ,in‐memory computing ,positive feedback mechanism ,quasi‐nonvolatile memory ,stateful logic ,Electric apparatus and materials. Electric circuits. Electric networks ,TK452-454.4 ,Physics ,QC1-999 - Abstract
Abstract In‐memory computing significantly reduces workload and energy cost of data access in the traditional von Neumann computing architecture. Using various memristors, stateful logic is developed to realize in‐memory computing. However, memristors have encountered critical issues in terms of device variation and reliability, and therefore, fundamental device solutions are required to realize practical stateful logic. In this study, NAND, NOR, and half‐adder stateful logic operations of gated silicon diodes with a p+–n–p–n+ structure are demonstrated to achieve in‐memory computing. Gated diodes have bistable, steep switching, and quasi‐nonvolatile memory characteristics, enabling reliable stateful logic operation. The uniformity of their device characteristics overcomes the inherent stochastic characteristics of memristors that are widely researched for stateful logic. The sequential multiread logic operation simplifies the complex state logic scheme. In particular, a nondestructive half‐adder operation can be executed in five sequential steps using six parallel diodes. Thus, the stateful logic of gated diodes can be a potential building block for in‐memory computing.
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- 2024
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4. Effect of interface defects on electrical characteristics of a-ITGZO TFTs under bottom, top, and dual gatings
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Mingu Kang, Kyoungah Cho, Minhyeok Seol, Sangsub Kim, and Sangsig Kim
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Amorphous indium-tin-gallium-zinc-oxide ,Dual gate thin-film transistor ,Bulk accumulation ,Interface trap states ,TCAD simulation ,Science (General) ,Q1-390 ,Social sciences (General) ,H1-99 - Abstract
Here, we investigate the effects of interface defects on the electrical characteristics of amorphous indium-tin-gallium-zinc oxide (a-ITGZO) thin-film transistors (TFTs) utilizing bottom, top, and dual gatings. The field-effect mobility (27.3 cm2/V∙s) and subthreshold swing (222 mV/decade) under a dual gating is substantially better than those under top (12.6 cm2/V∙s, 301 mV/decade) and bottom (11.1 cm2/V∙s, 487 mV/decade) gatings. For an a-ITGZO TFT, oxygen deficiencies are more prevalent in the bottom-gate dielectric interface than in the top-gate dielectric interface, and they are less prevalent inside the channel layer than at the interfaces, indicating that the presence of oxygen deficiencies significantly affects the field-effect mobility and subthreshold swing. Moreover, the variation in the electrical characteristics due to the positive bias stress is discussed here.
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- 2024
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5. Bidirectional Synaptic Operations of Triple‐Gated Silicon Nanosheet Transistors with Reconfigurable Memory Characteristics
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Yunwoo Shin, Jaemin Son, Juhee Jeon, Seungho Ryu, Kyoungah Cho, and Sangsig Kim
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bidirectional synaptic functions ,reconfigurable memory characteristics ,silicon nanosheet ,spiking neural network ,triple‐gated transistors ,Electric apparatus and materials. Electric circuits. Electric networks ,TK452-454.4 ,Physics ,QC1-999 - Abstract
Abstract In this study, a triple‐gated transistor with a p+‐i‐n+ silicon nanosheet (NS) is proposed as a single synaptic device, and bidirectional synaptic functions are realized using reconfigurable memory characteristics. The triple‐gated NS transistor features steep switching and bistable characteristics with a subthreshold swing below 5 mV dec−1 and an ON/OFF current ratio of ≈5 × 106 for both the n‐ and p‐channel modes. This transistor exhibits electrically symmetric reconfigurable memory characteristics with an ON current ratio of 1.02 for the n‐ and p‐channel modes. Moreover, the bidirectional synaptic weight updates of binarized spike‐timing‐dependent plasticity learning are successfully performed in a single transistor. This study demonstrates the potential of a triple‐gated NS transistor for achieving compact synaptic arrays in large‐scale silicon‐based neuromorphic computing systems.
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- 2024
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6. Reconfigurable Logic‐In‐Memory Cell Comprising Triple‐Gated Feedback Field‐Effect Transistors
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Jongseong Han, Jaemin Son, Juhee Jeon, Yunwoo Shin, Kyoungah Cho, and Sangsig Kim
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logic‐in‐memory ,positive feedback loops ,reconfigurable logic gates ,reconfigurable logic‐in‐memory cells ,triple‐gated feedback field‐effect transistors ,Electric apparatus and materials. Electric circuits. Electric networks ,TK452-454.4 ,Physics ,QC1-999 - Abstract
Abstract A reconfigurable logic‐in‐memory (R‐LIM) cell performs logic‐in‐memory functions as well as reconfigurable logic gates. The R‐LIM cell is constructed with triple‐gated (TG) feedback field‐effect transistors (FBFETs) that are reconfigured in n‐channel or p‐channel modes via electrostatic doping. Each TG FBFET has one control gate electrode and two program‐gate electrodes that determine the channel mode. Their reconfigurability enables the symmetrical operation of the n‐channel and p‐channel modes through an on‐current ratio of 1:04. Furthermore, the R‐LIM cell performs eight Boolean logic operations, storing the logic outputs for ≈100 s under zero‐bias conditions. The R‐LIM cell is useful for developing in‐memory computing systems with high energy efficiency and functional logic.
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- 2023
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7. Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors
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Jaemin Son, Juhee Jeon, Kyoungah Cho, and Sangsig Kim
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field-effect transistor ,positive feedback loop ,oscillator ,physical unclonable function ,random number generator ,Chemistry ,QD1-999 - Abstract
In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator exhibited uniform probability distributions of 51.6% for logic 0 and 48.4% for logic 1. The generation of analog voltages provides binary random variables that are stored for over 5000 s. This demonstrates the potential of the ring oscillator in advanced physical functions and true random number generator technologies.
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- 2024
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8. Temperature-Dependent Feedback Operations of Triple-Gate Field-Effect Transistors
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Taeho Park, Kyoungah Cho, and Sangsig Kim
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feedback field-effect transistor (FBFET) ,latch-up phenomenon ,positive feedback loop ,temperature-dependent ,TCAD simulation ,Chemistry ,QD1-999 - Abstract
In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of −200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from −1.01 V (1.34 V) to −11.01 V (10.45 V) in the n-channel (p-channel) mode. In contrast, with decreasing temperature from 25 °C to −200 °C, the thermally generated charge carriers decrease, causing a shift in the latch-up voltage in the opposite direction to that of the increasing temperature case. Despite the shift in the latch-up voltage, the TG FBFETs exhibit ideal switching characteristics, with subthreshold swings of 6.6 mV/dec and 7.2 mV/dec for the n-channel and p-channel modes, respectively. Moreover, the memory window widens with increasing temperature. Specifically, at temperatures above 85 °C, the memory windows are wider than 3.05 V and 1.42 V for the n-channel and p-channel modes, respectively.
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- 2024
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9. Effects of Interface States on Electrical Characteristics of Feedback Field-Effect Transistors
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Juhee Jeon, Kyoungah Cho, and Sangsig Kim
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Positive feedback mechanism ,memory ,interface state ,trap ,FBFET ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
In this study, we examine the effect of interface trap states on the electrical characteristics of single-gated feedback field-effect transistors (FBFETs) using a commercially available computer-aided design simulation package. Interface trap states exist between the channels and the oxide layers, and these trap states act as acceptor-like trap states in regions of higher energy than the intrinsic Fermi energy ( $E_{\mathrm {i}}$ ) and as donor-like trap states in regions of lower energy than $E_{\mathrm {i}}$ in the energy band. The density distribution peaks at $E_{\mathrm {i}}$ + 0.28 eV for the acceptor-like trap states and at $E_{\mathrm {i}}$ – 0.28 eV for the donor-like trap states. The occupation mechanism of these trap states is analyzed by the density of the interface states and trapped charges, the energy band diagram, and the current-voltage curves. In n-channel (p-channel) FBFETs, the latch-up voltage varies by approximately 0.01 V as the acceptor-like (donor-like) trap states increase, whereas the effect of the donor-like (acceptor-like) trap states is negligible. Moreover, the FBFETs exhibit an operating speed of 4 ns and retention time of 900 s during a memory operation, despite the existence of the interface states.
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- 2023
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10. Read Operation Mechanism of Feedback Field-Effect Transistors with Quasi-Nonvolatile Memory States
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Juhee Jeon, Kyoungah Cho, and Sangsig Kim
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quasi-nonvolatile memory ,TCAD ,FBFET ,read operation ,rising time ,Chemistry ,QD1-999 - Abstract
In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, generating the memory state “State 1 (State 0)”. Read pulses of 40 ns read these states with a retention time of 3 s, and the potential barrier formation and carrier accumulation were influenced by these read pulses. The potential barriers were analyzed, using junction voltage and current density to explore the memory states. Moreover, FBFETs exhibited nondestructive readout characteristics during the read operation, which depended on the read voltage and pulse width.
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- 2024
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11. Logic‐In‐Memory Characteristics of Reconfigurable Feedback Field‐Effect Transistors with Double‐Gated Structure
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Yunwoo Shin, Jaemin Son, Juhee Jeon, Kyoungah Cho, and Sangsig Kim
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double‐gated structures ,inverters ,logic‐in‐memory ,positive feedback loop mechanisms ,reconfigurable ,Electric apparatus and materials. Electric circuits. Electric networks ,TK452-454.4 ,Physics ,QC1-999 - Abstract
Abstract The reconfigurable feedback field‐effect transistors (R‐FBFETs) with a double‐gated structure are designed and the logic and memory operations of a logic‐in‐memory (LIM) inverter comprising two R‐FBFETs are investigated. The R‐FBFETs exhibit an extremely low subthreshold swing of ≈1 mV dec−1, a high on/off current ratio of ≈107, and a long retention time of 10 s, owing to a positive feedback loop mechanism. The on‐current ratio of the p‐ to n‐channel modes is 1.03, which indicates a high degree of reconfigurability. The LIM inverter retains the output logic “1” and “0” states for over 50 s under zero‐bias conditions. The symmetric reconfigurable switching and memory operations of the R‐FBFETs enable the LIM inverter to perform logic and memory operations for a long retention time without a power supply.
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- 2023
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12. Universal logic-in-memory cell enabling all basic Boolean algebra logic
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Eunwoo Baek, Kyoungah Cho, and Sangsig Kim
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Medicine ,Science - Abstract
Abstract Among the promising approaches for implementing high-performance computing, reconfigurable logic gates and logic-in-memory (LIM) approaches have been drawing increased research attention. These allow for improved functional scaling of a chip, owing to the improved functionality per unit area. Although numerous studies have been conducted independently for either reconfigurable logic or LIM units, attempts to construct a hybrid structure based on reconfigurable logic and LIM units remain relatively rare. In this study, we merge reconfigurable logic gates and LIM units to achieve a universal logic-in-memory (ULIM) cell for enabling all basic Boolean logic operations and data storage in a single cell. A ULIM cell consisting of silicon memory devices with reconfigurable n- and p-program modes can reconfigure logic operations within the complete set of Boolean logic operations. Moreover, the ULIM cell exhibits memory behaviors for storing output logic values without supply voltages for a certain period, resulting in zero static power consumption. Hence, this study provides a way to realize high-performance electronics by utilizing the silicon devices with a hybrid function of reconfigurable logic and LIM.
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- 2022
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13. Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors
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Juhee Jeon, Sola Woo, Kyoungah Cho, and Sangsig Kim
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Medicine ,Science - Abstract
Abstract In this study, we propose an inverter consisting of reconfigurable double-gated (DG) feedback field-effect transistors (FBFETs) and examine its logic and memory operations through a mixed-mode technology computer-aided design simulation. The DG FBFETs can be reconfigured to n- or p-channel modes, and these modes exhibit an on/off current ratio of ~ 1012 and a subthreshold swing (SS) of ~ 0.4 mV/dec. Our study suggests the solution to the output voltage loss, a common problem in FBFET-based inverters; the proposed inverter exhibits the same output logic voltage as the supply voltage in gigahertz frequencies by applying a reset operation between the logic operations. The inverter retains the output logic ‘1’ and ‘0’ states for ~ 21 s without the supply voltage. The proposed inverter demonstrates the promising potential for logic-in-memory application.
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- 2022
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14. New ternary inverter with memory function using silicon feedback field-effect transistors
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Jaemin Son, Kyoungah Cho, and Sangsig Kim
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Medicine ,Science - Abstract
Abstract In this study, we present a fully complementary metal–oxide–semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a positive feedback loop by carrier accumulation in their channels, which allows to achieve excellent memory characteristics with extremely low subthreshold swings. This hybrid operation of the switching and memory functions enables FBFETs to implement memory operation in a conventional CMOS logic scheme. The inverter comprising p- and n-channel FBFETs in series can be in ternary logic states and retain these states during the hold operation owing to the switching and memory functions of FBFETs. It exhibits a high voltage gain of approximately 73 V/V, logic holding time of 150 s, and reliable endurance of approximately 105. This ternary inverter with memory function demonstrates possibilities for a new computing paradigm in multivalued logic applications.
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- 2022
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15. Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double‐Gated Feedback Field‐Effect Transistors
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Jaemin Son, Yunwoo Shin, Kyoungah Cho, and Sangsig Kim
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field‐effect transistor ,logic‐in‐memory ,multivalued logic ,positive feedback loop ,universal gate ,Electric apparatus and materials. Electric circuits. Electric networks ,TK452-454.4 ,Physics ,QC1-999 - Abstract
Abstract In this study, the logic‐in‐memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double‐gated feedback field‐effect transistors. The component transistors reconfigure their operation modes into n‐ or p‐channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on‐current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero‐bias condition. This study demonstrates that the ternary logic gates are promising candidates for next‐generation low‐power computing systems.
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- 2023
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16. Neural oscillation of single silicon nanowire neuron device with no external bias voltage
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Sola Woo and Sangsig Kim
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Medicine ,Science - Abstract
Abstract In this study, we perform simulations to demonstrate neural oscillations in a single silicon nanowire neuron device comprising a gated p–n–p–n diode structure with no external bias lines. The neuron device emulates a biological neuron using interlinked positive and negative feedback loops, enabling neural oscillations with a high firing frequency of ~ 8 MHz and a low energy consumption of ~ 4.5 × 10−15 J. The neuron device provides a high integration density and low energy consumption for neuromorphic hardware. The periodic and aperiodic patterns of the neural oscillations depend on the amplitudes of the analog and digital input signals. Furthermore, the device characteristics, energy band diagram, and leaky integrate-and-fire operation of the neuron device are discussed.
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- 2022
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17. NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors
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Yejin Yang, Juhee Jeon, Jaemin Son, Kyoungah Cho, and Sangsig Kim
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Medicine ,Science - Abstract
Abstract The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowire feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.
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- 2022
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18. Temperature-Dependent Electrical Characteristics of p-Channel Mode Feedback Field-Effect Transistors
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Taeho Park, Jaehwan Lee, Jaemin Son, Juhee Jeon, Yeonwoo Shin, Kyoungah Cho, and Sangsig Kim
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Field-effect transistor ,positive feedback loop ,temperature-dependent ,simulation ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
In this study, the temperature-dependent electrical characteristics of p-channel mode feedback field-effect transistors (FBFETs) were examined at temperatures ranging from 250 to 425 K. Their steep subthreshold swings of less than 1 mV/dec were maintained even at temperatures up to 400 K. As the temperature increased to 400 K, the latch-up voltage shifted from −0.951 to −0.613 V, which was caused by a reduction in the potential barriers in the channels of the FBFETs. High $I_{\mathrm {on}}/I_{\mathrm {off}}$ ratios above 108 were maintained in the temperature range of 250 to 400 K. However, at temperatures over 400 K, the FBFETs were turned on regardless of the gate voltages owing to the generation of a thermally induced positive feedback loop.
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- 2022
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19. Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges
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Yejin Yang, Young-Soo Park, Jaemin Son, Kyoungah Cho, and Sangsig Kim
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Medicine ,Science - Abstract
Abstract In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.
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- 2021
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20. One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors
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Sangik Choi, Jaemin Son, Kyoungah Cho, and Sangsig Kim
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Medicine ,Science - Abstract
Abstract In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.
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- 2021
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21. Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors
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Juhee Jeon, Kyoungah Cho, and Sangsig Kim
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one-transistor dynamic random-access memory ,memory array ,silicon nanowire ,feedback field-effect transistor ,positive feedback mechanism ,Mechanical engineering and machinery ,TJ1-1570 - Abstract
Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+–n–p–n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10−15 J/bit for the write ‘1’ operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.
- Published
- 2023
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22. Electrical Stability of p-Channel Feedback Field-Effect Transistors Under Bias Stresses
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Jaemin Son, Kyoungah Cho, and Sangsig Kim
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Field-effect transistor ,positive feedback loop ,reliability ,bias stress ,recovery ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
In this study, we examined electrical stability of the p-channel feedback field-effect transistors (FBFETs) under negative bias stress (NBS) and positive bias stress (PBS). The intact FBFETs have a subthreshold swing (SS) of 0.12 mV/dec, an on-current of $\sim 10^{-4}$ A, and a threshold voltage ( $V_{\mathrm {TH}}$ ) of −0.76 V. There is a negligible change in the on-current and SS when the FBFETs are stressed by a gate-bias voltage corresponding to an electric field of 5.4 MV/cm across the gate oxide. On the other hand, as the duration of the stress increases to 1000 s, the $V_{\mathrm {TH}}$ shifts to −0.89 V and −0.67 V for NBS and PBS, respectively. The $V_{\mathrm {TH}}$ was recovered to over 83% at a recovery bias voltage of ±5 V. The electrical stabilities of FBFETs under NBS and PBS are discussed in this study.
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- 2021
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23. Prediction of Device Characteristics of Feedback Field-Effect Transistors Using TCAD-Augmented Machine Learning
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Sola Woo, Juhee Jeon, and Sangsig Kim
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feedback field-effect transistors ,machine learning ,random forest regression ,technology computer-aided design (TCAD) ,TCAD-augmented machine learning ,Mechanical engineering and machinery ,TJ1-1570 - Abstract
In this study, the device characteristics of silicon nanowire feedback field-effect transistors were predicted using technology computer-aided design (TCAD)-augmented machine learning (TCAD-ML). The full current–voltage (I-V) curves in forward and reverse voltage sweeps were predicted well, with high R-squared values of 0.9938 and 0.9953, respectively, by using random forest regression. Moreover, the TCAD-ML model provided high prediction accuracy not only for the full I-V curves but also for the important device features, such as the latch-up and latch-down voltages, saturation drain current, and memory window. Therefore, this study demonstrated that the TCAD-ML model can substantially reduce the computational time for device development compared with conventional simulation methods.
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- 2023
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24. Effect of net voltage of thermoelectric generator on performance of hybrid energy device
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Yoonbeom Park, Kyoungah Cho, Seunggen Yang, Taeho Park, Sungeun Park, Hee-eun Song, Soo Min Kim, and Sangsig Kim
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Photovoltaic cell ,Thermoelectric generator ,Hybrid energy device ,Thermoelectric voltage ,Voltage drop ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
In this study, we investigate the performance of a hybrid energy device (HED) composed of a photovoltaic cell (PVC) and a thermoelectric generator (TEG) through an analysis of the voltage difference (net voltage) between voltage drop and thermoelectric voltage. The efficiency of the HED is compared with that of an isolated PVC at irradiances in the range of 200∼1000 W/m2. At an irradiance of 200 W/m2, the maximum power of the HED is 6.7% higher than that of the isolated PVC because the thermoelectric voltage is greater than the voltage drop in the TEG. Our study reveals that the net voltage between the voltage drop and the thermoelectric voltage determines whether the output power of the HED is higher than that of the isolated PVC. In addition, the relationship between the net voltage and the increase in maximum power of the HED reveals that the net voltage becomes a predictor of the performance of HED.
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- 2020
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25. Performance Enhancement of Hybrid Energy Devices Using Cooling Patches
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Jaehwan Lee, Kyoungah Cho, Yoonbeom Park, Sungeun Park, Hee-eun Song, and Sangsig Kim
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Renewable energy sources ,TJ807-830 - Abstract
In this study, we demonstrated the enhancement of the output power of a hybrid energy device (HED) using a cooling patch that does not consume any external electric power. The HED consisted of a photovoltaic cell (PVC) and a thermoelectric generator (TEG); the cooling patch was attached to the TEG. When the PVC was exposed to solar irradiance, the cooling patch lowered the temperature of the PVC and increased the thermal gradient across the TEG, thereby increasing the output power. For an HED with a cooling patch at an irradiance of 1000 W/m2, the output power increased to 24.2 mW, as compared to the output power of 19.9 mW for an HED without any cooling patch.
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- 2022
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26. Integrate-and-Fire Neuron Circuit Without External Bias Voltages
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Young-Soo Park, Sola Woo, Doohyeok Lim, Kyoungah Cho, and Sangsig Kim
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p-n-p-n diode ,technology computer-aided design simulation ,latch-up phenomenon ,integrate-and-fire neuron ,spiking neural networks ,absence of external bias lines ,Neurosciences. Biological psychiatry. Neuropsychiatry ,RC321-571 - Abstract
In this study, we propose an integrate-and-fire (I&F) neuron circuit using a p-n-p-n diode that utilizes a latch-up phenomenon and investigate the I&F operation without external bias voltages using mixed-mode technology computer-aided design (TCAD) simulations. The neuron circuit composed of one p-n-p-n diode, three MOSFETs, and a capacitor operates with no external bias lines, and its I&F operation has an energy consumption of 0.59 fJ with an energy efficiency of 96.3% per spike. The presented neuron circuit is superior in terms of structural simplicity, number of external bias lines, and energy efficiency in comparison with that constructed with only MOSFETs. Moreover, the neuron circuit exhibits the features of controlling the firing frequency through the amplitude and time width of the synaptic pulse despite of the reduced number of the components and no external bias lines.
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- 2021
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27. Mechanism of carrier controllability with metal capping layer on amorphous oxide SiZnSnO semiconductor
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Byeong Hyeon Lee, Ahrum Sohn, Sangsig Kim, and Sang Yeol Lee
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Medicine ,Science - Abstract
Abstract The change of electrical performance of amorphous SiZnSnO thin film transistors (a-SZTO TFTs) has been investigated depending on various metal capping layers on the channel layer by causing different contact property. It was confirmed that the change of electrical characteristics was sensitively dependent on the change of the capping layer materials on the same channel layer between the source/drain electrodes. This sensitive change in the electrical characteristics is mainly due to different work function of metal capping layer on the channel layer. The work function of each capping layer material has been analyzed and derived by using Kelvin probe force microscopy and compared with the energy bandgap of the SZTO layer. When the work function of the capping layer is larger than that of the channel layer, electrons are depleted from the channel layer to the capping layer. On the contrary, in the case of using a material having a work function smaller than that of the channel layer, the electrical characteristics were improved because electrons were injected into the channel layer. Based on depletion and injection mechanism caused by different contact barrier between metal capping layer and channel layer, NOT, NAND, and NOR logic circuits have been implemented simply by changing metal capping layer on the channel layer.
- Published
- 2019
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28. Design and Simulation of Logic-In-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor
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Eunwoo Baek, Jaemin Son, Kyoungah Cho, and Sangsig Kim
- Subjects
feedback field-effect transistor ,logic-in-memory ,mixed-mode simulation ,positive feedback loop ,silicon nanowire ,Mechanical engineering and machinery ,TJ1-1570 - Abstract
In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). The hybrid logic and memory operations of the LIM inverter were investigated by mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.8 (V/V) when transitioning from logic ‘1’ to ‘0’ and 7.9 (V/V) when transitioning from logic ‘0’ to ‘1’, while holding calculated logic at zero input voltage. The energy band diagrams of the n-FBFET structure demonstrated that the holding operation of the inverter was implemented by controlling the positive feedback loop. Moreover, the output logic can remain constant without any supply voltage, resulting in zero static power consumption.
- Published
- 2022
- Full Text
- View/download PDF
29. Switchable‐Memory Operation of Silicon Nanowire Transistor
- Author
-
Yoonjoong Kim, Jinsun Cho, Doohyeok Lim, Sola Woo, Kyoungah Cho, and Sangsig Kim
- Subjects
one transistor ,positive feedback loop ,silicon nanowires ,switchable‐memory ,Electric apparatus and materials. Electric circuits. Electric networks ,TK452-454.4 ,Physics ,QC1-999 - Abstract
Abstract The switchable‐memory operation of a feedback silicon nanowire transistor with a dual‐gate structure is demonstrated. The single transistor exhibits volatile memory characteristics with a retention time longer than 3600 s, as well as a switching capability with a subthreshold swing lower than 7 mV dec−1. A gate‐controlled memory window forms around a gate voltage of 0 V owing to the positive feedback loop in the channel region, allowing a program/erase endurance of more than 1000 cycles. The memory transistor, with switching capability, opens up the possibility of overcoming not only the scaling limit faced by conventional volatile memory but also the inherent drawback of the separation of the building blocks for memory and logic.
- Published
- 2018
- Full Text
- View/download PDF
30. Enhanced Thermoelectric Characteristics of Ag2Se Nanoparticle Thin Films by Embedding Silicon Nanowires
- Author
-
Seunggen Yang, Kyoungah Cho, and Sangsig Kim
- Subjects
thermoelectric ,silver selenide nanoparticles ,silicon nanowires ,thin film ,Technology - Abstract
A solution-processable Ag2Se nanoparticle thin film (NPTF) is a prospective thermoelectric material for plastic-based thermoelectric generators, but its low electrical conductivity hinders the fabrication of high performance plastic-based thermoelectric generators. In this study, we design Ag2Se NPTFs embedded with silicon nanowires (SiNWs) to improve their thermoelectric characteristics. The Seebeck coefficients are −233 and −240 µV/K, respectively, for a Ag2Se NPTF alone and a Ag2Se NPTF embedded with SiNWs. For the Ag2Se NPTF embedded with SiNWs, the electrical conductivity is improved from 0.15 to 18.5 S/m with the embedment of SiNWs. The thermal conductivities are determined by a lateral thermal conductivity measurement for nanomaterials and the thermal conductivities are 0.62 and 0.84 W/(m·K) for a Ag2Se NPTF alone and a Ag2Se NPTF embedded with SiNWs, respectively. Due to the significant increase in the electrical conductivity and the insignificant increase in its thermal conductivity, the output power of the Ag2Se NPTF embedded with SiNWs is 120 times greater than that of the Ag2Se NPTF alone. Our results demonstrate that the Ag2Se NPTF embedded with SiNWs is a prospective thermoelectric material for high performance plastic-based thermoelectric generators.
- Published
- 2020
- Full Text
- View/download PDF
31. Characterization of a Photodiode Coupled with a Si Nanowire-FET on a Plastic Substrate
- Author
-
Kiyeol Kwak, Kyoungah Cho, and Sangsig Kim
- Subjects
pn heterojunction photodiode ,FET ,optical sensor ,plastic substrate ,nanowire ,Chemical technology ,TP1-1185 - Abstract
In this study, a laterally coupled device composed of a photodiode and a Si nanowires-field-effect transistor (NWs-FET) is constructed on a plastic substrate and the coupled device is characterized. The photodiode is made of p-type Si NWs and an n-type ZnO film. The Si NWs-FET is connected electrically to the photodiode in order to enhance the latter’s photocurrent efficiency by adjusting the gate voltage of the FET. When the FET is switched on by biasing a gate voltage of −9 V, the photocurrent efficiency of the photodiode is three times higher than that when the FET is switched off by biasing a gate voltage of 0 V.
- Published
- 2010
- Full Text
- View/download PDF
32. Photogating effects of HgTe nanoparticles on a single ZnO nanowire
- Author
-
Hojun, Seong, Kyoungah, Cho, Junggwon, Yun, Kiyeol, Kwak, Hyung, Jun Jin, and Sangsig, Kim
- Published
- 2010
- Full Text
- View/download PDF
33. Memory characteristics of silicon nanowire transistors generated by weak impact ionization
- Author
-
Sangsig Kim, Yoonjoong Kim, Minsuk Kim, and Doohyeok Lim
- Subjects
Materials science ,lcsh:Medicine ,02 engineering and technology ,Hardware_PERFORMANCEANDRELIABILITY ,01 natural sciences ,Article ,law.invention ,law ,0103 physical sciences ,Hardware_INTEGRATEDCIRCUITS ,Static random-access memory ,Silicon nanowires ,lcsh:Science ,010302 applied physics ,Multidisciplinary ,Hardware_MEMORYSTRUCTURES ,business.industry ,Transistor ,lcsh:R ,021001 nanoscience & nanotechnology ,Impact ionization ,Subthreshold swing ,Optoelectronics ,lcsh:Q ,0210 nano-technology ,business ,Hardware_LOGICDESIGN - Abstract
In this study, we demonstrate the static random access memory (SRAM) characteristics generated by weak impact ionization in bendable field-effect transistors (FETs) with n+-p-n+ silicon nanowire (SiNW) channels. Our bendable SiNW FETs show not only superior switching characteristics such as an on/off current ratio of ~105 and steep subthreshold swing (~5 mV/dec) but also reliable SRAM characteristics. The SRAM characteristics originate from the positive feedback loops in the SiNW FETs generated by weak impact ionization. This paper describes in detail the operating mechanism of our device and demonstrates the potential of bendable SiNW FETs for future SRAM applications.
- Published
- 2017
34. Mechanism of carrier controllability with metal capping layer on amorphous oxide SiZnSnO semiconductor
- Author
-
Ahrum Sohn, Sangsig Kim, Sang Yeol Lee, and Byeong Hyeon Lee
- Subjects
0301 basic medicine ,Kelvin probe force microscope ,Multidisciplinary ,Materials science ,business.industry ,Science ,NOR logic ,Article ,Amorphous solid ,03 medical and health sciences ,030104 developmental biology ,0302 clinical medicine ,Semiconductor ,Thin-film transistor ,Electrode ,Medicine ,Optoelectronics ,Work function ,sense organs ,business ,Layer (electronics) ,030217 neurology & neurosurgery - Abstract
The change of electrical performance of amorphous SiZnSnO thin film transistors (a-SZTO TFTs) has been investigated depending on various metal capping layers on the channel layer by causing different contact property. It was confirmed that the change of electrical characteristics was sensitively dependent on the change of the capping layer materials on the same channel layer between the source/drain electrodes. This sensitive change in the electrical characteristics is mainly due to different work function of metal capping layer on the channel layer. The work function of each capping layer material has been analyzed and derived by using Kelvin probe force microscopy and compared with the energy bandgap of the SZTO layer. When the work function of the capping layer is larger than that of the channel layer, electrons are depleted from the channel layer to the capping layer. On the contrary, in the case of using a material having a work function smaller than that of the channel layer, the electrical characteristics were improved because electrons were injected into the channel layer. Based on depletion and injection mechanism caused by different contact barrier between metal capping layer and channel layer, NOT, NAND, and NOR logic circuits have been implemented simply by changing metal capping layer on the channel layer.
- Published
- 2019
35. Flexible semi-around gate silicon nanowire tunnel transistors with a sub-kT/q switch.
- Author
-
Myeongwon Lee, Youngin Jeon, Minsuk Kim, and Sangsig Kim
- Subjects
FIELD-effect transistors ,SILICON nanowires ,ELECTRIC potential ,QUANTUM tunneling ,DIELECTRIC materials ,TEMPERATURE - Abstract
Tunnel field-effect transistors (TFETs) with a subthreshold swing (SS)<60 mV/dec are expected to be active devices in low-power flexible systems, potentially lowering operational voltage by virtue of steep switching behavior via band-to-band tunneling. In silicon (Si) channel materials, however, it still remains a challenge to obtain SS smaller than 60 mV/dec. In this study, we experimentally demonstrate the sub-60 mV/dec operation of a flexible semi-around gate TFET on a plastic substrate using Si nanowires (SiNWs) as the channel material. With the combined advantages of selectively thinned SiNW channels (width ~15 nm and height ~40 nm) and high-κ (Al
2 O3 ~7 nm) gate dielectric, in conjunction with an abrupt degenerate source junction, the device with a channel length of ~500 nm exhibits a minimal SS of ~42 mV/dec at room temperature. Moreover, mechanical bendability of the device indicates that it has stable and good fatigue properties, providing an important step towards the realization of steep-slope switches for low-power and energy-efficient flexible electronics. [ABSTRACT FROM AUTHOR]- Published
- 2015
- Full Text
- View/download PDF
36. Bendable solid-state supercapacitors with Au nanoparticle-embeddedgraphene hydrogel films
- Author
-
Sangsig Kim, Kyungwhan Yang, Kyoungah Cho, and Dae Sung Yoon
- Subjects
Supercapacitor ,Multidisciplinary ,Materials science ,Graphene ,Capacitive sensing ,Nanoparticle ,02 engineering and technology ,Internal resistance ,010402 general chemistry ,021001 nanoscience & nanotechnology ,01 natural sciences ,Capacitance ,Article ,0104 chemical sciences ,law.invention ,law ,Electrode ,Composite material ,0210 nano-technology ,Current density - Abstract
In this study, we fabricate bendable solid-state supercapacitors with Au nanoparticle (NP)-embedded graphene hydrogel (GH) electrodes and investigate the influence of the Au NP embedment on the internal resistance and capacitive performance. Embedding the Au NPs into the GH electrodes results in a decrease of the internal resistance from 35 to 21 Ω, and a threefold reduction of the IR drop at a current density of 5 A/g when compared with GH electrodes without Au NPs. The Au NP-embedded GH supercapacitors (NP-GH SCs) exhibit excellent capacitive performances, with large specific capacitance (135 F/g) and high energy density (15.2 W·h/kg). Moreover, the NP-GH SCs exhibit comparable areal capacitance (168 mF/cm2) and operate under tensile/compressive bending.
- Published
- 2017
37. Gate-field dependent photosensitivity of soluble 1,2,4,5-tetra(5'-hexyl-[2,2']terthiophenyl-5-vinyl)-benzene based organic thin film transistors
- Author
-
Mi Yeon Cho, Kihyun Kim, Su Jin Kim, Seong Gi Jo, Kyung Hwan Kim, Ki Hwa Jung, Dong Hoon Choi, Sangsig Kim, and Jinsoo Joo
- Subjects
Benzene -- Electric properties ,Benzene -- Optical properties ,Voltage -- Measurement ,Thin film devices -- Design and construction ,Physics - Abstract
The various photoresponsive current-voltage characteristics of the organic thin film transistors (OTFTs) are analyzed. An increase in the incident light power is shown to lead to a significant reduction in the photosensitivity of the devices.
- Published
- 2010
38. Nondestructive Readout Memory Characteristics of Silicon Nanowire Biristors.
- Author
-
Doohyeok Lim, Minsuk Kim, Yoonjoong Kim, Jinsun Cho, and Sangsig Kim
- Subjects
SILICON nanowires ,IONIZATION energy ,ELECTRIC resistors ,CAPACITORS ,RANDOM access memory - Abstract
In this paper, we demonstrate nondestructive readout memory characteristics of a bistable resistor (biristor) with an n
+ -p-n+ Si nanowire (SiNW) channel on a bendable substrate. The SiNW channel is fabricated using a top--down route, which is compatible with the current complementary metal-oxide-semiconductor technology. The SiNW biristor shows the outstanding memory characteristics such as a retention time of 10 s and a current sensing margin of ~23-μA at room temperature. These memory characteristics originate from a positive feedback process resulting from impact ionization near the p-n junction. Moreover, the positive feedback mechanism is comprehensively investigated using device simulation. [ABSTRACT FROM AUTHOR]- Published
- 2018
- Full Text
- View/download PDF
39. Nano-Floating Gate Memory Devices Composed of ZnO Thin-Film Transistors on Flexible Plastics
- Author
-
Kyoungah Cho, Sungsu Kim, Sangsig Kim, and Byoungjun Park
- Subjects
Electron mobility ,Fabrication ,Materials science ,Thin-film transistors ,Nanochemistry ,Nanotechnology ,Flexible devices ,Substrate (electronics) ,Hardware_PERFORMANCEANDRELIABILITY ,law.invention ,Materials Science(all) ,law ,Nano ,Hardware_INTEGRATEDCIRCUITS ,lcsh:TA401-492 ,Low temperature ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Nano Express ,business.industry ,Transistor ,General Medicine ,Condensed Matter Physics ,Non-volatile memory ,Thin-film transistor ,Optoelectronics ,Nanoparticles ,lcsh:Materials of engineering and construction. Mechanics of materials ,business - Abstract
Nano-floating gate memory devices were fabricated on a flexible plastic substrate by a low-temperature fabrication process. The memory characteristics of ZnO-based thin-film transistors with Al nanoparticles embedded in the gate oxides were investigated in this study. Their electron mobility was found to be 0.18 cm2/V·s and their on/off ratio was in the range of 104–105. The threshold voltages of the programmed and erased states were negligibly changed up to 103 cycles. The flexibility, memory properties, and low-temperature fabrication of the nano-floating gate memory devices described herein suggest that they have potential applications for future flexible integrated electronics.
- Published
- 2011
40. Electrical characteristics of a bendable a-Si:H thin film transistor with overlapped gate and source/drain regions.
- Author
-
Hyungon Oh, Kyoungah Cho, and Sangsig Kim
- Subjects
SILICON compounds ,THIN film transistors ,TRANSISTORS ,TENSILE strength ,MECHANICAL behavior of materials - Abstract
In this study, we investigate the influence of an overlap between the gate and source/drain regions of a-Si:H thin film transistors (TFTs) on their electrical characteristics under tensile or compressive strain through experiment and mechanical simulation. The strain distribution in the a-Si:H TFT for a bending radius of 2mm reveals that the strain at both ends of the TFT is ten times larger than that at the source-drain current path. The overlap lowers the stress sustained by the TFT in the region comprised between the channel and the gate insulator; therefore, TFTs with the overlap operate even at a tensile strain of 2.54%. In particular, the overlap is remarkably effective on relaxing the stress sustained in the interface between the gate insulator and the gate electrode, consequently improving the electrical stability of the bent TFT. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
41. Influence of thermal stress on heat-generating performance of indium tin oxide nanoparticle thin films.
- Author
-
Kyungwhan Yang, Kyoungah Cho, Sangsig Kim, and Kiju Im
- Subjects
INDIUM tin oxide ,THERMAL stresses ,QUARTZ ,MICROCRACKS ,THIN films - Abstract
In this study, the authors investigate the influence of thermal stress on the heat-generating performance of indium tin oxide (ITO) nanoparticle (NP) thin films on quartz substrates. ITO NP thin films experience repeated thermal stresses during their electrical heating cycles. As the number of the heating cycles increases to 50, the highest temperature of the ITO NP thin film decreases from 317 to 221 °C. Our analysis of the temperature profiles, morphological images, and electrical resistance reveals that the degradation in the heat-generating performance is closely correlated with microcracks in the oxide thin film caused by thermal stresses. [ABSTRACT FROM AUTHOR]
- Published
- 2016
- Full Text
- View/download PDF
42. Electrical and mechanical characteristics of fully transparent IZO thin-film transistors on stress-relieving bendable substrates.
- Author
-
Sukhyung Park, Kyoungah Cho, Hyungon Oh, and Sangsig Kim
- Subjects
TRANSISTORS ,ZINC oxide films ,YOUNG'S modulus ,INDIUM ,ELASTOMERS - Abstract
In this study, we report the electrical and mechanical characteristics of fully transparent indium zinc oxide (IZO) thin-film transistors (TFTs) fabricated on stress-relieving bendable substrates. An IZO TFT on a stress-relieving substrate can operate normally at a bending radius of 6mm, while an IZO TFT on a normal plastic substrate fails to operate normally at a bending radius of 15mm. A plastic island with high Young's modulus embedded on a soft elastomer layer with low Young's modulus plays the role of a stress-relieving substrate for the operation of the bent IZO TFT. The stress and strain distributions over the IZO TFT will be analyzed in detail in this paper. [ABSTRACT FROM AUTHOR]
- Published
- 2016
- Full Text
- View/download PDF
43. Steep Subthreshold Swing n- and p-Channel Operationof Bendable Feedback Field-Effect Transistors with pâiân㖩⫞ by Dual-Top-Gate Voltage Modulation.
- Author
-
Youngin Jeon, Minsuk Kim, Doohyeok Lim, and Sangsig Kim
- Published
- 2015
- Full Text
- View/download PDF
44. Electrical characteristics of flexible ZnO thin-film transistors annealed by microwave irradiation.
- Author
-
Sukhyung Park, Kyoungah Cho, Kyungwhan Yang, and Sangsig Kim
- Subjects
THIN film transistors ,ZINC oxide thin films ,IRRADIATION ,PHOTOLUMINESCENCE ,ELECTRIC conductivity - Abstract
This study examines the effect of microwave annealing upon the electrical characteristics of a representative ZnO thin-film transistor (TFT) deposited on a flexible plastic substrate. After microwave irradiation, the mobility of the TFT is increased from 0.2 to 1.5 cm²/(V s) and its on/off ratio increases from 36.5 to 6.9 x 10
6 . The photoluminescence study reveals that the concentration of oxygen vacancies increases remarkably when the ZnO thin films are exposed to microwave radiation. In this paper, in addition to the results mentioned above, the correlation between the photoluminescence and electrical characteristics is discussed and the electrical characteristics of the ZnO TFT under strain are analyzed. [ABSTRACT FROM AUTHOR]- Published
- 2014
- Full Text
- View/download PDF
45. A Feature-Based Modeling Approach for Building Hybrid Access Control Systems.
- Author
-
Sangsig Kim, Dae-Kyoo Kim, Lunjin Lu, Sooyong Park, and Suntae Kim
- Published
- 2011
- Full Text
- View/download PDF
46. Simulation of a lateral trench IGBT with p+ diverter having superior electrical characteristics.
- Author
-
Ey Goo Kang, Seung Hyun Moon, Sangsig Kim, and Man Young Sung
- Published
- 2001
- Full Text
- View/download PDF
47. Voltage-induced electroluminescence characteristics of hybrid light-emitting diodes with CdSe/Cd/ZnS core-shell nanoparticles embedded in a conducting polymer on plastic substrates.
- Author
-
Kiyeol Kwak, Kyoungah Cho, and Sangsig Kim
- Subjects
LIGHT emitting diodes ,ELECTROLUMINESCENCE measurement ,NANOPARTICLES ,ELECTRIC potential measurement ,ANTHOLOGY films ,ELECTROCHEMILUMINESCENCE - Abstract
We investigate the electroluminescence (EL) characteristics of a hybrid light-emitting diode (HyLED) with an emissive layer comprised of CdSe/Cd/ZnS core-shell nanoparticles (NPs) embedded in poly(9,9-di-n-octylfluorenyl-2,7-diyl) (PFO) on a plastic substrate. The EL characteristics change dramatically with increasing of the biased voltage. At low voltages, recombination of electrons and holes occurs only in the PFO film because of poor charge transfer in the PFO-CdSe/Cd/ZnS NPs composite film, while the color of the light-emitting from the HyLED changes from blue to red as the biased voltage increases from 7.5 to 17.5V. We examine and discuss the mechanism of this color tunability. [ABSTRACT FROM AUTHOR]
- Published
- 2014
- Full Text
- View/download PDF
48. Stable Bending Performance of Flexible Organic Light-Emitting Diodes Using IZO Anodes.
- Author
-
Kiyeol Kwak, Kyoungah Cho, and Sangsig Kim
- Subjects
LIGHT emitting diodes ,ANODES ,PHOTOLUMINESCENCE ,SEMICONDUCTOR diodes ,OPTICS - Abstract
We report luminescent characteristics and mechanical stability of a flexible organic light-emitting diode (FOLED) using an amorphous ZnO-doped In
2 O3 (a-IZO) anode with a low sheet resistance of 18.9 Ω/◻ and a high optical transparency of 86%. The FOLED consisting of a-IZO/poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS)/poly[(9,9-di-n-octylfluorenyl-2,7-diyl)-alt-(benzo[2,1,3]thiadiazol-4, 8-diyl)] (F8BT)/LiF/Al exhibits the efficient luminescent characteristics, which are nearly identical with the photoluminescence spectrum of the organic emitting material in our FOLED. This observation clearly indicates that the luminescent characteristics of the FOLED are solely ascribed to molecular exciton formation within the F8BT layer, since exciplex and charge transfer exciton formation are strictly suppressed by both tunneling/thermionic injection of holes at the PEDOT:PSS/F8BT interface and enhanced hole transport. Furthermore, the use of the considerably flexible a-IZO anode and PEDOT:PSS acting as a strain-relief buffering material enables good retention of the efficient luminescent characteristics of the FOLED even after continuous bending of up to 1000 times. [ABSTRACT FROM AUTHOR]- Published
- 2013
- Full Text
- View/download PDF
49. Switching memory cells constructed on plastic substrates with silver selenide nanoparticles.
- Author
-
Jin Jun, Kyoungah Cho, Junggwon Yun, and Sangsig Kim
- Subjects
FLASH memory ,PROGRAMMABLE logic devices ,SUBSTRATES (Materials science) ,COMPUTER storage devices ,FERROELECTRIC RAM ,NANOPARTICLES ,SWITCHING circuits ,SELENIDES - Abstract
Programmable metallization cell (PMC) memory is a kind of next generation non-volatile memory that has attracted increasing attention in recent years as a possible replacement for flash memory. In spite of the considerable amount of research focused on the fabrication of non-volatile memories on plastic substrates with lightweight, thin, and bendable characteristics, there have been few studies on the fabrication of PCM memory on flexible substrates. In this study, we synthesized AgSe nanoparticles (NPs) by a positive-microemulsion method and constructed PMC memories on plastic substrates with programmable layers formed by the spin-coating of the AgSe NPs. To the best of the knowledge, this is the first attempt to construct PMC memory on plastic substrates by the spin-coating of AgSe NPs. The AgSe NPs synthesized in this study had a uniform size of 2 nm and interestingly showed α-phase (high temperature phase) stability at room temperature. Switching behaviors were observed through the voltage scanning on the fabricated memories with applicable switching voltages. However, the resistance ratios of the off-state to the on-state were quite small. The possible reasons for the α-phase stability of the AgSe NPs at room temperature and the detailed memory characteristics will be described in this article. [ABSTRACT FROM AUTHOR]
- Published
- 2011
- Full Text
- View/download PDF
50. Electrical Characteristics of Hybrid Nanoparticle--Nanowire Devices.
- Author
-
Dong-Young Jeong, Kihyun Keem, Byoungjun Park, Kyoungah Cho, and Sangsig Kim
- Published
- 2009
- Full Text
- View/download PDF
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