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10kV+ rated 4H- Silicon Carbide (SiC) Insulated Gate Bipolar Transistors (IGBTs) have the potential to become the devices of choice in future Medium Voltage (MV) and High Voltage (HV) power converters. However, one significant performance concern of SiC IGBTs is the extremely fast collector voltage rise (dV/dt) observed during inductive turn-off. Studies on the physical mechanisms of high dV/dt in 4H-SiC IGBTs revealed the importance of collector-side design in controlling the phenomenon. In this paper we propose a novel collector-side design approach, which consists of four n-type layers with optimized doping densities and allows the control of dV/dt independently from the device performance. Further, we demonstrate a reduction of dV/dt by 87% without degrading the high switching frequency capability of the device, or the on-state performance, through the addition of two n-type epitaxial layers in the collector side, between the buffer and the drift regions.

Power semiconductor devices are key to delivering high-efficiency energy conversion in power electronics systems, which is critical in efforts to reduce energy loss, cut carbon dioxide emissions and create more sustainable technology. Although the use of wide or ultrawide-bandgap materials will be required to develop improved power devices, multidimensional architectures can also improve performance, regardless of the underlying material technology. In particular, multidimensional device architectures—such as superjunction, multi-channel and multi-gate technologies—can enable advances in the speed, efficiency and form factor of power electronics systems. Here we review the development of multidimensional device architectures for efficient power electronics. We explore the rationale for using multidimensional architectures and the different architectures available. We also consider the performance limits, scaling and material figure of merits of the architectures, and identify key technological challenges that need to be addressed to realize the full potential of the approach. Accepted version

This work presents for the first time a comparative numerical study on the performance of planar 3.3 kV SiC MOSFETs during clamped and unclamped inductive switching for various cell layouts and pitches. It is demonstrated that despite its larger on-state losses, the atomic lattice layout (ALL) incurs smaller switching losses than the stripe and the circular designs for all examined cell pitches. Conversely, while the ALL does turn off earlier than the other layouts during UIS, the decrease in the peak lattice temperature that it brings is predicted to be marginal if just a single unit cell is considered.

In this manuscript, the short circuit (SC) capability of 1.2 kV vertical double diffused SiC MOSFET with different layout topologies is investigated. 3D finite element electro-thermal simulations have been carried out in order to assess the performance of five different cell topologies. It has been found that while the maximum drain current density observed during a SC event agrees well with the specific on-state resistance behaviour, the maximum temperature evolution in the unit cell follows the opposite trend. This behaviour can be explained by the relatively poor spreading of the carriers in the JFET region (of the ALL) at small cell pitches (~ 8um), which can lead to the formation of a filament with a high current density and heat generation.

Schottky contacts have been used to fabricate normally-off lateral reverse-blocking MESFETs on p-type (boron-doped) O-terminated monocrystalline diamond. The devices utilized an ohmic source contact but both gate and drain contacts were Schottky in nature. Boron-doped p-channel diamond MESFETs reported to date display the less attractive normally-on characteristics. Here, the normally-off transistor delivered a current level of ~1.5 μAmm⁻¹ at a negative $V_{GS}$ of 0.8 V and a transconductance (gₘ) of 16 μSmm⁻¹, measured at room temperature (RT); at a temperature of 425 K, these values rose to ~70 μAmm⁻¹ for $I_{DS}$ and a gₘ value of 260 μSmm⁻¹. In both cases, a negligible gate leakage current was measured with no breakdown apparent at the maximum field investigated here (3.7 x 10⁵ V/m⁻¹). The Schottky gate demonstrates a well-behaved control of the channel even at higher temperatures. The high-temperature operation, normally-off behavior, and diamond's inherent radiation hardness make this transistor promising for harsh environment applications.

In this letter, a miniature flow sensing system has been designed, simulated, manufactured, and tested. The system is comprised of a thermal flow sensing die, a package body, a lid, and leveling epoxy. The lid design is crucial to the system performance, and a reference design was shown to create vortices within the flow channel, resulting in nonlinear and nonrepeatable sensor response. Two novel lid designs were investigated that showed increased sensitivity and repeatability, while minimizing the effect of vortices disrupting the sensor response. These structures were named “vortex guides.” The first design provided a double increase in the signal sensitivity, while the second design isolated the vortices away from the sensors functional area, providing predictable flow response over a wider flow range. This enables high-sensitivity, large-range, low-cost miniature flow sensing for mass-market production.

As superjunction devices are scaled down to smaller dimensions, the gate ringing becomes more prominent in dynamic switching. The exact origin of superjunction MOSFET 's gate ringing has not been so far identified as the conventional three-terminal measurement method cannot capture the dynamic behavior of the device, in particular the redistribution of charge between the different internal capacitive components in the superjunction structure. In this article, it is found that the gate ringing is highly related to the input capacitance. Specifically, by employing a TCAD model with a split gate method, the gate-to-source ( CGS ) and gate-to-drain ( CGD ) current are investigated during the dynamic transitions. The gate ringing is highly dependent on sum of the input capacitances ( CGS + CGD ) for the turn- on . In the case of the turn- off , however, the gate ringing is affected by the ratio of the input capacitances ( CGD / CGS ) and a lower CGS is desirable for a low gate oscillation.

For large scale testability of p-GaN HEMTs it is essential to investigate threshold voltage ( $\text{V}_{\mathrm{ th}}$ ) instability from the perspective of the measurement induced instability. In this paper the impact of accumulated gate bias stress during standard transfer characteristic measurements ( $\text{I}_{\mathrm{ D}}$ - $\text{V}_{\mathrm{ G}}$ ) in a p-GaN AlGaN/GaN-on-Si normally off HEMT is quantitatively analysed and modeled. This illustrates the associated threshold voltage ( $\text{V}_{\mathrm{ th}}$ ) instabilities and leads to a better understanding of the $\text{V}_{\mathrm{ th}}$ measurement challenges of a p-GaN HEMT. Upon an application of a constant gate bias close to nominal $\text{V}_{\mathrm{ th}}$ the drain current $\text{I}_{\mathrm{ D}}$ shows an initial marginal rise, followed by a short stable period ( $\text{I}_{\mathrm{ Dstable}}$ - $\text{T}_{\mathrm{ zone}}$ ) and a steep decay period. The effective bias history built on the gate stack varies when pulse on-time (Ton) or step time (Tstep), corresponding to pulsed or DC step $\text{I}_{\mathrm{ D}}$ - $\text{V}_{\mathrm{ G}}$ measurements, are varied. We find that this can lead to a $\text{V}_{\mathrm{ th}}$ variation of up to 20%. It is also observed that the choice of Ton and Tstep determines whether $\text{I}_{\mathrm{ D}}$ is measured in $\text{I}_{\mathrm{ Dstable}}$ - $\text{T}_{\mathrm{ zone}}$ or the rise or decay periods. Measurement induced $\text{V}_{\mathrm{ th}}$ instability is attributed to trapping of 2DEG electrons at the AlGaN barrier and we demonstrate that an ohmic gate contact, in comparison to the Schottky gate contact, may compensate for the trapped 2DEG electrons by hole injection across the AlGaN barrier. Experimental results of $\text{V}_{\mathrm{ th}}$ stability under the same stress conditions for a Schottky and ohmic gate contact are supported by a detailed TCAD analysis.

The impact of different p-well designs upon the transient performance, in particular, the turn-off losses and short-circuit capability, of a >10 kV SiC n-IGBT is assessed. We find that in addition to improved transient performance, a substantial reduction in the depth of p-well implants can be achieved, if an extensively optimized retrograde approach is utilized. A conventional p-well consisting of a uniformly doped deep implant (doping concentration of ~3×1017 cm-3 and depth of >1.5 µm) exhibits considerable turn-off switching losses without offering any short circuit capability. However, an optimized retrograde p-well consisting of a variable doping profile and depth as shallow as 0.7-0.8 µm results in much reduced turn-off losses with excellent short-circuit capability. Shallow implants are desirable to lower the development cost and processing challenges. The retrograde p-well is therefore highly promising for the development of >10 kV class of SiC IGBTs.

The dV / dt in superjunction metal–oxide–semiconductor field-effect transistors (MOSFETs) during the turn-off transient has been shown to be higher than during the turn-on, which can be attributed to a shorter Miller plateau. In this article, we will show that these asymmetrical turn-on and turn-off characteristics are indirectly detected by the hysteresis of the dynamic gate-to-drain capacitance, ${C}_{\text {GD}}$ . Moreover, this article reveals the mechanisms behind the asymmetrical switching and the origin of the hysteresis, which have been shown to be caused by the difference in the ${C}_{\text {GD}}$ displacement current paths for the turn-off and the turn-on.

Multi-epitaxially grown superjunctions feature a fluctuation of the doping concentration (ripple) in the pillars and the ripple is highly dependent on the supplied thermal energy during the fabrication. This study thoroughly investigates the relationship between the ripple in the pillars and the static/dynamic characteristics of the device. The ripple dependent trade-offs in terms of the specific resistance and turn-off switching loss will be able to provide a guide for developing fine pitch superjunction devices.

As the dimensions of the power metal-semiconductor field-effect transistor (MOSFET) are scaling down, and the output capacitance is considerably reduced, the fast dV / dt becomes an issue and can trigger severe oscillations during hard switching. To understand the origin of the dV / dt and the induced gate oscillations, the intricate link between the device operation and the circuit conditions is required. In this article, the dynamic gate-to-drain capacitance, ${C}_{\text {GD}}$ , is extracted by employing a five-terminal method. Through the use of simulations, the relationship between ${C}_{\text {GD}}$ and the induced gate oscillations is explored. In addition to this, the 2-D depletion behavior in a superjunction system, which affects the dynamic ${C}_{\text {GD}}$ , is investigated.

Metal-oxide gas sensors have great potential for emerging applications, including breath analysis due to their small form factor, low cost, and low power, which enables integration in consumer electronics, such as smartphone accessories, wearables, and, in the future, smartwatches and phones. Acetone concentration in breath is an important biomarker for well-being and biomedical applications, such as weight loss and ketoacidosis monitoring. In this article, we present a monolithically integrated array of gas sensors combined with a flow sensor in order to provide better quantification of acetone. In particular, this work demonstrates improvement in the acetone selectivity thanks to the combination of three different metal oxides and the ability to compensate with the flow variation.

In recent years, there has been a growing desire to monitor and control harmful substances arising from industrial processes that impact upon our health and quality of life. This has led to a large market demand for gas sensors, which are commonly based on sensors that rely upon a chemical reaction with the target analyte. In contrast, thermal conductivity detectors are physical sensors that detect gases through a change in their thermal conductivity. Thermal conductivity gas sensors offer several advantages over their chemical (reactive) counterparts that include higher reproducibility, better stability, lower cost, lower power consumption, simpler construction, faster response time, longer lifetime, wide dynamic range, and smaller footprint. It is for these reasons, despite a poor selectivity, that they are gaining renewed interest after recent developments in MEMS-based silicon sensors allowing CMOS integration and smart application within the emerging Internet of Things (IoT). This timely review focuses on the state-of-the-art in thermal conductivity sensors; it contains a general introduction, theory of operation, interface electronics, use in commercial applications, and recent research developments. In addition, both steady-state and transient methods of operation are discussed with their relative advantages and disadvantages presented. Finally, some of recent innovations in thermal conductivity gas sensors are explored.

The state-of-the-art superjunction (SJ) MOSFETs are based on the p-n pillar structures, arranged in a 2-D stripe geometry. This arrangement uses the superposition of the electric field components at the p-n junctions to create an enhanced depletion volume for higher breakdown capability. In this article, we will discuss structures, which additionally use the component of the electric field in the third dimension, to further enhance the depletion space. This allows higher doping concentrations in the pillars, which result in a better tradeoff between the breakdown voltage and the ON-state resistance, when compared with the 2-D structures. Specifically, we present a core–shell cylindrical SJ structure, and using the radial Poisson equation, we explain the electric field distribution within the SJ. We further discuss which geometry (core or shell) gives the best performance tradeoff. This is followed by the development of an analytical model, for the ON-state resistance in a 3-D SJ. Finally, we derive a specific figure of merit for the 3-D SJs and compare it with that of the equivalent 2-D structures.

Funder: National Physical Laboratory; doi: http://dx.doi.org/10.13039/501100007851, Funder: Royal Society Dorothy Hodgkin Research Fellowship, The gas sensor market is growing fast, driven by many socioeconomic and industrial factors. Mid-infrared (MIR) gas sensors offer excellent performance for an increasing number of sensing applications in healthcare, smart homes, and the automotive sector. Having access to low-cost, miniaturized, energy efficient light sources is of critical importance for the monolithic integration of MIR sensors. Here, we present an on-chip broadband thermal MIR source fabricated by combining a complementary metal oxide semiconductor (CMOS) micro-hotplate with a dielectric-encapsulated carbon nanotube (CNT) blackbody layer. The micro-hotplate was used during fabrication as a micro-reactor to facilitate high temperature (>700 ∘C) growth of the CNT layer and also for post-growth thermal annealing. We demonstrate, for the first time, stable extended operation in air of devices with a dielectric-encapsulated CNT layer at heater temperatures above 600 ∘C. The demonstrated devices exhibit almost unitary emissivity across the entire MIR spectrum, offering an ideal solution for low-cost, highly-integrated MIR spectroscopy for the Internet of Things.

We present a miniaturised thermal acoustic gas sensor, fabricated using a CMOS microhotplate and MEMS microphone. The sensing mechanism is based on the detection of changes in the thermal acoustic conversion efficiency which is dependent on the physical properties of the gas. An active sensing element, consisting of a MEMS microphone, is used to detect the target gas while a reference element is used for acoustic noise compensation. Compared to current photoacoustic gas sensors, our sensor requires neither the use of gas-encapsulated microphones, nor that of optical filters. In addition, it has all the benefits of CMOS technology, including production scalability, low cost and miniaturization. Here we demonstrate its application for CO[Formula: see text] gas detection. The sensor could be used for gas leak detection, for example, in an industrial plant., We acknowledge funding from EPSRC grants EP/S031847/1, EP/R022534/1, Alan Turing Institute Award TU/B/ 000096 under EPSRC Grant EP/N510129/1, and Royal Society Equipment Grant RG170136.

In this letter, we investigate by means of experimental results and TCAD simulations the threshold voltage instability due to OFF-state drain stress in p-GaN gate AlGaN/GaN-on-Si HEMTs. When the drain of the p-GaN HEMT is biased in the OFF-state the threshold voltage ( ${V}_{\text {th}}$ ) shows a linear increase up to ~40%. This increase saturates at drain bias voltages above 50 V. The positive ${V}_{\text {th}}$ shift is attributed to the ionization of acceptor traps in the AlGaN region below the p-GaN gate with the source of these trapping sites suggested to be the p-GaN gate out-diffused Mg dopant atoms. The ionization of the Mg acceptors due to high electric field during OFF-state bias and the removal of the generated holes from the AlGaN region through the gate contact creates the charge conditions for a positive ${V}_{\text {th}}$ shift. The sharp decrease in the gate drain capacitance ( ${C}_{\text {gd}}$ ) for ${V}_{D} V, the simulated gate edge electric field reaching its peak for a drain voltage bias ${V}_{D} \sim {50}$ V and the positive threshold voltage shift observed for negative gate stress further validate the proposed model.

A p-well consisting of a retrograde doping profile is investigated for performance improvement of >10kV SiC IGBTs. The retrograde p-well, which can be realized using low-energy shallow implants, effectively addresses the punch-through, a common issue in high-voltage vertical architectures consisting of a conventional p-well with typical doping density of 1e17cm-3 and depth 1μm. The innovative approach offers an extended control over the threshold voltage. Without any punch-through, a threshold voltage in the range 6V-7V is achieved with gate-oxide thickness of 100nm. Gate oxide thickness is typically restricted to 50nm if a conventional p-well with doping density of 1e17cm-3 is utilized. We therefore propose a highly promising solution, the retrograde p-well, for the development of >10kV SiC IGBTs.

An analytical model for superjunction (SJ) MOSFETs having an oxide pillar between the n-pillar and the p-pillar is developed. Owing to the low permittivity of the oxide, a high electric field is sustained across the oxide. This reduces the parasitic depletion width within the n-pillar, thus improving the current conducting path. The advantage of this structure is particularly visible as the cell pitch is scaled down and the pillows become narrower. The use of an oxide pillar leads to 30% reduction in the specific ON-state resistance when compared to a conventional SJ for a 2- $\mu \text{m}$ cell pitch. The analytical model shows a good agreement with the simulation results.

This paper investigates the advantages and disadvantages of bonding pad over active area (BPOA) layout over a conventional layout for lateral AlGaN/GaN HEMTs designed for use in power applications. Extensive analysis of the performance of a BPOA device, both experimentally and supported by 3-D TCAD model simulations, reveals that while it can offer a higher current capability per unit area, it can lead to other disadvantages compared to a conventional design when considering reliability aspects.

The geometric structure of a low-power thermal micro-hot film sensor has been investigated and optimized, using both computational and experimental methods. The response and accuracy of eight CMOS designs with different heater and membrane sizes were studied and found to vary considerably with geometry. It is found that reducing the heater length causes an improved electro-thermal efficiency and that a large reduction in accuracy was seen when reducing the membrane size. Our simulations suggest that this effect is due to higher temperature gradients causing localized stronger natural convective flows above the measuring resistor. However, the reduced accuracy disappears as flow rate increases due to a higher proportion of forced convection compared with natural convection. We believe that this paper will help in the design of a new generation of high accuracy MEMS thermal flow sensors for low-cost, low-power application.

A new type of high-voltage termination, namely the “deep p-ring trench” termination design for high-voltage, high-power devices, is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required but also removes the need for an additional mask as is the case of the traditional p+ ring-type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide, which results in reduced hot carrier injection and improved device reliability.

In ISPSD 2020 it has been shown that the effective mobility of a lateral 4H-SiC MOSFET could be increased by an order of magnitude through using an ultra-narrow-body design. Thus, this work presents further experimental results on a wide set of fin widths, ranging from conventional (860nm) to ultra-narrow (35nm). Furthermore, a 3D TCAD model, employing quantum corrections, is matched to experiment and applied to study these designs. It is thereby shown that the FinFET effect can have a strong impact in SiC devices and may allow for up to an 18x increase of the mobility relative to a reference width of 280nm. Finally, an optimization window of ~30-50nm is predicted for the fin width, below which the FinFET effect becomes detrimental.

This paper presents for the first time a combined experimental/numerical study of the electro-thermal surge current behaviour of 6.5kV SiC MOSFETs for various cell layouts. By means of a matched TCAD model it is demonstrated that the circular (and hence also the hexagonal) topology shows an inferior surge capability to the stripe. Conversely, the ALL allows for the dissipated losses and the peak lattice temperature attained during a 10ms pulse test to be reduced in both body and channel diode mode. In this context, it is shown that the sensitivity of the device’s response to the active area can be decreased at smaller pitches.

In this paper we present a snap-back free 3.3kV, 75A Reverse Conducting IGBT (RC-IGBT) with improved Reverse Bias (RBSOA) and Short-Circuit (SCSOA) Safe Operating Areas. The device employs floating N+ regions under the gate BUSBARs to locally reduce hole concentration and uses segmented N+ Anode regions to minimise the reverse recovery losses. The device architecture was conceived on extensive TCAD modelling and a DOE approach. The best design variants have been manufactured, tested and used for extensive analysis of key device trade-offs.

In this paper we present a novel MEMS technology for CO 2 detection, based on differential thermal conductivity. Holes have been positioned across the thin-film dielectric membrane to induce an asymmetric temperature profile in conjunction with a centrally heated tungsten resistor, leading to distinct magnitudes of gas interaction across the sensor, all of which is substantiated by a numerical model. Differential readings are taken from four surrounding resistors and shown to correlate to CO 2 concentration. The best resistor combination is investigated and is shown to provide a sensitivity of 0.05 mV/%CO 2 . Using separate heating and sensing elements greatly lowers the noise and a detection resolution of < 100 ppm is calculated. This proof-of-concept article introduces a device that could lead to low-cost, low-power, high-sensitivity, scalable gas detection.

A termination design which efficiently reduces leakage current and improves robustness of very high voltage insulated gate bipolar transistors (IGBTs) (>3.3 kV) without adversely affecting other device characteristics is presented here. Proposed design uses a selectively formed Buried N+ layer in the N-buffer under the termination region. Optimised placement of the N+ buried regions reduces carrier modulation in the termination area thus lowering the leakage current and reducing maximum temperature during the reverse bias safe operating area tests. This improves dynamic ruggedness of the IGBT without deteriorating other device characteristics.

Early diagnosis in exhaled breath is a key technology for next-generation personal healthcare monitoring. Current chemiresistive sensors, primarily based on metal oxide (MOx) thin films, have limited applicability in such portable systems due to their high power consumption, long recovery time, poor device-to-device consistency, and baseline drifts. To address these challenges for ammonia ($${{\rm{NH}}}_{3}$$ NH 3 ) detection in exhaled breath, a critical biomarker for a variety of kidney and liver problems, we present a formulation of a graphene–MOx functional ink-based sensing platform. We integrate our sensing layer directly onto miniaturized CMOS microhotplates (μHP) via inkjet printing, potentially enabling scalability and device-to-device performance repeatability. Using stage-by-stage temporal analysis, and a temperature-pulsed modulation (TM) strategy, we achieve ultrahigh responsivity (1500% at 10 ppm pure $${{\rm{NH}}}_{3}$$ NH 3 ), fast response and recovery time (28 and 43 s), ultralow power consumption (~6 mW), negligible baseline drift ($${{\rm{WO}}}_{3}$$ WO 3 ) device as part of the sensor array. Our dual graphene–MOx formulations and their integration with ultralow power CMOS through inkjet printing represent a significant step towards reliable and portable multi-analyte breath diagnostics.

It is common knowledge that the gate ringing of a power MOSFET is proportional to the dV/dt during the dynamic switching. In this study we show a particular situation when the gate ringing can be reduced significantly with a faster dV/dt. The faster dV/dt occurs when the driving current in the superjunction MOSFET increases, leading to faster charging of the parasitic capacitance. Initially, the gate ringing increases with the higher dV/dt. However, beyond a certain level the gate ringing starts to decline with further increase in the dV/dt. This abnormal phenomenon originates from the temporary turn-off the MOS channel during the turn-off transition.

Commercially available high voltage Silicon Carbide (SiC) Junction Barrier Schottky (JBS) are typically designed with advanced anode topography depending on the manufacturer and the specific current-voltage rating. The anode layout of JBS rectifiers affects a wide range of electro-thermal parameters such as the leakage current and the response of the diode to over-current events (surge current capability). In this paper, the effect of 3D anode geometries for the active area of 3.3 kV-20 A SiC JBS diodes is investigated in detail for both single and repetitive surge current events. By means of advanced 3D electro-thermal finite element simulations, a trade-off between the main factors which are contributing to the bipolar behavior activation is identified.

The planar Integrated Gate Commutated Thyristor (IGCT) concept is proposed to simplify the fabrication process of the device and improve the ruggedness as well as electrothermal performance of the device. The planar IGCT concept has been verified experimentally with 4.5kV devices fabricated on 4-inch Si wafers. Afterwards, the electrical characteristics of the planar IGCT were compared with that of the conventional (with trench or mesa gate) IGCT. Both the planar and the conventional IGCTs are fabricated with corrugated p-base referred to as High Power Technology (HPT) design. In addition, mixed-mode TCAD device simulations have been performed to verify the turn-off failure mechanism and to analyze the electro-thermal performance of the planar IGCT in reference to that of the conventional IGCT.

A novel Trench IGBT design, namely the p-ring Trench Schottky IGBT, with improved latch-up immunity and an enhanced safe-operating area is proposed. This design improves the performance of the FS+ IGBT by facilitating the collection of holes through a p-doped (p-ring) buried region connected through a Schottky contact to the source/cathode contact. This unique structure approach allows the improvement in the device reliability and it is shown under numerical studies to be highly effective in expanding the safe operating area (SOA), suppress dynamic avalanche, improve the latch up robustness and have the potential to improve the device switching operation.

A lateral trench SiC MOSFET with lateral conduction on the side walls was designed using an ultra-narrowbody (UNB) sandwiched by the trench walls. The p-body is designed to be very narrow in order to avoid any depletion region formed in its body. The structure is similar to a FinFET, but applied to a SiC device. The body width in the channel region of the fabricated UNB MOSFET was 55 nm. The drain current of the UNB and conventional MOSFET were 1.27 μA and 0. 11μA, respectively, at $V_{D S}=30 V$. The UNB structure presented a significant increase in the mobility, reaching values of over 200cm2/Vs. The result indicated a very prominent FinFET effect, resulting in very high mobility and hence very significant improvement in the channel resistance of SiC MOSFETs.

Partial SOI (PSOI) is revisited as a suitable High Voltage (HV) architecture for Power Integrated Circuits (PICs). The added process complexity compared to SOI RESURF is offset by the better heat conduction due to thinner BOX, the wider voltage range capability and the reduced parasitic capacitance to the Handle Wafer (HW). The new proposed platform technology is therefore particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low Ron, fast switching and reduced self-heating are essential. This work reports on the extension of a 200V PSOI process to 400V while providing competitive Ron and low HCI degradation.

We present a new experimental technique to characterise the crosstalk of a thermopile-based thermal imager, based on bi-directional electrical heating of thermopile elements. The new technique provides a significantly simpler and more reliable method to determine the crosstalk, compared to a more complex experimental setup with a laser source. The technique is used to characterise a novel single-chip array, fabricated on a single dielectric membrane. We propose a theoretical model to simulate the crosstalk, which shows good agreement with the experimental results. Our results allow a better understanding of the thermal effects in these devices, which are at the center of a rising market of industrial and consumer applications.

Temperature monitoring and thermal management of CMOS circuits / sensors is often required for long term circuit reliability and sensors temperature compensations. The ideal solution is to co-fabricate the temperature sensors along with the CMOS circuits and other sensors using CMOS materials and the same CMOS processes. In this paper we therefore, report on the fabrication and thermal characterization of such thin film temperature sensors. The thin film Resistance Temperature Detectors (RTDs) are made of single crystal p-type silicon on a silicon substrate using a Silicon on Insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process. The influence of thin film length and width on the response of RTDs has been investigated. Furthermore, the effects of aluminum (Al) and tungsten (W) metallization used for power tracks on the response of RTDs have been studied. To assess the performance of the RTDs based on SOI CMOS p-type silicon, in addition to sensitivity and TCR, their power consumption, linearity, hysteresis, repeatability, reproducibility and expected life span have also been evaluated. The p-type silicon RTDs consume very less power (i.e. 0.9 μW only) and demonstrate a sensitivity of 13.88 Ω / oC, which is much higher than the previously reported CMOS RTDs and widely used non-CMOS platinum RTDs. The RTDs also exhibit a linear response (98.9% fsd), an excellent repeatability and significantly low hysteresis with maximum variation of 0.2% between forward and reverse cycle. These RTDs also boast good reproducibility, within the wafer and wafer to wafer, with maximum sensitivity variation of 1.3% between different tested samples. The expected life span of the RTD is > 10 years. These inexpensive RTDs are therefore, good candidates for use as temperature sensors on CMOS circuits / sensors system.