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The traditional Thevenin equivalent Modular Multilevel Converter (MMC) model has poor versatility for the two working conditions of pre-charging and DC-side faults. In this paper, an improved Thevenin equivalent MMC model considering pre-charge conditions and DC side fault conditions is proposed. The model divides the pre-charging condition into a Controllable charging stage and an Uncontrollable charging stage. The DC-side fault condition is divided into the pre-blocking and post-blocking conditions of the converter. The circuit characteristics are analyzed, and the equivalent model topology is comprehensively improved to make it suitable for full-condition simulation, and a control strategy suitable for the equivalent model is proposed. The detailed model and the proposed improved equivalent model were built in PSCAD/EMTDC for comparison and analysis. The simulation results shows that the improved equivalent model can be applied to various working conditions, and the versatility of the traditional Thevenin equivalent model is improved.

This brief proposes a highly-integrated 3-phase ( $3\boldsymbol{\Phi }$ ) 4:1 resonant switched-capacitor (ReSC) converter with parasitic capacitor soft charging for Internet-of-Things devices, reducing the current stress at the point of load. Both the $3\boldsymbol{\Phi }$ resonant operation and the parasitic loss reduction schemes improve the power conversion efficiency. Also, this $3\boldsymbol{\Phi }$ -ReSC converter implements a flying capacitor pre-charge scheme to guarantee a safe startup. The chip, fabricated in a 65-nm CMOS process, occupies a silicon area of 1.39 mm2. We achieve a peak efficiency of 85.5% and a maximum output current of 130mA, in a mm-sized solution, with an input range of 2.3 V – 2.5 V.

for automobile applications, a high-switching 48-to-5V DC-DC buck converter is implemented with 0.5µm CMOS process and 0.5µm Gallium-Nitride (GaN)-on-Si process, including the pre-charge tracking technique, temperature-dependent controlled gate driver, and adaptive relaxation gate-drive control technique, which can increase the efficiency by about 8.8% and ensure the current capacity of Enhance-GaN (E-GaN). The inner local negative feedback loop can enhance the reliability and reduce the RON by 12mΩ. The peak efficiency is as high as 95.4%.

This article describes the memory cell proposed design of a low-power 8T SRAM cell. Two PMOS transistors are employed in this proposed approach, one of which is connected to the node voltage Q and the other one is connected to the Qbar. In order to remove the swing voltage at the bit and bit bar lines. When the cell is in working mode, the swing voltage is minimized, which reduces the dynamic power dissipation. Precharge voltage level is a technique in which a PMOS transistor acts as a switch and an NMOS transistor acts as a resister, resulting in a series of leakage current reductions when the transistors move from sleep to active and vice versa. The findings of the comparison show that the read, write, and hold mode operation for the proposed 8T SRAM cell is superior to that of the 6T SRAM cell. This is frequently because greater static noise margins are obtained, ensuring good bit cell write ability. All simulation results of read and write on the proposed 8T SRAM cell and current models of 6T SRAM cell have been applied to 130 nm CMOS technology utilizing the Symica DE tool.

A pulse-width-modulation (PWM) bidirectional ac-dc converter (i.e., active rectifier) with dc-faultblocking and self-pre-charge capabilities is proposed in this paper for low-voltage dc (LVDC) applications. The proposed converter, which is named as ”H5 + converter”, consists of an H4 bridge, a bidirectional switch, and a transient-voltage-surge (TVS) diode. The bidirectional switch and the TVS diode enable the dc-fault blocking and dc-bus self-pre-charge, while preserving the low common mode voltage noise and low leakage current of the converter. Additionally, the proposed H5+ converter has advanced features under a dc-side short circuit fault, such as fault diagnosis and fault recovery. Operation principles of the proposed converter are presented and analyzed. A down scaled prototype is built. Experiment results are shown and analyzed, including steady-state waveforms, common-mode performance, start-up dynamics, as well as dc fault blocking, fault diagnosis, and fault recovery. Moreover, the proposed converter is compared with other two dc-fault blocking converters for LVDC applications, in terms of converter capabilities, required devices, and power switch losses.

Emerging device-based crossbar-array can improve energy efficiency and performance in Spiking Neural Network (SNN) that performs numerous addition and multiplication operations. However, for the large size of crossbar array, delay for SL voltage development increases due to large capacitances of bit-line, and area overhead of peripheral circuit increases significantly. In this paper, we propose STT-MRAM architecture for SNN by minimizing area overhead and operation delay with peripheral circuit optimization. When the proposed method is applied, in 512×512 crossbar array, voltage development delay is reduced by 5.75 (ns), making it possible to perform faster inference operation.

A non-volatile memory designed to FLASH recollections and switch SRAM seems to be the Magnetic RAM (MRAM) proximity unit. Due to its inherent radiation hardness, Spin Transfer Torque Magnetic Memory (STT-MRAM) was also used for top-responsibility applications. CMOS circuit sensitive to radiation Pre Charge Sense electronic equipment (PCSA); but we are able to recharge the non-volatile storage ceaselessly to urge accurate details. Since the current advantages are abandoned by radiation effects, STT-MRAM cannot be used specifically for top radiation applications. In this paper, a new style in the change of PCSA STT-MRAM sensing circuit is proposed and the paper focused more on power and space with performance up gradation.

Dielectric Modulated Field Effect Transistor (DMFETs) offer advantages over many other well-known biosensors, making them extremely important in the fields of medicines and diagnostics. The paper aims to model a DMFET using the SPICE Level-3 model. This adapted model of the DMFET sensor can be used to detect the presence of both the charged as well as uncharged biomolecules in the nanogap cavity etched in gate-dielectric. The presence of both negatively charged and uncharged DNA molecules at the nanogap cavity changes the threshold voltage, thereby changing the on-current. Finally, this work integrates a low noise, low power pre-charge amplifier designed in 90-nm CMOS technology with the small-signal output of the adapted DMFET model. Charge sensitivity of 984.2 mV/pC was achieved without using any high magnitude passive feedback resistance.

Modular multilevel converter (MMC) is one of the most promising topologies in high-voltage applications. Kinds of modular topologies have been widely studied and discussed, but the dc fault ride-through capability and operating efficiency are still considered as a trade-off. In this paper, an enhanced alternate arm multilevel converter (AAMC) is proposed with the arm phase-shift modulation. By adjusting the phase-shift angle, the energy balance is achieved to allow a wide operating range. Combining the merits of low-cost half-bridge submodules and bipolar full-bridge submodules, the proposed T-type AAMC requires less power devices than traditional MMCs and AAMCs while keeps the dc fault ride-through capability. Since an additional ac arm stack is equipped in the T-AAMC, the dc-side based pre-charge methods is not applicable. The ac-dc coordinated pre-charge strategy is proposed to charge both the full-bridge stacks and half-bridge stacks to the reference voltage. Simulation cases are presented to validate the effectiveness of the proposed topology, modulation and pre-charge strategy.

Due to limited scalability and leakage power of CMOS-based logic circuit, Spin Transfer Torque (STT) device, which has the characteristics of a low area, zero leakage power, nonvolatile and infinite endurance, is one of the strongest candidates to overcome limitations of CMOS. Based on these characteristics, efforts have been made to develop STT-device logic circuit. However, STT-device logic circuit has encountered the problem of read reliability. To address read reliability issue, we propose a new Sense amplifier, named variation-tolerant separated precharge sense amplifier. This circuit, by using transmission gate and feedback, is resilient to process variation and has high read reliability. Simulation using the 65nm process is conducted to show the performance of the proposed sensing circuit. Simulation results demonstrate that the reading error rate of the proposed sense amplifier decreased by 68% and 37% respectively, compared to the conventional SPCSA and RESPCSA.

This paper proposes the pre-charge, discharge, and mini-UPS circuits of an auxiliary power network architecture for 10kV SiC-based power electronics building block. The design and working principle of all components are given with hardware prototypes and test waveforms. This architecture proposes a simple auxiliary-power-only pre-charge method, and increase the system reliability by having a rapid discharge circuit for dc-link, and a mini-UPS backup power supply.

This paper presents a cost-effective electromagnetic energy harvester (EMEH) based on wire-wound technology. It also shows the energy management system used to convert the EMEH's AC voltage to a DC one. The EH system is self-powered and does not require external sources or pre charge of any of its components and provides maximum power point tracking.

The intent of this paper is to analyze the working of the Magnetic Tunnel Junction (MTJ) based Ternary Content Addressable Memory (TCAM) with and without the match-line (ML) pre-charge. The designs of the memory with MTJs that have been implemented by previous researchers have made use of ML pre-charge. In this paper, for performance comparison, three different TCAM cells have been implemented - one with ML pre-charge (PC) and the other two, namely Self-Controlled Pre-charge free (SCPF) and Hybrid SCPF (HSCPF), without ML pre-charge. The designs were simulated on Cadence Virtuoso design tool using CMOS 180 nm technology with a supply voltage of 3 V. Arrays of different sizes for all three circuits were simulated and compared with respect to delay, area and power. The study revealed that, for an 8X16 array, the delay for SCPF and HSCPF is 79.77% and 25013.5% more than that of PC circuit, area occupied is 98.65% and 38.04% more than that of PC Circuit. Power consumed for SCPF and HSCPF arrays is 125.38% and 7.5% more than that of PC Circuit. This is in contrast to the Static Random Access Memory (SRAM) based TCAM circuits where power and delay for SCPF and HSCPF circuits is lesser than that of PC circuit.

The paper focuses on control analysis and operational issues of a recently proposed direct voltage regulated active capacitance reduction circuit, consisting of a small auxiliary capacitance interfaced to dc link by bidirectional dc–dc converter. The aim of such a system is replacing the bulk dc bus capacitor without escalating the ripple. While the hardware of the system under study is similar to some of the proposed active capacitance reduction solutions, the control structure is quite different. The primary goal of the controller is direct regulation of dc-link voltage rather than dc-link current, performed by most of existing solutions, thus avoiding the use of invasive dc-link current measurement/s. It is revealed that such an active capacitance reduction circuitry may be perceived as output-voltage regulated wide-input-range converter feeding a bidirectional power load. Such an arrangement was neither mentioned nor analyzed in the literature by far, requiring nontrivial and challenging control design. A dual-loop voltage-current arrangement widely used in typical power supplies is proposed to control the active capacitance reduction circuitry. It is shown that the control structure is sufficient to yield satisfactory performance even though the system possesses a slow unstable mode when absorbing power from the dc link. The revealed findings are fully supported by simulations and experimental results.

The deployment of electric vehicles (EVs) protects the environment by reducing carbon emissions. Since plugged-in EVs require energy from the power grid to charge their batteries, the charger component is inevitable. With the appropriate control, additional functions can be achieved with the existing charger’s converter topology. This paper discussed the implementation of a new control strategy in a three-phase off-board EV charger, which provided grid voltage regulation while charging the vehicle. The vehicle charging control (P-control) and grid voltage regulation control (V-control) were implemented in the back-end DC/DC converter and front-end AC/DC converter of the charger, respectively. The proposed P-control utilized the constant current/reduced constant current charging approach to rapidly charge the battery while alleviating battery deterioration. Meanwhile, the proposed V-control had the capability to regulate the grid voltage and DC-link voltage during the EV charging process. Besides the PSCAD/EMTDC simulation, experimental testing was performed on a 2 kVA laboratory EV charger to validate the control performance. While complying with the harmonic standards, the experimental results showed that the charger prototype effectively regulated the grid voltage to the pre-charge voltage while maintaining the DC-link voltage at 150 V during various charging currents of up to 5 A.

To improve light load efficiency, a three-phase photovoltaic (PV)-based microinverter may operate in single-phase, two-phase or three-phase mode depending on the available input power. Therefore, its dc-link capacitor may be subjected to large peak-to-peak voltage ripple when operating in phase skipping mode. This paper determines the minimum value of the dc-link capacitor by allowing the maximum acceptable voltage ripple on the dc link. This allows for the use of film capacitors instead of electrolytic capacitors in order to improve the microinverter reliability. Unfortunately, higher dc-link voltage ripple introduces harmonic distortion on the inverter output current waveform if it is not compensated for by the dc-link voltage controller. This paper proposes a simple synchronous control method to regulate the dc-link voltage with the presence of large voltage ripple. The dc-link voltage controller is synchronized with the phase-locked loop and samples the average value of dc-link voltage without introducing unwanted harmonics into the voltage sense path. Experimental results were obtained from a 300-W three-phase half-bridge microinverter prototype to verify the proposed dc-link voltage control performance. Inverter output current total harmonic distortion of 1.6% was achieved even though the dc-link peak-to-peak voltage ripple reached as high as 87 V with 219-V split dc-link voltage. Dynamic response is fast enough to easily track the most extreme ramp change in input PV power.

This paper presents a voltage-controlled distribution static synchronous compensator (DSTATCOM)-based voltage regulator for low-voltage distribution grids. The voltage regulator is designed to temporarily meet the grid code, postponing unplanned investments while a definitive solution could be planned to solve regulation issues. The power stage is composed of a three-phase four-wire voltage-source inverter and a second-order low-pass filter. The control strategy has three output voltage loops with active damping and two dc bus voltage loops. In addition, two loops are included to the proposed control strategy: the concept of minimum power point tracking (mPPT) and the frequency loop. The mPPT allows the voltage regulator to operate at the minimum power point, avoiding the circulation of unnecessary reactive compensation. The frequency loop allows the voltage regulator to be independent of the grid voltage information, especially the grid angle, using only the information available at the point-of-common coupling. Experimental results show the regulation capacity, the features of the mPPT algorithm for linear and nonlinear loads, and the frequency stability.

In this letter, the five-level packed U-cell (PUC5) inverter is reconfigured with two identical dc links operating as an active power filter (APF). Generally, the peak voltage of an APF should be greater than the ac voltage at the point-of-common coupling (PCC) to ensure the boost operation of the converter in order to inject harmonic current into the system effectively; therefore, full compensation can be obtained. The proposed modified PUC5 (MPUC5) converter has two equally regulated separated dc links, which can operate at no load condition useful for APF application. Those divided dc terminals amplitudes are added at the input of the MPUC5 converter to generate a boosted voltage that is higher than the PCC voltage. Consequently, the reduced dc-links voltages are achieved since they do not individually need to be higher than the PCC voltage due to the mentioned fact that their summation has to be higher than PCC voltage. The voltage balancing unit is integrated into the modulation technique to be decoupled from the APF controller. The proposed APF is practically tested to validate its good dynamic performance in harmonic elimination, ac-side power factor correction, reactive power compensation, and power quality improvement.

A novel write bitline (BL) charge sharing write driver (CSWD) and a half-V DD read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half-V DD to V DD essentially reduces the write dynamic power dissipation by 50%. Half-V DD precharging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and I on /I off ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).

To deeply understand interrupting phenomena in high-voltage circuit breakers, it is important to measure the electrical characteristics of switching arcs in high-speed gas flow at current zero. A ring-shaped capacitive probe is proposed to measure a spatial arc voltage distribution. The configuration of the probe is decided by considering the effects of arc position and arc radius. The difference between arc voltage distributions is distinguished for an interrupting current of 12 and 30 kA on interrupting tests using the circuit breaker model.

– This paper presents a zero voltage switching DC/DC converter for DC micro-grid system applications. The proposed circuit includes three half-bridge circuit cells connected in primary-series and secondary-parallel in order to lessen the voltage rating of power switches and current rating of rectifier diodes. Thus, low voltage stress of power MOSFETs can be adopted for high voltage input applications with high switching frequency operation. In order to achieve low switching losses and high circuit efficiency, asymmetric pulse-width modulation is used to turn on power switches at zero voltage. Flying capacitors are used between each circuit cell to automatically balance input split voltages. Therefore, the voltage stress of each power switch is limited at Vin/3. Finally, a prototype is constructed and experiments are provided to demonstrate the circuit performance.

In this paper, we describe an improved algorithm for arc flash calculations. This method can be used in any software that performs arc flash calculations to determine the incident energy, arc flash boundaries, and other related parameters for arc flash risk assessment purposes. The method provides a more sophisticated and precise way of calculating short circuit contributions to the fault location. To illustrate the effectiveness of the method, a typical renewable power plant (wind energy) with common types of protection is analyzed. The arc flash risk assessment results are compared in both the conventional way and the presented method. The new approach is called the “Integrated Method.” This method is an accurate way of modelling the short circuit contribution of the devices, which can potentially change the total short circuit current at the fault location. This Integrated Method considers the decay of the contributing machines and also the devices where currents are interrupted due to a protection device. It also accounts for the current decays over time.

This letter presents a voltage-controlled capacitor that varies from 20% to 100% of the rated capacitance (1 μ F) with a control voltage from half of the voltage rating to 0 V. Capacitance, self-resonant frequency, and equivalent series resistance were measured with respect to the control voltage. An equivalent circuit and a nonlinear model derived from relationship between permittivity and electric field were created and implemented in SPICE. A buck converter with input of 12 V, output of 5 V, and switching frequency of 500 kHz was built to demonstrate the change from 85% to 40% of the rated capacitance of the voltage-controlled capacitor. The error between the simulation and experiment was limited within 10%, which verifies the model.

To solve some problems caused by the ac control method used for the existing modular multilevel dc–dc converter (MMDC), this paper has proposed a new MMDC topology with a wide range of output voltage by means of dc control. By reconstructing the submodule structure, the converter has a power branch and an auxiliary balance branch, which are used to transmit dc power and balance the capacitor voltage, respectively. Both dc analysis and control method are adopted to establish a mathematical model so as to deduce the mathematical relationships between the key electrical parameters. Moreover, what have been done include analyzing the self-balancing principle of the capacitor voltage and the mechanism of the auxiliary balance branch, calculating the related parameters of the capacitor voltage fluctuation, and presenting a dc closed-loop control strategy based on a small-signal model. The analyses of the steady and dynamic states in combination with simulation and experiment show that the proposed converter can stably operate in the mode of dc control, with a large adjustable range of output voltage, a small fluctuation in voltage of the capacitor, and the ability of the inductor to suppress the spike of the auxiliary balance current effectively so as to reduce the impact on the device.

This paper discussed the design and development of a 2 kVA three-phase off-board electric vehicle charger prototype with a practical voltage control, where the procedures of the experimental construction were comprehensively presented. For the experimental setup, the effectiveness of the interface circuits and auxiliary power supply units were individually validated. Moreover, the electric vehicle charger utilized a Digital Signal Processor to employ the control strategies of vehicle charging and power grid voltage regulation. The proposed control can simultaneously charge the battery of electric vehicle, maintain a constant DC-link voltage and also provide the appropriate reactive power compensation to regulate the grid voltage to the desired level. While complying with the power quality standards, the experimental results had validated the practicality of the integrated electric vehicle charger and the control performance. The charger prototype had effectively regulated the grid voltage to the pre-charge voltage of 0.96 per unit while maintaining the DC-link voltage at 150 V during various charging currents of up to 5 A.

As a key element of a power system, a circuit breaker (CB) requires regular maintenance. Intelligent online condition assessment is increasingly becoming a requirement for key items of power plants, including CBs. The interruption chamber, as the most critical part of the CBs, plays an important role in the proper operation of CBs. Online assessment of this part is difficult from a technical perspective due to the high noise level and presence of a transient recovery voltage. This paper proposes a set up for the online measurement of the CB arc voltage during trip/close operations. In addition, a method has been proposed to evaluate the remaining useful lifetime of the interruption chamber based on the measured arc voltage and current. The setup and the proposed approach are verified experimentally.

Wireless power transmission (WPT) based on near-field inductive coupling principle is a promising solution to the power supply issue of a freely moving capsule robot (CR) that employs dc motors as actuators. However, the limited inductive power can cause a voltage drop when dc motors start or stall, because short-time peak power is required. To handle the voltage drop issue, we propose the use of a novel power management circuit (PMC) that consists of four successively connected segments of a full-bridge rectifier for ac–dc conversion, a buck dc–dc converter for highly efficient voltage reduction, a power buffer for power storage and short-time power supply, and a low drop-out (LDO) regulator for voltage stabilization. The power buffer is implemented with a super-capacitor array (SCA) that employs the output voltage of the dc–dc converter as its charging voltage. To analyze and optimize the PMC containing the SCA (PMC-SCA), a model is built based on deducing the input resistance relations between each pair of adjacent segments, and its correctness is then validated experimentally. A comparison between the PMC-SCA and the traditional PMC (a rectifier + a regulator) is also conducted, and the former shows superiorities in both reducing voltage drop and improving safety related to temperature rise of onboard receiving coil (RC). Finally, a primary PMC-SCA prototype measuring $\Phi $ 13 mm $ \times $ 4 mm is integrated to an inchworm-like CR for effectiveness validation; the CR working voltage is measured to be higher than 3 V at all times, which ensures the proper functioning of the CR.

DC power relay is a key electromechanical component widely used in electrical vehicles, photovoltaics, as well as more-electric aircrafts for energy managing, power conversion, and distribution. As the voltage and current increase due to relay switches, arc discharge becomes an unavoidable and significant issue during the operation of the dc high-power relay. Bridge-type contact and external permanent magnets are spontaneously employed in its arc chamber to accelerate the quenching of arc. In this paper, the complicated arc discharge plasma in a dc power relay has been investigated by using both experimental and numerical approaches. Initially, arc dwell and arc restriking characteristics during the arc motion phase are presented by analyzing the voltage and current waveforms and arc images acquired in carefully designed breaking experiments. The arc driven by a transverse magnetic field with a variety of flux densities and the influence of flux densities on arc voltage and dwell are preliminarily discussed based on the experimental results. Then, to reveal the arc physics and to determine the influence of transverse magnetic field on arc motion characteristics, a simplified model based on the magnetohydrodynamic (MHD) theory is built and three cases with different magnetic field are calculated. The simulated arc behaviors including distributions of the temperature and current density are presented. The mechanism underlying the influence of transverse magnetic field on the arc motion is analyzed according to arc root transfer and arc voltage variation. In addition, to understand the formation of the arc restriking, the critical breakdown electric-field strength inside the arc gap is also calculated based on streamer breakdown theory. The parameters in the space occupied by earlier arcs, as predicted by the MHD simulations, are used in the breakdown calculation. Results show that the critical breakdown voltage reduces remarkably along with growth of the operating voltage and breaking current, and the arc dwell time can be reduced by strengthening the external magnetic field within a reasonable extent.

This paper presents a grid supported solar energy conversion system with an adjustable dc link voltage for common point of interconnection (CP) voltage variations. A two-stage circuit topology is proposed, wherein the first stage is a boost converter, which serves for maximum power point tracking, and the second stage is a grid tied voltage source converter (VSC), which not only feeds extracted solar photovoltaic (PV) energy into the three-phase distribution system but also serves for harmonics mitigation, reactive power compensation, and grid current balancing. An interweaved double-frequency second-order generalized integrator-based control algorithm is proposed for control of this multifunctional VSC, which possesses the feature of good steady-state performance along with fast dynamic response even under sudden load changes at CPI. Moreover, a feed-forward term for the solar PV contribution is used to enhance the dynamic response for climatic changes and CPI voltage variation. An adjustable dc link voltage structure is used to accommodate CPI voltage variation, which helps in reduction of losses in the power circuit. To implement adjustable dc link voltage structure, the reference dc link voltage is adjusted with variation in CPI voltage in real time. A proportional–integral controller is used to regulate dc link voltage to set reference value. A wide range of experimental results are shown to demonstrate the features of the proposed system. The total harmonic distortion of grid current has been found well under IEEE-519 standard even under nonlinear loads at CPI.

This paper presents a study of proposed approach founded on series active power filter based on photovoltaic array (PV-SAPF) which is controlled by classical PI using pulse width modulation inverter (PWM). The proposed system is connected to grid system to feed linear and nonlinear loads to handle deep sags, swells voltage, voltage distortion and power factor crushing caused by any electrical perturbation. In the other hand, the excess of the energy is injected into the mains when the network is not affected and after compensation. To prove the effectiveness of the planned system, the PV-SAPF is carried out using MATLAB / Simulink environment. The results Simulations results proved the ability and the efficiency of the proposed system in mitigation the harmonic voltage distortion, correction the voltage sag and swell, power factor improvment and power quality enhancement.

This paper presents a work that was aimed to develop methods along with test facilities for characterizing the arc/contact movement in low-voltage miniature circuit breaker which has a related current under 125 A, and to find its relation with the short-circuit current/voltage in the circuit. The method consists of: 1) the high-speed camera for obtaining the image of the arc or contact movement; 2) the data acquisition system that measures the current during the short-circuit break; and 3) the circuitry system that establishes the synchronization of the arc movement capturing and the current acquisition. In particular, two methods were developed for this purpose: one based on analog signal and the other based on digital signal. The experiment shows that the accuracy of the synchronization, dependent on the sampling rate of the high-speed camera, is about from tens of microseconds to hundreds of microseconds with both methods. The two methods have their own advantages and disadvantages, and they can be tailored to applications for the best performance.

Traditionally, series electric vehicles, such as bus, construction machine like bulldozer, carry a certain capacity of power batteries, capacitors or other energy storage units. However, these energy storage units not only occupy a few large of vehicle space leading to be uncomfortable for passengers and driver, but also increase production cost, and reduce the powerline's reliability. In order to make the powerline system more compact and reliable, a new series electric system without energy storage unit is proposed in this paper. This new powerline's mathematic models are established. And a fuzzy PI closed-loop control strategy with parametric self-tuning function control is put forward to stabilize the powerline DC-link's voltage fluctuation. The models and control strategies are simulated in Matlab/Simulink software environment. The results give a verification on the new powerline's configuration, as well as the proposed control strategy.

This paper compares different methods for voltage-dip characterization. Those methods are based on earlier proposed algorithms for extracting three-phase characteristics (dip type, characteristic voltage, and so-called “PN factor”). The difference between the 12 methods being studied in this paper is in the way in which the time variation of those characteristics is treated to result in single-event characteristics. The methods are applied to 259 measured voltage dips, and the performance of the different methods is compared. It is found that small differences in the method can result in big differences in results. From the comparison, two methods are selected and recommended for inclusion in international standards.

This study examines the use of superconducting magnetic and battery hybrid energy storage to compensate grid voltage fluctuations. The superconducting magnetic energy storage system (SMES) has been emulated by a high-current inductor to investigate a system employing both SMES and battery energy storage experimentally. The design of the laboratory prototype is described in detail, which consists of a series-connected three phase voltage source inverter used to regulate ac voltage, and two bidirectional dc/dc converters used to control energy storage system charge and discharge. "DC bus level signaling" and "voltage droop control" have been used to automatically control power from the magnetic energy storage system during short-duration, high-power voltage sags, while the battery is used to provide power during longer term, low-power undervoltages. Energy storage system hybridization is shown to be advantageous by reducing battery peak power demand compared with a battery-only system, and by improving long-term voltage support capability compared with an SMES-only system. Consequently, the SMES/battery hybrid dynamic voltage restorer can support both short-term high-power voltage sags and long-term undervoltages with significantly reduced superconducting material cost compared with an SMES-based system.

This paper introduces a cascaded H-bridge multilevel converter (CHB-MC)-based StatCom system that is able to operate with extremely low dc capacitance values. The theoretical limit is calculated for the maximum capacitor voltage ripple, and hence minimum dc capacitance values that can be used in the converter. The proposed low-capacitance StatCom ( LC -StatCom) is able to operate with large capacitor voltage ripples, which are very close to the calculated theoretical maximum voltage ripple. The maximum voltage stress on the semiconductors in the LC -StatCom is lower than in a conventional StatCom system. The variable cluster voltage magnitude in the LC -StatCom system drops well below the maximum grid voltage, which allows a fixed maximum voltage on the individual capacitors. It is demonstrated that the proposed LC -StatCom has an asymmetric V–I characteristic, which is especially suited for operation as a reactive power source within the capacitive region. A high-bandwidth control system is designed for the proposed StatCom to provide control of the capacitor voltages during highly dynamic transient events. The proposed LC -StatCom system is experimentally verified on a low-voltage seven-level CHB-MC prototype. The experimental results show successful operation of the system with ripples as high as 90% of the nominal dc voltage. The required energy storage for the LC -StatCom system shows significant reduction compared to a conventional StatCom design.

In this paper, a method for suppressing the low-frequency portion of dc-link ripple inevitably present in power conversion systems with reduced capacitance is proposed. The discussed active capacitance reduction circuitry (consisting of a feedback-controlled shunt-connected bidirectional buck-boost converter, terminated by a small auxiliary capacitance) directly regulates the dc-link voltage, utilizing a dual-loop control structure with parallel-connected multiresonant-bank-enhanced voltage loop stabilizing controller to achieve nearly constant, low-frequency-ripple-free steady-state dc-link voltage. Consequently, the proposed active capacitance reduction system may be perceived as a virtual infinite capacitor from the dc link point of view. The suggested circuitry is successfully applied to a single-phase commercial power factor correction front end in a nearly plug-and-play fashion. The control algorithm effectiveness is fully supported by simulations and experimental results.

Varactors are often used in phase-locked-loop (PLL) circuits for dynamic frequency control. However, the voltage and current ratings of varactors are too low to be used in most power electronic circuits. This paper proposes a transistor-controlled variable capacitor (TCVC), which functions similar to varactors in that its equivalent capacitance can be controlled by a dc voltage. However, TCVC can handle high voltages and currents so that it can be used in dc-ac power converters of wireless power transfer (WPT) systems such as an autonomous push-pull resonant converter to adjust its zero voltage switching (ZVS) frequency so that the operating frequency of the system can be stabilized to simplify the circuit and EMI filter design particularly for WPT systems with multiple power pickups while maintaining soft-switching operation of the converter against magnetic coupling and load variations. The relationship between the equivalent capacitance of the TCVC and the dc control voltage is developed by theoretical analysis and verified by experimental results. A prototype circuit is built with a PLL controller to demonstrate that the soft-switching condition of the converter is maintained when the operating frequency is locked in at 1.65 MHz under load and magnetic coupling variations.

The read or write operation on a core cell imposes a stress on the unselected core cells of that row, which is equivalent to that of a read operation. Such stress on the unselected core cell is termed as Read Equivalent Stress (RES). Considering RES principal, the power dissipation becomes very important constraint during fault testing of Static Random Access Memories (SRAMs) using March Tests. In order to minimise the power dissipation during testing of SRAMs, it has been found that the power consumption associated with RES is wholly unnecessary and is focused to be completely eliminated in our work. The novel RES Eliminating Pre-Charge Control Logic has been proposed to eliminate RES which exploits the fact that during test, the addressing sequence of SRAM is known well in advance. The proposed RES Eliminating Pre-Charge Control circuit ensures the complete elimination of RES as well as of power dissipation contributed by RES during test of SRAM. We have observed and analysed that the proposed R...

A novel voltage-doubling circuit with parallel-resonant dc–dc converter is proposed. The converter consists of full-bridge inverter, resonant tank, high-frequency high-voltage transformer, and voltage-doubling circuit. In the high-voltage applications, low-output voltage ripple has been given much attention. The output voltage step-up ratio is increased by two parts. One is a high-frequency high-voltage transformer and the other is a voltage-doubling circuit. The novel voltage-doubling circuit can not only reach a higher output voltage but also reduce output ripple to a lower level than the conventional one. Therefore, while maintaining the same output voltage, the transformer's turn ratio can be reduced compared with the conventional voltage-doubling circuit. The output power can be adjusted by the phase-shift control technique. In addition, combining this technique with the parallel resonant tank can make all the switches achieve zero voltage turn on (ZVS). The operating principles, steady-state analysis, and the parameter designs are discussed in this paper. Finally, a prototype circuit with 400-V input voltage, 40-kV output voltage, and 300-W output power is developed in the laboratory to verify the performance of the proposed converter.

Various circuit breaker models have been developed as a tool to evaluate the breaker interrupting capability and to investigate interaction between the breaker and the external circuit. This paper presents selected models of high voltage SF6 circuit breakers (Cassie–Mayr, Schwarz–Avdonin, and an ideal switch with a predefined chopping current level), followed by analysis of the models impact on the 400 kV overhead line fault clearing process. Several study cases have been performed to demonstrate the impact of the circuit breaker model on the arcing time and on the transient recovery voltage (TRV) during breaking of the near-to-generator faults. The results obtained indicate that the arc voltage introduced by the circuit breaker model can force the fault current zero crossing and in consequence can significantly change the breaking conditions. It particular, in the study cases where the arc voltage has significant impact on the breaking conditions (such as the near-to-generator fault), the models applied accurately represent arc voltage during the entire current interruption process.

This paper presents the impact of temperature on electrical characteristics of a free-burning arc including voltage and power. By decreasing the arc current during the extinction, the arc temperature decreases as well. Beside, to change the arc temperature during arcing time two substances are applied near to the arc. High-speed camera images confirm a strong evaporation of the coating materials after high current arc ignition. An electrical arc model based on physical parameters is modified to determine the electrical characteristics of the arc in case of changing temperature. This model can be used as a black-box model to reproduce the electrical characteristic of the arc regarding temperature variation.

A capacitor pre-charge technique based CMOS relaxation oscillator is proposed to improve its linearity adaptively. The effect of comparator offset and delay variation across PVT will be counteracted by the pre-charge process because it is included both in the effective charge process and the pre-charge process. Then, the non-linearity of the oscillator caused by the delay of the control circuit and the offset voltage of the comparator can be eliminated. The proposed relaxation oscillator with a typical frequency of 100 kHz is implemented in 0.5 μm Bipolar-CMOS-DMOS process. Measured results show that

This paper presents a CMOS fully-integrated temperature sensor based on a relaxation oscillator for IoT applications. To reduce power consumption, this sensor utilizes the half-period pre-charge compensation relaxation oscillator and uses a time-to-digital convertor (TDC) instead of analog-to-digital convertor (ADC) to count. Besides, the current distribution circuit is employed to improve temperature accuracy. The proposed sensor is implemented in 0.18 µm CMOS and occupies an area of 0.11 mm2. Measurement results show that the temperature sensor achieves an inaccuracy of −0.3/+0.27 °C across −15°C to 65°C after 2-point calibration. The chip consumes 1.3 µW at 27°C with a 650 mV voltage supply.

The pre-charge sense amplifier is essential for the design of hybrid circuits based on the combination of CMOS and spin devices like magnetic tunnel junction (MTJ). The double tail sense amplifier (DTSA) offers better reliability, power efficiency and good performance. This paper offered a novel modified double-tail sense amplifier' (MDTSA) and compared its performance in terms of delay, power and sensing error with the existing DTSA.

A Content Addressable Memory compares input search data with the stored data and hence match data address is returned. In CAM the user provides the data and gets the address of matched data. CAMs are consisting of conventional semiconductor memory with extra comparison circuitry that enables search operation. Parallel search scheme in CAM enables high speed applications but the major challenge is high power-consumption, to overcome this drawback now a days FinFET technology is used. In the existing NAND and NOR CAM cells there is a problem of continuously pre-charging of match lines which consumes more power that can be avoided by pre-charge free logics to drive a match line. The paper presents 16 x 16 CAM arrays using pre-charge free (PF) logic and optimized MLSA design to sense matched data are built using FinFET 18nm technology. Compared to conventional CAM, proposed PF CAMs improves the performance, reduces the power and energy consumptions greatly.