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It is crucial for the successful application of high-temperature superconducting (HTS) power transformers that they are able to survive under abnormal operations, such as a short-circuit fault. Modeling, based on the design of a four-winding three-phase HTS power transformer, suggests severe boiling will occur on the surface of the winding during a short-circuit fault and will jeopardize the turn-to-turn insulation of the HTS power transformer. In this paper, a turn-to-turn insulation breakdown experiment platform involving the introduction of boiling on the surface of electrode has been built. Nomex 410 paper, one of the candidates for turn-to-turn insulation in the design of the HTS power transformer, was tested. The characteristics of dielectric strength of Nomex 410 in three different thicknesses (0.13, 0.18, and 0.25 mm) have been investigated, without boiling, as well as under different boiling situations, in an open bath of liquid nitrogen. The voltage application methods applied during both experiments test the electrical breakdown of Nomex 410 under a dynamic situation. The experiment results show that when under film boiling, compared to the test results for nucleate boiling, the dielectric strength of Nomex 410 paper decreases by approximately 38% of the value when no boiling is involved. Moreover, it is verified that the presence of an electric field accelerates the heat transfer between the liquid nitrogen and the heated electrode. [ABSTRACT FROM PUBLISHER]

In pulp and paper plants, power transformers play a critical role in process continuity. These transformers are subject to internal short circuits, external short circuits, and abnormal operating conditions. The following protection challenges to power transformers will be explored, and methods to improve the protection are provided. First, remanence in a current transformer (CT) may cause misoperation of phase differential protection due to compromised CT performance. Heavy through-faults, sympathetic inrush, and recovery inrush all cause high current. This, combined with high remanent flux, can create a security issue. IEEE CT performance calculations will be used to support the use of dual slope differential characteristics to promote secure differential protection operation when challenged with unequal CT performance. Second, on transformer energizing, the second harmonic current has been traditionally used as a means to prevent phase differential misoperation. Certain transformers may not exhibit high enough the second harmonic, causing a dependability issue if the restraint is set too low. The use of the second and fourth harmonics for inrush detection will be shown to enhance the reliability during energizing inrush situations. Third, overexcitation can occur from abnormal operation of the utility system or the plant's excitation control. Causes of overexcitation will be outlined and the use of volts per hertz protection is explored. With overexcitation occurring from system voltage rise, the phase differential protection has been traditionally blocked using the fifth harmonic restraint. This may cause an undesired nonoperation of the phase differential protection if an internal fault occurs while the transformer is overexcited, causing a delay in tripping and severe damage to the transformer. A technique using adaptive phase differential pickup value will be illustrated to overcome this challenge. Finally, on resistance-grounded power transformers, phase differential protection sensitivity for ground faults near the neutral is decreased. The use of ground differential protection will be explored and the increased sensitivity gained will be demonstrated. [ABSTRACT FROM AUTHOR]

Fuses are commonly used to provide medium voltage (MV) protection to distribution transformers. Unfortunately, there are certain deficiencies introduced when primary-side fuses are used. In paper mill power systems, given the unique organization of the paper mill loads around individual feeders to facilitate load shedding, it may be advantageous to provide transformer differential relay protection from the primary of the transformer to the load side of the main secondary breaker instead of primary fuse protection. This protection can then trip either a primary-side grounding switch (with fuses) or a primary-side feeder circuit breaker using a fiber or a WiMAX (Worldwide Interoperability for Microwave Access) connection. Protection against overload is provided by a secondary main circuit breaker and by design. [ABSTRACT FROM AUTHOR]

Voltage-controlled three-phase three-leg inverters are widely applied in various occasions. The inverters are generally switched to the current-controlled mode to limit the fault currents when short-circuit faults happen. Under symmetrical fault, the inverter can be controlled as a symmetrical, three-phase current source. However, the voltage limiting will happen under asymmetrical fault. As a result, the fault phase currents will be distorted and cannot be completely controlled. Considering that the voltage limiting is mainly caused by large load impedance of healthy phase under asymmetrical fault, the voltage limiting is avoided by paralleling the virtual impedance with the output filter capacitor in this paper. As a result, the current limiting loop is not broken and the fault phase currents can be effectively controlled. The implementation of virtual impedance in control system and the influence of virtual impedance on the stability of system are also analyzed in detail in this paper. The theoretical results are validated by experiments. [ABSTRACT FROM AUTHOR]

Traditionally, water mobility inside the cellulosic insulation, as those used in power transformers, has been modeled using the so-called Fick's diffusion theory, considering that the water movement in this porous material only depends on local conditions, such as temperature and moisture concentration. However, recent experimental works have demonstrated that the moisture movement inside the cellulose insulation could be also influenced by a global condition, that is, the insulation's thickness. In this paper, the influence of the insulation thickness in the mobility of moisture inside the cellulosic materials, such as Kraft paper and pressboard, is analyzed. In addition, the improvement in moisture dynamics estimation obtained when this variable is included into the diffusion models has been proved. [ABSTRACT FROM PUBLISHER]

Ground faults in field/rotor and generator stator circuits are serious events that can lead to damage, costly repair, extended outages, and loss of revenue. This paper explores advances in field/rotor circuit ground fault and stator ground fault protection. These advanced protection strategies employ ac injection, ground differential protection, and the use of hybrid grounding to reduce both internal generator ground fault levels and facility ground levels in utility-paralleled operating modes. [ABSTRACT FROM AUTHOR]

Fault diagnosis and fault tolerant (FT) control of electric drive systems have been extensively studied by many researchers. Naturally, one would like to use fault diagnosis information to improve FT control to achieve good post-fault performance while it is safe to do so. In this paper, a novel FT control method is proposed for permanent magnet synchronous motor with inter-turn short circuit fault. Given fault severity, the proposed FT control can reduce torque ripple while keeping reasonable torque output. The theoretical derivation, simulation, and experimental validation are presented in this paper. [ABSTRACT FROM AUTHOR]

This paper provides the electrical equivalent circuits of high-resistance grounded (HRG) power systems other than the delta–wye-connected utility power supply transformer included in Part I of this paper. This paper also provides the HRG of a medium-voltage generator for connection to an industrial power system and to a utility power system, and this paper discusses a line–ground fault with fault resistance. Three-line diagrams of ungrounded power systems are also included to illustrate the HRG application and its effect on the ground fault current during the line–ground fault. The damage at the fault location is based on the assumption that the fault remains a line–ground fault until it is cleared by appropriate ground fault protection relays. The fault resistance and the fault current that have an effect on the damage at the fault location are included. This paper provides guidance to update the current edition of the IEEE STD. 142, with respect to HRG systems. [ABSTRACT FROM AUTHOR]

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan. [ABSTRACT FROM AUTHOR]

Cable fault location is generally much more difficult if cable defect has not reached the level of serious breakdown. Traditional methods such as time domain reflectometry (TDR) and partial discharge detection cannot solve this problem well due to their low sensitivity. This paper proposes a new non-destructive detection method based on the impedance spectroscopy (IS), which can effectively locate soft faults in the cable. In this paper, a numerical model for cable with distributed parameters is established firstly. Based on this model, cable faults are extracted from the imaginary part of impedance spectrum with Discrete Fourier Transform (DFT). The Chebyshev window is introduced to suppress interference and enhance signal-to-noise ratio, which improves the sensitivity and accuracy of fault location significantly. Experiments and simulations show that this method can well locate multi-segment defects in cables with good accuracy. The window function successfully amplifies the normalized amplitude of faults and improves the positioning accuracy. Compared with other method, this method reduces distortion points effectively. The fault location error is within 0.53%, which has great potential for field application. [ABSTRACT FROM AUTHOR]

The rising cost of production testing for a system-on-a-chip (SoC) is one of the crucial matters to chip makers, due to long test time and costly automated-test-equipment. This paper proposes a spectral leakage-driven built-in self-test (BIST) scheme to precisely predict the nonlinearity of mixed-signal circuits in the loopback mode, thereby accomplishing cost-effectiveness (compared to previous BIST-based works). A digitally synthesized single-tone sinusoidal stimulus used for conventional harmonic testing is incoherently sampled by a device under test (DUT). The DUT output signal exhibits the correlation between the DUT harmonics and the spectral leakage introduced by the incoherent sampling. The DUT output signal is then fed to another DUT through a loopback path, so that the harmonics of a pair of DUTs are correlated with the spectral leakage on the loopback response; the magnitude of the spectral leakage is considered as a weighting factor on the harmonic magnitude of those DUTs. The correlation is quantitatively modeled as characteristic equations in , and postprocessing predicts the harmonics of the two individual DUTs, by simultaneously solving the characteristic equations using on-chip DSP core available in an SoC. Simulation and hardware measurements validated that this paper can be practically used for production testing by showing less than 0.3 and 0.6 dB of the prediction errors, respectively. [ABSTRACT FROM AUTHOR]

This paper describes a test compaction procedure that combines the advantages of using multicycle tests for test compaction with the advantages of using both broadside and skewed-load tests for increasing the fault coverage and achieving test compaction. The procedure is the first to combine these two concepts in a single procedure. The combination is made possible by a definition of a multicycle skewed-load test that is suggested in this paper, and complements the definition of a multicycle broadside test. Experimental results demonstrate the effectiveness of multicycle broadside and skewed-load tests in achieving test compaction for benchmark circuits. [ABSTRACT FROM AUTHOR]

Multicycle tests achieve test compaction by increasing the number of clock cycles between scan operations and reducing the number of tests. Tests in a compact multicycle test set typically have different numbers of clock cycles between their scan operations. This creates an opportunity to improve the test set by increasing the numbers of clock cycles between the scan operations of the tests, without increasing the number of tests and without exceeding a bound $L$ on the number of clock cycles. Motivated by this observation, this paper studies the padding of multicycle broadside and skewed-load tests for transition faults. After padding, all the tests have $L$ clock cycles between their scan operations. This paper makes several observations and defines new types of multicycle tests that are supported by commercial tools to allow padding to be performed without losing fault coverage. The new types of tests can be used for achieving a higher fault coverage, further test compaction, or an improved test set quality within the bound $L$. This paper develops padding procedures and presents experimental results for benchmark circuits to demonstrate these effects. [ABSTRACT FROM AUTHOR]

After a transformer failed following a double-phase fault, there was an interest in understanding how the fault mechanism led to the failure. This paper investigates this fault condition in detail and demonstrates the underlying challenges in correcting the failure. The electrical and thermal system models were developed and simulated to analyze the transformer response under double-phase fault conditions. Experimental measurements validated the simulation results on a real three-phase distribution transformer. This paper presents the results from simulated and experimental analysis from double-phase fault on a Yg–Yg distribution transformer. [ABSTRACT FROM AUTHOR]

Transformers are essential components of electric power generation, transmission, and distribution, and the majority of power transformers rely on liquid dielectrics as an insulating medium and for heat transfer. At present, the most common liquid dielectrics used are the mineral oils, which are produced from the middle range of petroleum-derived distillates. In recent years, concerns have been expressed regarding the presence of polynuclear aromatic hydrocarbons in mineral oils, because in the event of a transformer fire, or explosion, polynuclear aromatic hydrocarbons could readily be released into the environment. This situation has put mineral-oil-filled transformers in sensitive areas, such as inside buildings, in residential areas, and near schools or hospitals, under scrutiny. Human health and environmental concerns have led to efforts to develop alternative transformer insulating oils for use in these sensitive areas. In particular, vegetable oils have drawn the most attention, and research on the properties and performance of vegetable oils has been carried out in a few laboratories [1]. [ABSTRACT FROM PUBLISHER]

A logic diagnosis procedure provides information about the defects that are present in a faulty unit as a set of candidate faults. To obtain smaller, and more accurate, sets of candidate faults, a diagnostic test generation procedure produces a test set that distinguishes fault pairs. This paper observes that large sets of candidate faults are obtained when multiple defects are present in a faulty unit, even if a diagnostic test set is used for logic diagnosis. This points to the possibility that fault pairs do not provide a complete set of targets for diagnostic test generation. This paper analyzes the conditions that cause a large set of candidate faults to be formed under a particular logic diagnosis procedure and suggests new targets for diagnostic test generation. The experimental results for benchmark circuits demonstrate that a diagnostic test set can be improved by adding diagnostic tests for the new targets. [ABSTRACT FROM AUTHOR]

Data recorded by intelligent electronic devices such as protective relays contain a wealth of valuable information that can be used beyond post-mortem analysis of fault events. The objective of this paper is to propose algorithms to estimate zero-sequence line impedance and fault resistance using protective relay data collected during short-circuit fault events. Protective relaying data may be available from one or both ends of the line. For the latter, they may be collected at different sampling rates with dissimilar fault time instants. Furthermore, they may be unsynchronized. This paper presents approaches which uses measurement data from one and both ends of the line. The efficacy of the proposed algorithms presented in this paper are demonstrated using a test case as well as field data. The error percentage of the zero-sequence line impedance magnitude estimated using the data from both ends of a two-terminal line was under 3% for all the test cases. The error percentage in estimating the fault resistance was less than 1% in the test cases presented. [ABSTRACT FROM AUTHOR]

This paper deals with the short-circuit analysis of distribution systems dominated by Voltage Source Converters (VSCs). A novel methodology has been proposed in this paper for short-circuit calculation of power systems populated with VSCs where the control modes and potential current-saturated operation of power converters are considered. The studied distribution system has been modeled using an element-based steady-state formulation that includes the converter equations in both normal operation and fault scenarios. Then, equilibrium points of the studied distribution system are identified by solving the established systems of equations for different potential current-saturation states of the VSCs. The methodology identifies possible solutions involving different saturation states of different converters. The proposed methodology is applied to a specific case study of a distribution system penetrated with VSCs in both grid-forming and grid-following control. The short-circuit analysis results indicate that VSCs operation shows a significant impact on the short-circuit equilibrium points of the studied system. In addition, multiple equilibrium points may exist depending on whether the grid-forming converter is saturated or not. The existence of multiple equilibrium points is validated through dynamic simulations. [ABSTRACT FROM AUTHOR]

Flexible DC distribution networks have been widely developed because of their advantages of high efficiency, low cost, and easy access to renewable energy. However, as distribution networks have more ends than the two-terminal transmission line, it is more challenging to protect them and locate their faults. Therefore, this paper proposes a modified T-source circuit breaker to protect against DC faults. Based on the proposed circuit breaker, an integral fault location method using double-terminal asynchronous data is proposed. The accuracy of the algorithm is not affected by the fault resistance. There are no differential terms in the algorithm, which greatly reduces the sensitivity to noise. The integral algorithm can remain steady when the voltage and current are zero in oscillation and attenuation periods. This constitutes the main contribution of this paper. Finally, it is verified by simulation and experiment that the proposed circuit breaker can isolate the power source within a short time in the typical DC distribution network. Under a noise of 30 dB for simulation, the location error of the proposed algorithm is <0.4% when the fault resistance is 0.5 Ω–500 Ω. [ABSTRACT FROM AUTHOR]

The commutation failure (CF) is the most common fault in line-commutated high voltage direct current (LCC-HVDC) systems that may lead to the transient overvoltage in the sending-side system. In the worst condition, the CF may lead to large-scale wind turbine tripping. To resolve this problem, the mathematical relationship between the reactive power consumed by the rectifier and DC voltage, DC current is derived. Then, a transient overvoltage calculation method is proposed in this paper. Furthermore, the mechanism of transient overvoltage caused by the CF is analyzed; it is revealed that the reason for three times transient overvoltage is the rapid decrease of the reactive power consumed by the rectifier during the CF and the recovery period from the CF. This paper proposes a constant reactive power control (CRPC) to inhibit transient overvoltage of the sending-side AC system. The proposed CRPC can increase the reactive power consumed by the rectifier, reduce the exchange reactive power between AC and DC systems, and suppress the transient overvoltage. A simulation model in PSCAD serves to verify the proposed CRPC on the transient overvoltage suppression in the situation of different fault types, fault duration, fault severity and short circuit ratio (SCR). [ABSTRACT FROM AUTHOR]

Significant changes have occurred in the protection and grounding of generators in the past 15 years that impact generators at petroleum refineries and chemical plants. This paper updates the author's earlier paper on the subject of generator protection upgrades and highlights areas of protection that are still not addressed by some generator owners, as well as new protection areas not previously addressed. New generator protection changes are reflected in recent IEEE guides such as C37.102-2006. This paper discusses these changes as they apply to industrial generators and the risks of ignoring them. This paper outlines the risks in several functional areas where old generator electromechanical relay protection is inadequate. In addition, this paper discusses hybrid grounding of the generator stator windings, which substantially reduces stator ground fault damage—avoiding lengthy generator outages to repair. This type of grounding is a relatively new concept in generator grounding introduced in a series of IEEE Industry Applications Society (IAS) Working Group papers publicized in 2002. This grounding scheme has been installed on a number of generators but must be coupled with proper relaying and transient overvoltage protection. This paper also highlights the major new protection requirements for gas turbine starting with a load commutating inverter and protection advances made possible by the use of digital technology, which have fostered new methods not possible with older technologies. [ABSTRACT FROM AUTHOR]

Closed-form determination of fault current limiter (FCL) impedance for symmetrical faults was reported previously using a mathematically rigorous method. In this paper, extensions of the method to asymmetrical faults are presented. Single line-to-ground faults and line-to-line faults are studied. As shown in this paper, although the material corresponding to asymmetric faults use the same basic concepts described before, the different nature of asymmetrical faults and application of symmetrical components theory lead to a different formulation. Also, the graphical representation of asymmetrical faults is as contour plots instead of the circle diagrams for three-phase faults. A three-bus and the IEEE 39-bus systems are used to illustrate the virtues of the method for the proper selection of FCLs impedance. Results demonstrate that the FCL designed, as shown in this paper, works properly for asymmetrical faults. The new formulation and graphical representation for asymmetrical faults are compatible with traditional power system short-circuit analysis software. An example with both symmetrical and asymmetrical faults is presented to illustrate how a full FCL impedance design can be achieved with the method. [ABSTRACT FROM AUTHOR]

This paper defines a new type of a low-power broadside test, called a reverse low-power broadside test, whose application requires design-for-testability logic. The unique feature of a reverse low-power broadside test is that it duplicates the switching activity during the second functional capture cycle of a given low-power broadside test, except that signal-transitions are reversed. Thus, the switching activity of a reverse low-power broadside test duplicates that of a low-power broadside test in every subcircuit and on every line individually. In addition, the reversed test detects different faults, and can thus increase the fault coverage of a low-power broadside test set. This paper studies the ability of reverse low-power broadside tests to increase the transition fault coverage in benchmark circuits considering functional broadside tests as well as low-power broadside tests that are not functional. [ABSTRACT FROM AUTHOR]

This paper provides a pragmatic solution to the challenge of testing fault current interruption of high-voltage direct current (HVDC) circuit breakers (CBs). The critical parameters in the design of a test circuit capable of supplying the necessary stresses: current, energy, and voltage (both during and after interruption) are discussed. In addition, a practical implementation of a test circuit based on ac short-circuit generators operated at low power frequency, which is capable of testing the current interruption performance of the proposed technologies of HVDC CBs, is discussed. Tests validating the proposed method and circuit have been conducted on a prototype of an HVDC CB and the test results are presented. Since the performance of some technologies of HVDC CBs can depend on the magnitude of the interrupted current, four test duties are defined and demonstrated in the paper. Moreover, testing of HVDC CBs using ac short-circuit generators poses new challenges, such as the application of dielectric dc stress after current interruption and the protection of both the test-object as well as the test-circuit components when the HVDC CB fails to interrupt. Methods to overcome these challenges are developed and practically demonstrated in a test laboratory. Finally, taking into account the available resources of the author's test laboratory, the capability to test multiple series-connected modules of different technologies of HVDC CBs is verified and example cases are demonstrated. Six short-circuit generators (13 500 MVA @ 50 Hz) and up to ten step-up transformers (up to 550 kV) were actually used. [ABSTRACT FROM AUTHOR]

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

Inverter-based resources respond differently than synchronous generation sources during power system faults, challenging line protection reliability. To understand the reliability challenges, Sandia National Laboratories and North American Electric Reliability Corporation (NERC) led a collaborative study with four inverter manufacturers (mix of Type 3 Wind, Type 4 Wind, and PV Solar) and two North American protective relay manufacturers. As part of this study, an electromagnetic transients program (EMTP) with “real-code” models representing inverter firmware was used to investigate the protective relay response to faults on the modeled power system with the different inverter types. The currents and voltages obtained from the study were then played back through line relay hardware with settings typical of systems with conventional generation. The protective relays exhibited the expected reliability challenges but provided insight into the behavior of inverter-based resources during power system faults. In this paper, we share some of the challenging cases with the responses of the different line protection schemes. Using insight from the various event records, Part II of this paper shows how relay settings can be modified to obtain a substantial improvement in reliability. [ABSTRACT FROM AUTHOR]

With the rapid development of microgrid and large-scale grid-connected operation, the detection and location of short-circuit faults in microgrid has become a bottleneck. In this paper, a simulation model of short-circuit fault in low-voltage AC microgrid is built on PSCAD/EMTDC. The characteristics of current wavelet energy spectrum under various short-circuit fault states are studied and the early detection of faults is realized. Based on the relationship between the first peak value of fault current wavelet energy spectrum and the location of short-circuit points, a method for early detection and area location of short-circuit faults in microgrid is proposed. The simulation and experimental results show that this method can detect and locate the short-circuit fault area of microgrid quickly and accurately. [ABSTRACT FROM AUTHOR]

Weather-related or other types of faults can negatively impact the continuity of the electricity delivery to the consumers and, thus, lead to poorer reliability scores. 90% of customer outage-minutes are due to events which affect local distribution systems. The radial configuration is simple and has a low cost design; however, when a fault occurs it often causes power outages beyond the location of the fault itself. Therefore, it is beneficial for utilities to automatically isolate the fault and, thus, restore power to as many consumers as possible. The benefits of fault isolation and service restoration include, but are not limited to: enhanced reliability and resiliency, reduced loss of revenue to the utility, and enhanced comfort and satisfaction for the utility’s consumers. This paper provides an algorithm to quickly isolate a fault and automatically restore power to as many nodes of the distribution system as possible by opening and closing switches already placed within the system. The expert model and centralized algorithm that are proposed in this paper guarantee an optimal solution and a short run-time regardless of the size of the distribution system. A mathematical proof of the optimal nature of the solution is provided. In addition, the model is validated in practice, solving two different-sized systems. [ABSTRACT FROM AUTHOR]

This paper presents a novel methodology to estimate the saturation curve parameters of single-phase transformers, using minimum information from inrush and no-load tests. Only the value of the first current peak and the decay time are used from a unique inrush test, and only the third and fifth current harmonics from a unique no-load test. The proposed methodology is based on the existence of a signature for each transformer which can be easily obtained and characterize all possible inrush currents. This is the main contribution of the paper. Different transformers with different parameters have been tested in the laboratory. Experiments and simulations are carried out to validate the methodology. First, the respective no-load and inrush tests are made. Second, the parameters of each transformer are estimated. Third, the performance and accuracy of the proposed methodology are verified by a close agreement between the measured and the estimated saturation curves and between the simulated and the recorded inrush waveforms. Some remarkable advantages of the proposed methodology are: (a) considers the deep saturation, (b) avoids the need to know the residual flux (or to demagnetize the transformer) and the switching angle from the inrush test, and (c) it is computationally straightforward. [ABSTRACT FROM AUTHOR]

Railway turnout systems (RTS), as one of the most critical ground infrastructures of the high-speed rail, which directly impact the railway operation safety, are also susceptible to frequent faults. Hence, efficient fault prediction and intelligent maintenance decision support of RTS are significant to avoid unexpected outages and guarantee the operation safety of trains. A key challenge for fault prediction of RTS is to extract and select effective feature combinations that describe the degradation status of the system and then generate health indicators (HI) with high monotonicity, correlation, and robustness. In this paper, we focus on the jam fault caused by insufficient lubrication, which is one of the most frequent faults of RTS, and we present a novel unsupervised adaptive latent feature extraction method based on the improved sparse auto-encoder (ISAE). The locally weighted regression (LOESS) is performed to smooth the extracted latent features to overcome the influence of the noise. Improved auto-associative kernel regression (IAAKR) is utilized to fuse the feature combination and generate HI, which can intuitively describe the degradation status of RTS. Finally, the gated recurrent unit (GRU) network is introduced to enhance the correlation data process and construct the fault prediction models. The parameters of GRU are optimized by the improved particle swarm optimization (IPSO) algorithm. Extensive experiments are conducted on a real-world RTS degradation dataset collected from the Changsha Railway Station in China, which is related to the jam fault caused by the lubrication reduction, and the results show the proposed method achieves better prediction performance compared to state-of-the-art methods in terms of different evaluation metrics. [ABSTRACT FROM AUTHOR]

Conventional half bridge modular multilevel converter (MMC) system will suffer great over-current when there is a dc side fault. Therefore, topology study in sub-modules with dc side fault blocking capability have become one of the hotspots in MMC field. However, fault blocking topologies using conventional IGBT devices must employ more semiconductors than half bridge topology. The extra semiconductor devices employed in the topology will lead to the increase of cost and conduction loss. To reduce the conduction loss of the fault blocking topology, a novel sub-module topology is proposed in this paper. The proposed topology employs reverse blocking devices to form the low conduction loss path. Conduction loss analysis is conducted in this paper to show the priority of the proposed topology. Simulation and experiment results verified the dc fault blocking capability of the proposed topology. [ABSTRACT FROM AUTHOR]

DC-DC converters are needed for the future development of high voltage direct current (HVDC) grids, as they allow to interconnect lines with different voltages and topologies. The dc-dc converters can increase the grid controllability adding power flow control, voltage regulation and/or fault blocking capability. The dc modular multilevel converter (dc-MMC) is a non-isolated solution proposed to interconnect HVDC systems with the same line topology. This paper proposes a new dc-MMC with a control strategy, which allows the converter to interconnect different line topologies (e.g., rigid bipole connected to a symmetric monopole). The paper presents the different line topologies in HVDC installations. Then, a mathematical model with a variable transformation is proposed for the new dc-dc converter. A control structure is proposed and implemented in Matlab/Simulink using an average arm model and simplified dc grids. The results validate the control in normal operation, fault blocking capability and post-fault scenario (degraded mode). [ABSTRACT FROM AUTHOR]

Recent years have seen an explosion in the demand for the Internet of Things (IoT). IoT makes any physical object smart by providing sensing capability. The physical objects are embedded with sensors that form a network of sensors. However, sensors are vulnerable to faults due to energy depletion, software failures, and hardware failures. The existing fault detection schemes put huge computational overhead on the battery-limited and low computational capacity sensor nodes that are subject to the premature death of the sensor nodes. Also, they suffer from poor fault detection accuracy and huge false alarm rate that significantly reduce the overall performance of the networks. In this paper, an energy-aware intelligent fault detection scheme is proposed for IoT-enabled wireless sensor networks that significantly improve fault detection accuracy and reduce false alarm rate. A novel 3-Tier hard fault detection mechanism is used for detecting hardware unit faults of the sensor nodes. Furthermore, an optimized deep learning mechanism is used for various soft fault detection that prevents premature death of sensor nodes. The paper mathematically analyses the proposed scheme in terms of energy consumption, time complexity, and message complexity. Extensive simulations show the enhanced performance of the proposed scheme compared with the state-of-the-art algorithms in terms of fault detection accuracy, false alarm rate, false-positive rate, energy consumption, and network lifetime. [ABSTRACT FROM AUTHOR]

This special section on "Diagnosis and Prognosis for Complicated Industrial Systems?Part II? is the continuation of its previous part I (IEEE Transactions on Industrial Electronics, Vol. 63, Issue 4, 2016). The diagnosis and prognosis approaches can be roughly classified into two categories: 1) model-based and 2) data-driven approaches. The model-based approaches perform the diagnosis and prognosis relying on the physical models from first principles, whereas the data-driven approaches make full use of the process data to monitor the systems under consideration. Due to the increasing complexity of the industrial system, new challenges are encountered in diagnosis and prognosis of such complicated systems, and more efficient process monitoring approaches are needed. From this point of view, the papers included in this section are focused on the recent developments of diagnosis and prognosis for complicated industrial systems, providing novel ideas and referential directions for both the academic and industrial communities. [ABSTRACT FROM PUBLISHER]

This two-part paper proposes a revised method for calculating high voltage (HV) cable sheath currents, and for fault location of cross-bonded HV cable systems. The equivalent circuit and the cable impedance per unit length under short-circuit fault conditions are revised from those under non-fault conditions. Part 1 of this paper proposes a revised phasor domain mathematical model for the sheath current calculation under fault conditions, following demonstration that short-circuit faults can cause changes in the equivalent circuit of the cable metal sheath, and cause changes in the cable impedance per unit length. The calculation results, as given in a case study, show that there exists a unique relation between the fault position and the sheath fault currents, making it possible to locate a fault by analyzing the characteristics of the sheath currents during a fault. Part 2 of the paper focuses on the fault location method via sheath current monitoring. [ABSTRACT FROM AUTHOR]

DC microgrid has attracted more and more attention due to its unique characteristics, but the development of a dc microgrid is also facing some challenges, such as interruption and isolation of short-circuit fault currents. Therefore, the dc circuit breaker plays an important role in ensuring the normal work of a dc microgrid. In this paper, a novel bidirectional dc solid-state circuit breaker is proposed to realize the bidirectional flow of energy, which ensures the higher operating efficiency of the dc microgrid. Compared with other solid-state circuit breakers, the proposed novel topology has simpler structure, common ground, and fewer components. First, this paper makes a detailed analysis of the different working stages of the circuit when the fault occurs in combination with simulation results of the circuit topology. Then, the standard of selecting the components through the calculation and analysis of the circuit is given in this paper. Finally, the performance of the novel bidirectional solid-state circuit breaker is verified by experiments. [ABSTRACT FROM AUTHOR]

The development of the dc microgrid system on-board has promoted the development of the dc circuit breaker, but short circuit fault may cause serious damage to the system. Many problems exist in the traditional dc circuit breaker such as long periods of fault interruption, complex circuit structure, existing arc, low reliability, and low anti-interference. Aiming to solve these problems, a novel solid-state dc circuit breaker is proposed in this paper. First, this paper analyzes the working principle and process of the circuit in detail according to the results of the simulation based on Saber. Second, this paper gives the criteria on how to choose the parameters of the components correctly in the circuit. The concept of the maximum fault resistance according to the minimum fault current is also introduced. Moreover, this paper analyzes the influence of the minimum fault ramp rate on the circuit performance. Finally, experimental results verify that the performance of this novel solid-state circuit breaker agree with the theoretical analysis. [ABSTRACT FROM AUTHOR]

Formal techniques for the functional verification of System-on-Chip (SoC) hardware have matured significantly over the last years. They can penetrate deeply into a design to exhibit complex functional dependencies between various design components in terms of detailed logical and temporal relationships. They can also provide a well-defined formal relationship between an abstract system model of a design and its concrete implementation at the register-transfer level (RTL). This paper shows how such knowledge available from formal verification can be “condensed” into a database that stores all registers and flip-flops, at which time points they are actually relevant for the correct behavior of the design and when they are not. We show that the comprehensive information on temporary unobservabilities in the design can be of great value to reach two nonfunctional design goals that play a dominant role in many design flows: safety and low power consumption. This paper presents techniques to assess the effects of soft errors by single-event upsets (SEUs) with formal precision and to relate the results of the proposed analysis to an abstract system model. For example, our analysis can determine which soft errors may lead to a system “crash” and which are guaranteed not to cause any harm. For the application of the proposed approach in power optimization, this paper presents techniques for clock gating and power gating. For the examined designs, we observe a reduction of power consumption between 10% and 50% on top of the state-of-the-art commercial power synthesis. [ABSTRACT FROM AUTHOR]

This paper deals with the test of a reconfigurable hardware system (RHS). The latter is a hardware device that allows to change the hardware resources at runtime in order to modify the system functions and therefore to dynamically adapt the system to its environment. The increasing functional complexity of embedded systems and the transition to the RHS make the hardware testing a challenging task, especially under the confine of providing a high quality with a low cost. Considering the fact that the hardware test represents a key cost factor in a production process, an optimal test strategy can be advantageous in the competitive industrial market. Accordingly, this paper introduces a new methodology for an efficient hardware test of RHS. For an RHS, the number of stuck-at faults can be very large, which leads to a significant slowdown in the testing process. Because of the redundancy of faults between the different circuits composing an RHS, the proposed methodology aims at minimizing the number of faults using the inter-circuits relationships and consequently at providing an optimal fault set that can be effectively used for testing. Efficient techniques for test generation and test set validation are proposed to provide the test patterns for faults reduced by inter-circuits fault collapsing. The application of the generated test patterns is typically sufficient to provide an overall fault coverage. The proposed methodology is implemented in a new visual environment named TnTest. An experimental study confirms and validates the expected findings. Note to Practitioners—This paper addresses possible challenges for future generations of adaptive embedded systems. It proposes an original methodology for an efficient reconfigurable hardware system (RHS) hardware test. The main objective is to significantly reduce time and cost needed for the testing process. For an RHS, the number of stuck-at faults can be very large, which can cause a major slowdown in the hardware test. Based on the inter-circuits relations existing between the different circuits composing an RHS, the proposed methodology decreases considerably not only the number of the faults but also the test patterns needed for testing. The application of the generated test patterns is typically sufficient to provide an overall fault coverage. The proposed methodology is implemented in a new visual software environment named TnTest, which is capable of providing the smallest fault set as well as the efficient test set that can be effectively used for testing. This environment can be applied to test any embedded device that can be deployed in any new application based on flexible technologies. It can also be useful in manufacturing industries for a required improvement of the production process in relation to time and cost. [ABSTRACT FROM AUTHOR]

In this paper, rotor inter-turn faults in salient-pole synchronous machines are investigated using finite-element analysis. The machine under study is a 22 MVA eight-pole hydropower generator with fractional-slot windings. Simulated faulty cases include 1, 2, 5, 10, and 20 short-circuited turns (out of 58 turns) in one rotor pole. In the electromagnetic analysis, the effect of faults on airgap flux density and radial forces is studied. Furthermore, this paper investigates online detection of inter-turn faults using spectral analysis of stator voltage or current is studied. The amplitude of fault-related harmonics is investigated at various fault severities, as well as at no-load and full-load operations. This paper also discusses the effects of damper bars, an influence of parallel circuits in the stator windings, and influence of the pole pair number. In addition, a comparison between fault-related harmonics in the case of dynamic eccentricity and rotor inter-turn faults is presented. [ABSTRACT FROM AUTHOR]

This paper defines a new type of multicycle tests called autonomous multicycle tests. Similar to multicycle scan-based tests, autonomous multicycle tests include several consecutive functional capture cycles to enhance defect detection and achieve test compaction. Unlike multicycle scan-based tests, an autonomous multicycle test set uses the same initial state for all the tests. During the functional capture cycles of a test, the primary inputs are driven by primary outputs, and the circuit operates autonomously. A test uses a scan-in operation only for the initial primary input vector, and to determine the connection between the primary inputs and outputs. It uses a scan-out operation only for the final primary output vector. This results in reduced overheads related to storage requirements and test application time compared with scan-based tests, and several unique properties that are discussed in this paper. This paper describes a test generation procedure for autonomous multicycle tests that avoids sequential test generation, and presents experimental results to demonstrate the ability of the tests to detect target faults. [ABSTRACT FROM AUTHOR]

Protection of microgrids at the Point of Interconnection (POI) is a challenging task. Particularly, single-line-to-ground (SLG) faults on interconnection lines are difficult to detect using the fault current detection relays if the microgrid is ungrounded at utility side of its interconnection transformer; such microgrid contributes very low fault current, which disappears once the utility feeder breaker opens. Other common schemes for protection of microgrid interconnection line against SLG faults include Direct Transfer Trip (DTT) and over-voltage relay (59G). The main challenges associated with these methods are installation and maintenance costs of high-speed communication system, sensitivity of relay settings, and delayed fault clearing time due to selectivity requirements. To address such concerns, this paper proposes the use of a distance relay at the microgrid/LV side of the interconnection transformer to provide protection against SLG faults on the interconnection line at the utility/HV side. The designed distance relay executes an enhanced apparent impedance calculation using residual voltage compensation to correctly detect the fault, properly measure the fault location, and timely isolate the fault. In this paper, various scenarios are analyzed using ASPEN and PSCAD simulation tools to demonstrate the effectiveness of the proposed method for protecting the microgrid interconnection line under different fault scenarios. [ABSTRACT FROM AUTHOR]

Aiming at the fault traveling wave on the LCC-MMC HVDC transmission line, this paper analyzed its reflection and refraction characteristics at the DC buses and the fault point, plotted its propagation grid diagrams, obtained the relationship between the polarity of fault traveling wave and the boundary elements, and drew the conclusion that when the impedance of DC filter is far less than the wave impedance of transmission line, the existing fault location methods that need to distinguish these two waves according to their polarities are not applicable to the LCC-MMC HVDC system. On these bases, this paper proposed a modal traveling wave arrival time difference-based location principle for pole-to-ground fault, and a fault traveling wave propagation path ratio-based location principle for pole-to-pole fault, these principles neither need to identify the wave polarity, nor need the wave velocity value. In order to better extract the wave heads and their arrival time, this paper pre-treated the sampling data to make sure all the wave heads are extracted from the same frequency band, then the wave heads and their arrival time can be extracted with the empirical mode decomposition. The simulation results verified the effectiveness of the proposed fault location principle. [ABSTRACT FROM AUTHOR]

This paper presents an optimization framework for sequential reconfiguration using an assortment of switching devices and repair process in distribution system restoration. Compared to existing studies, this paper considers types, capabilities and operational limits of different switching devices, making it applicable in practice. We develop a novel multi-phase method to find the optimal sequential operation of various switching devices and repair faulted areas. We consider circuit breakers, reclosers, sectionalizers, load breaker switches, and fuses. The switching operation problem is decomposed into two mixed-integer linear programming (MILP) subproblems. The first subproblem determines the optimal network topology and estimates the number of steps to reach that topology, while the second subproblem generates a sequence of switching operations to coordinate the switches. For repairing the faults, we design an MILP model that dispatches repair crews to clear faults and replace melted fuses. After clearing a fault, we update the topology of the network by generating a new sequence of switching operations, and the process continues until all faults are cleared. To improve the computational efficiency, a network reduction algorithm is developed to group line sections, such that only switchable sections are present in the reduced network. The proposed method is validated on the IEEE 123-bus and 8500-bus systems. [ABSTRACT FROM AUTHOR]

The short-circuit response of inverter-interfaced distributed generators (IIDGs) is not adequately represented in many conventional protection studies. This paper presents an in-depth analysis of IIDG behavior during grid faults and proposes a more accurate reduced-order parameterized short-circuit current (RPSC) model of inverters. Typical inverter components are thoroughly investigated to identify those that play dominant roles during faults. The paper shows that the current limiter is the dominant factor for the steady-state fault-current of inverter; while the inverter filter along with the severity of the voltage disturbance largely determine the initial transient spike of inverter fault current. The proposed model is low-order and can be used in large scale simulations. The parameters of the proposed RPSC model can be extracted from laboratory experiments without requiring proprietary manufacturer information. The proposed fault-current model is analogous to the well-known synchronous machine model that segregates the inverter fault current into subtransient, transient, and steady-state fault currents. Experimental and simulation tests are presented to validate the model. [ABSTRACT FROM AUTHOR]

HVDC grid protection with adequate speed and reliability is required to minimise the impact of DC faults. In particular, fast breaker failure backup protection algorithms are needed to meet the expected reliability requirements of HVDC grids. In this paper, existing breaker failure backup protection algorithms are shown inadequate to detect partial failures like a single module failure of breakers with a modular structure. This paper proposes a backup protection algorithm which rapidly detects a DC breaker failure based on estimating the counter-voltage created by the energy absorption branch during an interruption. The performance of the proposed algorithm is evaluated using a four-terminal test network with both hybrid and mechanical DC breaker technologies. The simulation results show that the proposed algorithm is able to quickly detect both complete and partial failures of the two breaker technologies even considering measurement errors, noise and ageing of the energy absorption components. [ABSTRACT FROM AUTHOR]

The inrush current generated by power transformer energization (TE) causes voltage sag of the nearby bus, the typical residual voltage of the voltage sag caused by transformer energization (VSTE) is about 0.7 p.u.--0.9 p.u. and lasts for a longer duration, which may lead to the sensitive equipment trips. This paper proposes an estimation method of voltage sag frequency considering VSTE. Firstly, based on the maximum entropy method, the residual flux distribution is calculated by considering the relationship between the residual flux and closing angle at the moment of TE. The voltage sag waveform caused by TE is calculated based on the estimation of the probability distribution of residual flux, to evaluate VSTE objectively and comprehensively. Secondly, this paper proposes a non-rectangular voltage sag equivalent frequency statistical method based on multiple magnitude-duration (MMD) function, to avoid the overestimation of voltage sag frequency by the traditional methods. Furthermore, this paper proposes an assessment algorithm of voltage sag frequency. Finally, the simulation of IEEE-30 test system verifies the necessity and correctness of the proposed method. [ABSTRACT FROM AUTHOR]

The objective of this two-part paper is to provide clarity to physical concepts used in the field of transformer modeling, to dispel common misconceptions regarding numerical instabilities, and to present unified modeling techniques for low-frequency transients. This paper focuses on proper modeling of nonlinearities (magnetizing branches) since these components are critical to determine the low-frequency behavior. A good low-frequency model should properly represent: normal operation, inrush currents, open and short circuit, out-of-phase synchronization transient of step-up transformers, geomagnetic-induced currents, ferroresonance, and harmonics. This paper discusses the derivation of electrical dual models from the equivalent (magnetic) reluctance networks and the direct application of the principle of duality. It is shown that different dual models need to be derived for different transformer geometries and the advantages and disadvantages of each method are discussed. This paper also compares double-sided versus single-sided dual models, and shows that the double-sided model is a more general approach. The mathematical equivalency of several leakage models (negative inductance, mutual coupling, and BCTRAN) is demonstrated for three-winding transformers. It is also shown that contrary to common belief, a negative inductance is not the source of numerical oscillations, but they occur due to the use of noncorrect topological models for representing the core. [ABSTRACT FROM PUBLISHER]

This paper provides a follow-up to the paper The Effects of System Grounding, Bus Insulation and Probability on Arc Flash Hazard Reduction—The Missing Links. In that paper, system grounding and bus insulation were considered a means of reducing the probability of an arc flash incident by approximately two orders of magnitude. In September 2013, additional testing was conducted on a low-voltage motor control center (LVMCC) with the expectation that engineering enhancements such as insulated vertical bus, high resistance grounding, and other techniques could be implemented to further reduce the probability of an arc flash incident. The testing performed was with faults initiated in locations typically found in operating petrochemical facilities, in LVMCCs, with the starter unit door open. This paper discusses the findings of testing on real-world electrical equipment in an effort to further understand and minimize the probability of an arc flash incident. This paper reviews the physics of the arcing fault and how ignition wire, geometry, and the number of anode/cathode pairs all contribute to arcing fault energy and personnel exposure. [ABSTRACT FROM PUBLISHER]

An introduction is presented in which the editor discusses various reports within the issue on industrial electronics topics including induction machines, synchronous machines, and power components and power converters.