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In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts. [ABSTRACT FROM AUTHOR]

We investigate the channel material dependence of wave function deformation scattering (WDS), a phenomenon that occurs when the shape of the carrier wave function is forced to change as the channel is traversed. Line-edge roughness (LER) is one nonideality that can induce WDS in confined device geometries. We perform nonequilibrium Green's function simulations of ensembles of ultrascaled Fin Field Effect Transistors that exhibit correlated LER to determine the resulting on-current distributions. By considering various channel materials, we demonstrate two trends. First, WDS has a greater impact when the transport effective mass of the channel material is low, due to stronger coupling between conducting subbands. Second, WDS has a greater impact when the confinement effective mass of the channel material is high, due to the presence of more conducting subbands, which further enhances coupling. [ABSTRACT FROM AUTHOR]

An analytical model of parasitic capacitancein inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness (Tiox) and inserted-oxide recess (Trec), is shown using the proposed model and TCAD simulations. [ABSTRACT FROM AUTHOR]

We examine the impact of line-edge roughness (LER) on the variability in the on-current and saturation threshold voltage of ultrascaled FinFET devices via quantum-mechanical transport simulation. We obtain a realistic model of LER by decomposing the LER into short- $\lambda $ and long- $\lambda $ fluctuations, and we consider their separate influences on device performance. We show that the long- $\lambda $ fluctuations lead to greater device variability than the short- $\lambda $ fluctuations, and we explain the difference between the two cases via the influence of fluctuating quantum confinement arising from the LER. Finally, we consider devices in which the long- $\lambda $ fluctuations of the two fin edges are correlated and demonstrate that this correlation significantly improves the variability. Thus, we show the continued need for fabrication technology either to reduce the amplitude of the long- $\lambda $ fluctuations or to ensure the long- $\lambda $ fluctuations between the sidewalls of ultrascaled FinFET devices are correlated. [ABSTRACT FROM AUTHOR]

This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential for advanced circuit designs. The results show that VeSFET can provide high I {\mathrm {eff}} to I {\mathrm {off}} ratio, low gate capacitance, high \Delta V {t}/ V { {\textit{g2s}}} , and competitive drive capability with respect to a reference FinFET of comparable dimensions. [ABSTRACT FROM PUBLISHER]

The introduction of FinFET architecture was expected to alleviate the issue of mismatch compared with planar technology, given the lower doping levels required. However, several authors have reported better mismatch results for planar technology suggesting additional challenges for FinFET architecture. An additional mechanism previously not considered arising from charge present at points of disturbance in the silicon lattice in tapering and wavering fins is shown to contribute to transistor mismatch. We show that including this mechanism improves the quantitative understanding of mismatch in FinFETs. [ABSTRACT FROM AUTHOR]