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Digital Signage can be quickly updated, greatly enhancing functionality compared to traditional paper signs. Worries about climate change, carbon footprint, energy shortages and light pollution means Signage should be low power with low light pollution. In response, E Ink has developed Kaleido reflective ePaper outdoor displays with good color performance. On a spectrum between paper signs and other forms of full color electronic display Kaleido is much closer to paper signs in power use and lighting impact. Operating temperature range is ‐15°C to 65°C, removing the need for expensive, power hungry heating and cooling. [ABSTRACT FROM AUTHOR]

There has been much interest in replacing traditional information supports with more technological solutions in recent years. New technologies which allow paper-like perception with minimal power needs have emerged as low-power wireless scenarios. A priority for these new supports is to create the architecture for a scalable solution which maintains minimal power requirements. The retail industry demands a new information infrastructure that improves customer and employee satisfaction. In this work, authors propose an information provision architecture based on E-Paper and carry out an experiment where different smart labeling architectures based on Paper, E-Paper, LED liquid crystal display (LCD) and Dot-matrix LCD were tested in order to determine which is best suited for a real labeling environment. Enclosed in a research project called SMARKET, the authors pilot-tested the work in a real supermarket, having the opportunity to survey employees and customers about satisfaction and frustration with the use of the architectures proposed in this research work. [ABSTRACT FROM AUTHOR]

This paper presents a shock detection device for packages in the supply chain. The primary purpose is to identify package damage during storage, delivery, and handling. Additionally, products are likely to be damaged if dropped from a certain height, which sometimes does not appear on the package. By continuously measuring package vibrations and detecting shocks in the supply chain, consumers can gain an insight into the state of the product upon delivery. This paper presents the Smart Sticker implementation for ultra-low-power shock detection in the supply chain. The overall energy consumption must be kept as low as possible while continuously sensing the presence of shock to ensure that the Smart Sticker's battery lasts as long as possible. The Smart Sticker functions in three modes to meet the established constraints: low-power, active, and data transfer mode. While detecting the shock, the low-power mode uses the least amount of energy needed. If the shock exceeds the threshold, the Smart Sticker enters active mode, stores the detected g force value in memory, and then switches back to low-power mode. Finally, employing Near Field Communication (NFC) and energy harvesting, the data transfer mode allows the consumer to read the recorded data. The results show that the Smart Sticker for shock detection performs according to set requirements and successfully monitors and detects shock for packages in the supply chain. [ABSTRACT FROM AUTHOR]

High‐transmission, high contrast ratio and low‐power‐consumption amplified intrinsic fringe field (AIFF) multi‐domain vertical alignment (MVA) LCD's are developed for microdisplay for augmented reality, portable smart phones, GPS, tablet, and LC TV display applications. The AIFF MVA design eliminates all protrusions and ITO slits in TFT and CF.substrates, resulting in high transmission and high yield. The no‐pretilt fabrication process is low cost, does not require PI rubbing and special photoalignment process, and uses standard IC, LC, and PI materials. AIFF MVA is the only LCD mode without edge disclinations. It is compatible with the RGBW square pixel designs for low power consumption LCD applications. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for a 1-bit full adder is proposed based on dynamic logic methodology, which utilises pass transistors. The clocking operation falls into two phases. The clocking operation consists of a pre-discharged cycle, during which pseudo capacitors are reset to zero when the clock signal is high, and an evaluation cycle, during which the circuit outputs the adder function when the clock signal is low. The circuit uses a combination of 12 pass-transistors to better implement the full adder logic function with the maximum of a NMOS threshold voltage drop. Moreover, the circuit has no direct connection to the power-supply node and so this can possibly save the power dissipation. Our new adder outperforms other 1-bit full adder structures in terms of power-delay factor, according to simulation results. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) and blockchain are emerging technologies that have attracted attention in many industries, including healthcare, automotive, and supply chain. IoT networks and devices are typically low-powered and susceptible to cyber intrusions. However, blockchains hold considerable potential for securing low-power IoT networks. Blockchain networks provide security features such as encryption, decentralisation, time stamps, and ledger functions. The integration of blockchain and IoT technologies may address many of the security concerns. However, integrating blockchain with IoT raises several issues, including the security vulnerabilities and anomalies of blockchain-based IoT networks. In this paper, we report on our experiments using our blockchain test bed to demonstrate that blockchains on IoT platforms are vulnerable to DDoS attacks, which can also potentially lead to device hardware failures. We show that a number of anomalies are visible during either a DDoS attack or IoT device failure. In particular, the temperature of IoT hardware devices can exceed 90 °C during a DDoS attack, which could lead to hardware failure and potential fire hazards. We also found that the Block Transaction Rate (BTR) and network block loss percentage can increase due to corrupted hardware, with the BTR dropping to nearly zero blocks/sec and a block loss percentage of over 50 percent for all evaluated blockchains, and as high as 81.3 percent in one case. Our experiments demonstrate that anomalous temperature, latency, bandwidth, BTR, and network block loss percentage can potentially be used to identify DDoS attacks. [ABSTRACT FROM AUTHOR]

Edge computing enables prompt responses in IoT environments, such as the operation of autonomous vehicles and unmanned aerial vehicles. However, with the increase in sensor nodes, the computational burden on the computing node also increases. Specifically, data filtering and reduction at application nodes add to the energy burden for battery-operated devices. In this paper, we propose a preprocessing system at the application node that requires low power consumption for data transmission reduction. Based on our simulations, we identify the minimum data size needed to preserve the signal. We first design the preprocessing system using a hardware description language to evaluate its performance. Then, we implement the open-library-based MCU system, including the proposed preprocessing IP, to assess its operation and overhead. Our implementation of the preprocessing system reduces data transmission by 50% with acceptable information loss. Additionally, the area and power consumption after the logic synthesis of the preprocessing IP within the entire MCU system are evaluated at only 3.6% and 13.1%, respectively. By performing preprocessing using the MCU and proposed IP, nearly 74.4% power reduction is achieved compared to using the existing MCU core. [ABSTRACT FROM AUTHOR]

Brain-inspired flexible neuromorphic devices are of great significance for next-generation high-efficiency wearable sensing and computing systems. In this paper, we propose a flexible organic electrochemical transistor using poly[(bithiophene)-alternate-(2,5-di(2-octyldodecyl)- 3,6-di(thienyl)-pyrrolyl pyrrolidone)] (DPPT-TT) as the organic semiconductor and poly(methyl methacrylate) (PMMA)/LiClO4 solid-state electrolyte as the gate dielectric layer. Under gate voltage modulation, an electric double layer (EDL) forms between the dielectric layer and the channel, allowing the device to operate at low voltages. Furthermore, by leveraging the double layer effect and electrochemical doping within the device, we successfully mimic various synaptic behaviors, including excitatory post-synaptic currents (EPSC), paired-pulse facilitation (PPF), high-pass filtering characteristics, transitions from short-term plasticity (STP) to long-term plasticity (LTP), and demonstrate its image recognition and storage capabilities in a 3 × 3 array. Importantly, the device's electrical performance remains stable even after bending, achieving ultra-low-power consumption of 2.08 fJ per synaptic event at −0.001 V. This research may contribute to the development of ultra-low-power neuromorphic computing, biomimetic robotics, and artificial intelligence. [ABSTRACT FROM AUTHOR]

Bluetooth Low Energy Mesh (BLE Mesh) enables Bluetooth flexibility and coverage by introducing Low-Power Nodes (LPNs) and enhanced networking protocol. It is also a commonly used communication method in sensor networks. In BLE Mesh, LPNs are periodically woken to exchange messages in a stop-and-wait way, where the tradeoff between energy and efficiency is a hard problem. Related works have reduced the energy consumption of LPNs mainly in the direction of changing the bearer layer, improving time synchronization and broadcast channel utilization. These algorithms improve communication efficiency; however, they cause energy loss, especially for the LPNs. In this paper, we propose a constrained flooding algorithm based on time series prediction and lightweight GBN (Go-Back-N). On the one hand, the wake-up cycle of the LPNs is determined by the time series prediction of the surrounding load. On the other, LPNs exchange messages through lightweight GBN, which improves the window and ACK mechanisms. Simulation results validate the effectiveness of the Time series Prediction and LlightWeight GBN (TP-LW) algorithm in energy consumption and throughput. Compared with the original algorithm of BLE Mesh, when fewer packets are transmitted, the throughput is increased by 214.71%, and the energy consumption is reduced by 65.14%. [ABSTRACT FROM AUTHOR]

Although CNN shows high performance in the image recognition field, it has great disadvantages. They are to take a long time to perform machine learning due to a lack of system resources, and to consume a lot of power due to the great volume of computation. A convolution layer is a key element of convolutional neural network processing. This paper presents a convolution layer hardware using processing elements with a low-power multiplier. The low-power multiplier reduces the switching activity by increasing the exchange rate between the multiplier and multiplicand. The proposed convolution layer hardware was implemented on the Intel DE1-SoC FPGA Board using Verilog-HDL. The performance was verified by comparing the exchange rate with the existing multipliers when performing multiplications to process convolutional operations for the MNIST image database. [ABSTRACT FROM AUTHOR]

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Modern processors often face challenges when handling instructions that overwhelm the branch target buffer (BTB), leading to front-end bottlenecks. As the BTB's capacity increases, its prediction module can become slower and power-hungry. In this paper, we introduce a straightforward yet highly effective two-level prediction mechanism to mitigate the escalating power consumption in the BTB structure, achieved by reducing the number of accesses. Our approach incorporates two main elements: M-BTB and V-BTB. M-BTB encompasses the first-level prediction mechanism and a fully associative BTB, while V-BTB houses the second-level prediction mechanism and a set-associative BTB. To implement our prediction mechanism, we optimize the traditional two-level BTB structure. The first level employs the skew mechanism, and the second level dissects the tag bits to create the Partial tag. These two levels of prediction mechanism correspond to the bank/way prediction for the two-level BTB structure. Our experimental results show that the first-stage prediction mechanism reduces M-BTB accesses by 75%, while the second-stage prediction mechanism ensures that over 98% of addresses require just zero or one way of the V-BTB to achieve a hit result. Our proposed approach achieves a remarkable 86–97% reduction in power consumption, with a minimal impact on performance and an increase in overall area efficiency. [ABSTRACT FROM AUTHOR]

The constant growth of social media, unconventional web technologies, mobile applications, and Internet of Things (IoT) devices create challenges for cloud data systems in order to support huge datasets and very high request rates. NoSQL databases, such as Cassandra and HBase, and relational SQL databases with replication, such as Citus/PostgreSQL, have been used to increase horizontal scalability and high availability of data store systems. In this paper, we evaluated three distributed databases on a low-power low-cost cluster of commodity Single-Board Computers (SBC): relational Citus/PostgreSQL and NoSQL databases Cassandra and HBase. The cluster has 15 Raspberry Pi 3 nodes with Docker Swarm orchestration tool for service deployment and ingress load balancing over SBCs. We believe that a low-cost SBC cluster can support cloud serving goals such as scale-out, elasticity, and high availability. Experimental results clearly demonstrated that there is a trade-off between performance and replication, which provides availability and partition tolerance. Besides, both properties are essential in the context of distributed systems with low-power boards. Cassandra attained better results with its consistency levels specified by the client. Both Citus and HBase enable consistency but it penalizes performance as the number of replicas increases. [ABSTRACT FROM AUTHOR]

Digital Image Processing has dominated Digital Signal Processing at the cost of more memory, resources, and high computational power. In image processing, filtering transformations and other operations need complex multiplications, and the multiplier is one of the most resources consuming elements. Recently, mitigating the multiplier complexity in the digital signal processing (DSP) algorithms sigma-delta modulation based general purpose and adaptive DSP algorithms are developed in MATLAB and compared with its counterpart multibit algorithms for functionality and area-performance-power in FPGA. The contemporary multiplier algorithms are also optimized to overcome the multiplier complexity challenge as computation becomes simple and fast. This paper extends the reported work by investigating the sigma-delta modulation approaches for developing a computationally efficient low-power image processing algorithm. The proposed model is designed, developed, and simulated in MATLAB. The simulation results are analyzed using SNR, MSE, and Peak SNR. The simulation results show that the proposed system can better mitigate the noise effect, making it robust for noisy environment. [ABSTRACT FROM AUTHOR]

This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design based on the leakage reduction mechanism. A multi-threshold logic is employed for reducing the leakage current during read/write operations. Here, the multi-threshold technique is used to insert the high threshold sleep control to the low threshold circuit. The insertion is performed in a serial manner. The high threshold transistors are very useful for deriving the low sub-threshold current. Meanwhile, the low threshold transistors are promising for improving the circuit performance. The high-low threshold transistor pairs are used to change the channel length by modifying the oxide thickness of the transistors. The overall implementation of the Multi-threshold-based SRAM cells are implemented with the help of CNFET in-order to avoid the short channel effect, mobility degradation which is occurred while considering the channel length below 32 nm in CMOS (Complementary Metal Oxide Semiconductor) devices. The paper clearly represents the performance improvement of the proposed SRAM cells with above-mentioned technologies. [ABSTRACT FROM AUTHOR]

This paper presents a class of zero-power microwave sensor architecture based on the direct-conversion principle to eliminate data processing at the Internet of Things sensors and provide unpowered nodes. A base station (BS) transmits a single tone signal at the frequency of $f_{0}$ /2 toward the sensing node using an antenna. At the node, an antenna receives the signal, and a passive frequency doubler makes the frequency twice. Then, a multi-port structure directly modulates the sensing data at the frequency of $f_{0}$ and sent back to the BS by an antenna. The multi-port circuit has one input, one output, and some loading ports. In this paper, a six-port modulator and four similar sensitive capacitive resonators are used. A pair of resonators senses the variation of a sample under test (SUT) while the other pair is covered by a reference or known material. At the BS, any quadrature receiver can be used to demodulate sensing data. Here, a similar six-port structure is used to extract data and find the SUT variations. An example one-node system is implemented at $f_{0} = 2.45$ GHz and evaluated by some standard SUTs. To support multiple nodes, a smart directional antenna is necessary at the BS, which also improves the overall efficiency of the system. [ABSTRACT FROM AUTHOR]

The survival rate for sudden cardiac arrest (SCA) is low, and patients with long-term risks of SCA are not adequately alerted. Understanding SCA's characteristics will be key to developing preventive strategies. Many lives could be saved if SCA's early onset could be detected or predicted. Monitoring heart signals continuously is essential for diagnosing sporadic cardiac dysfunction. An electrocardiogram (ECG) can be used to continuously monitor heart function without having to go to the hospital. A zeolite-based dry electrode can provide safe on-skin ECG acquisition while the subject is out-of-hospital and facilitate long-term monitoring. To the ECG signal, a low-power 1 μW read-out circuit was designed and implemented in our prior work. However, having long-term ECG monitoring outside the hospital, i.e., high battery life, and low power consumption while transmission and reception of ECG signal are crucial. This paper proposes a prototype with a 10-bit resolution ADC and nRF24L01 transceivers placed 5 m apart. The system uses the 2.4 GHz worldwide ISM frequency band with GFSK modulation to wirelessly transmit digitized ECG bits at 250 kbps data rate to a physician's computer (or similar) for continuous monitoring of ECG signals; the power consumption is only 11.2 mW and 4.62 mW during transmission and reception, respectively, with a low bit error rate of ≤0.1%. Additionally, a subject-wise cross-validated, three-fold, optimized convolutional neural network (CNN) model using the Physionet-SCA dataset was implemented on NVIDIA Jetson to identify the irregular heartbeats yielding an accuracy of 89% with a run time of 5.31 s. Normal beat classification has an F1 score of 0.94 and a ROC score of 0.886. Thus, this paper integrates the ECG acquisition and processing unit with low-power wireless transmission and CNN model to detect irregular heartbeats. [ABSTRACT FROM AUTHOR]

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power. [ABSTRACT FROM AUTHOR]

An artificial intelligence of things (AIoT) chip is a critical hardware component in edge devices that supports data acquisition and processing in the artificial intelligence (AI) era. In this paper, we introduce the architecture and circuit techniques for AIoT systems as well as the design challenges associated with them. To address the design challenges, we describe our design approaches to improve energy efficiency from the standpoints of system architecture, AI computing, and data acquisition circuits. Meanwhile, we present our most recent research progress and state-of-the-art AIoT chip demonstrations at a prestigious conference. Our design techniques improve power and energy efficiency by orders of magnitude on corresponding state of the arts (SOTA), allowing for an advanced AIoT chip design. [ABSTRACT FROM AUTHOR]

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 µm complementary metal-oxide-semiconductor (CMOS) process. [ABSTRACT FROM AUTHOR]

This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a 3 × 3 kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the 3 × 3 kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., G H and G V , respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient (G) of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing G H and G V cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window. [ABSTRACT FROM AUTHOR]

Currently, static circuit power is becoming a major concern, dominating the total power consumption due to the scaling down of CMOS technology. The smaller sizes drastically affect the leakage current, which integrated circuit designers attempt to overcome this issue. Hence, several methods and technologies have been proposed to prevail this phenomenon. One of these methods is using memory structures in logic designs. A Hybrid MTJ/CMOS circuit is one of these promising techniques to design low-power nonvolatile circuits with power gating ability and low overhead for reconfigurable possibilities. In this paper, we have proposed a fully nonvolatile, low-power Full-Adder based on MTJs that uses the spin transfer torque method assisted by the spin hall effect. Simulation results of these designs by HSPICE show that they can work fast with low-power consumption compared to other state-of-the-art nonvolatile full-adders. [ABSTRACT FROM AUTHOR]

Wireless Body Area Network (WBAN) is a wireless network of short-range communication protocols for remote healthcare monitoring with the possibility of giving freedom of human body movements. Sensor nodes (motes) are usually located under the skin, implanted deep in the body, or ingested, as in the rare case of smart pills for medical and non-medical usage. Since the necessary connections of wearable and implantable devices are wireless, and the components use low batteries, processing and transferring the critical data can deplete the nodes' power. In most cases, it is impossible to exchange or re-power batteries. Holter monitoring, loop recorders, and wireless capsule endoscopy are some of the WBAN's applications for saving and transferring medical data. Wireless capsule endoscopy is the application for image transmission in WBANs, and the image compression in common is a specific segment of capsule endoscopy. Since the better compression of images increases the frame rate and typically improves the diagnosis process, selecting the compression algorithm should be relevant. The considerable scope of this comprehensive study pays attention to the various biomedical data compression approaches in WBANs. This paper focuses on power-efficient schemes of remote healthcare networks. In this survey article, the energy-based biomedical data compression approaches of WBANs and remote healthcare networks are accurately classified based on lossy, lossless, and hybrid techniques; later, a comprehensive comparison of each specific method's power consumption is presented. [ABSTRACT FROM AUTHOR]

With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (−28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of −76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7. [ABSTRACT FROM AUTHOR]

This paper presents radiation hardened SRAM (namely LPDNUR and HSDNUR), both of which can self-recover from single-node and double-node upsets. LPDNUR uses a two-input C-element structure, which reduces the average power consumption because the stacked effect. Moreover, in order to reduce read access time (RAT) and write access time (WAT), the paper proposes HSDNUR, which uses a combination of NMOS and PMOS as the transistor for one-node data transmission, an approach that increases the current drive capability and reduces transmission delays. Compared to the state-of-the-art radiation-hardened SRAM design, such as QUCCE10T, QUCCE12T, We-Quatro, etc. The model results show that the average power consumption of LPDNUR is reduced by 24.59% on average, and the RAT and WAT of HSDNUR are reduced by an average of 35.71% and 24.14% respectively. • LPDNUR and HSDNUR fully achieve SNU and DNU recovery. • Average power of LPDNUR is 24.59% lower on average than other SRAM hardened since stack structure. • WAT and RAT of HSDNUR are 24.14% and 35.71% lower than other SRAM hardened on average by using TG. [ABSTRACT FROM AUTHOR]

This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T) SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based cross-coupled inverters comprise the storage cell of the proposed MST11T bit cell. In comparison with conventional inverters, ST-based inverters have sharp voltage transfer characteristics. As a result, the proposed bit cell's stability performance increases. The proposed SRAM cell's leakage power consumption is reduced because of the use of stacked N-type transistors. For the read operation of the proposed bit cell, the read decoupled technique is used. As a result, the read static noise margin (RSNM) has greatly improved. The proposed bit cell's write static noise margin (WSNM) is increased by adopting feedback-cutting methodology. The performance of the proposed bit cell is compared with that of conventional 6 T, conventional 8 T, Schmitt-trigger 10 T (known as ST2), modified PMOS-PMOS-NMOS-based cell core 10 T (MPPN10T), feedback-cutting 11 T (FC11T), Schmitt-trigger 11 T (ST11), and Schmitt-trigger 12 T (ST12T) cells. According to the simulation results, the proposed MST11T SRAM cell has RSNM of 2.42, 1.18, 1.71, 1.30, and 1.80 times higher when compared to 6 T, FC11T, ST2, MPPN10T, and ST12T, respectively. The WSNM of the proposed bit cell has been increased by 1.56, 2.44, 1.28, 1.71, 1.35, 1.52, and 1.02 times, respectively, over 6 T, 8 T, ST2, MPPN10T, FC11T, ST11T, and ST12T. Furthermore, the suggested cell has a read delay that is 1.32, 1.79, and 1.53 times lower than ST11T, FC11T, and ST12T, respectively. The proposed bit cell has a write delay that is 1.14 and 1.63 times lower than FC11T and ST11T, respectively. The proposed MST11T bit-cell consumes 3.74, 1.56, 4.59, 5.38, and 4.83 times less leakage power than the 8 T, ST2, MPPN10T, FC11T, and ST12 bit-cells, respectively. When compared to 8 T/ST2/MPPN10T/ST12T at 0.2 V supply voltage, the enhanced facts incur a 4.87/3.79/3.78/1.97 penalty in write delay. The figure of merit (FOM) is derived as a result of this extensive access to the revolutionary SRAM cell performance, i.e., offering greater values at a 0.2 V DC supply voltage. In addition, the paper examines the impact of manufacturing process and temperature changes on MST11T cell enactment, as well as the circuit robustness using HSPICE with 7-nm FinFET technology. [ABSTRACT FROM AUTHOR]

This paper investigates the use of approximate fixed-width and static segment multipliers in the design of Delayed Least Mean Square (DLMS) adaptive filters based on the sign–magnitude representation for the error signal. The fixed-width approximation discards part of the partial product matrix and introduces a compensation function for minimizing the approximation error, whereas the static segmented multipliers reduce the bit-width of the multiplicands at runtime. The use of sign–magnitude representation for the error signal reduces the switching activity in the filter learning section, minimizing power dissipation. Simulation results reveal that, by properly sizing the two approaches, a steady state mean square error practically unchanged with respect to the exact DLMS can be achieved. The hardware syntheses in a 28 nm CMOS technology reveal that the static segmented multipliers perform better in the learning section of the filter and are the most efficient approach to reduce area occupation, while the fixed-width multipliers offer the best performances in the finite impulse response section and provide the lowest power dissipation. The investigated adaptive filters overcome the state-of-the-art, exhibiting an area and power reduction with respect to the standard implementation up to −18.0% and −64.1%, respectively, while preserving the learning capabilities. [ABSTRACT FROM AUTHOR]

Numerous functionalities are provided by smartphones and prolonging their battery lifetime is an undeniably critical support issue. In this paper, we propose a low-power scheme called unnecessary region freezing (URF) that achieves significant total power consumption reduction in smartphones by reducing unnecessary drawing computation that originates from a user’s uninteresting display region. We implement URF on a real smartphone (Nexus 6). Then, we evaluate our scheme on top of an existing low-power scheme, partial display darkening (PDD). The results indicate that the URF scheme reduces total power consumption by average 5.1% through 12.5% depending on the size of the unnecessary region, compared with the PDD scheme. [ABSTRACT FROM AUTHOR]

Summary This paper introduces an area‐effective and low‐power readout circuit structure tailored for high dynamic range (HDR) CMOS image sensors (CISs) utilizing dual conversion gain (DCG) imaging technology. A switched capacitor amplifier, which is applied at the comparator input port of the column‐parallel single‐slope analog‐to‐digital converter (SS ADC), is proposed to compensate for the charge injection and clock feed‐through introduced when the pixel switches between high conversion gain (HCG) and low conversion gain (LCG) modes. The proposed SS ADC is supplemented by the integration of a configurable counter, and the counter is specifically crafted for performing the A/D conversion of the readout voltage within a DCG pixel. Compared to the conventional DCG readout circuit, the proposed readout circuit use only one ADC for A/D conversion of HCG signals and LCG signals, which greatly reduces the area and power consumption of the readout circuit. Simulation results under 110 nm CMOS technology illustrate that the proposed 10‐bit SS ADC has a DNL of +0.78/−0.91 LSB and an INL of +1.91/−1.69 LSB, with a SNR of 57.2 dB and a SNDR of 55.95 dB, corresponding to an ENOB of 9 bits. The power consumption of the proposed SS ADC is 56.4 μW per column with a conversion time of 12 μs, and the simulation results show that the power consumption is 23.35% lower than the conventional structure and the area is saved by 24.69%. [ABSTRACT FROM AUTHOR]

This paper presents static and dynamic theoretical analysis of a new Operational Transconductance Amplifier (OTA) dedicated to low-voltage and low-power applications. High linearity is obtained using signal attenuation for rail-to-rail operation. Design, layout and post-layout simulations have been carried-out with Cadence Virtuoso in a 0.18µm CMOS technology. Post-Layout Simulation (PLS) demonstrates proper operation down to ± 0.75 V supply voltage with a high open loop small-signal voltage gain of 58.26dB, a unity gain frequency of 18MHz and a total harmonic distortion of -66.55dB at 100 kHz for a peak-to-peak input voltage of 0.8V. Based on this circuit, two applications have been successfully demonstrated: on the one side, a 5th order Butterworth G mC filter and, on the other side, a voltage mode instrumentation amplifier. [ABSTRACT FROM AUTHOR]

Portable applications and battery-operated devices require highly reliable, stable, and low-power nanometer-sized embedded cache static random access memory (SRAM) cells. The conventional 6-transistor (6 T) SRAM cell and its variants suffer from malfunctioning during the read/write operations, and instability, and are vulnerable to the multi-bit soft-error rate at scaled technology node and low supply voltage (VDD). In this regard, this paper proposes an 12 T SRAM cell with reliable functioning and reduced multi-bit soft-errors appropriate for low-power portable applications. This cell performs single-end bitline decoupled read operation and write data-dependent feedback-cutting-aware differential write operation to improve the read static noise margin (RSNM) and write static noise margin (WSNM), respectively. The presence of stack transistors in the cell core and read path, and also high virtual ground (VGND) minimize the leakage power dissipation. The proposed cell is compared with other state-of-the-art SRAM cells at VDD = 0.7 V and under harsh process, voltage, and temperature (PVT) variations. It offers at least 1.18X higher RSNM, 1.27X higher WSNM, and 2.02X lower leakage power dissipation. It also shows the second-best read power and incurs a penalty in write power. This cell shows at least 1.17X, 1.32X, and 1.04X smaller spread in read delay, RSNM, and WSNM, respectively, when subjected to PVT variations. In addition, the proposed cell eliminates the write half-select disturbance by employing a separate gate to drive the access transistors and thus column-interleaving structure and error correction coding can be applied to reduce multiple-bit upset and increase soft-error immunity. The soft-error in the proposed cell is reduced by at least 1.37X in critical charge. Generally, the proposed cell offers the best overall performance among all the compared cells by showing the highest proposed figure of merit. [ABSTRACT FROM AUTHOR]

With the emergence of the internet-of-things (IoT), many devices process data through the IEEE 802.11 wireless networks. To satisfy the increased data processing, the wireless fidelity (Wi-Fi) networks must have sufficient capacity. IEEE 802.11ax is formulated to provide higher data processing capabilities for IoT applications. The IEEE 802.11ax receiver operating at 5 GHz must be able to withstand interference from nearby IoT applications. Hence, the low-noise amplifier (LNA) employed in such receivers must have a high input-referred third-order intercept point (IIP3). This paper aims to present a wideband LNA operating at 5 GHz with high IIP3 for modern IoT transceivers using IEEE 802.11ax protocol. The LNA is designed and implemented in UMC 65 nm CMOS technology using the Cadence virtuoso design tool. The proposed LNA can provide a maximum gain of 17.64 dB while consuming 8.18 mW of power from a 1.2 V supply. It can be noted that the minimum noise figure (NF) achieved is 3.67 dB and the corresponding IIP3 is 9.44 dBm at 5 GHz from the pre-layout simulations. [ABSTRACT FROM AUTHOR]

This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The timedomain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number. An energy efficient digital-to-analog converter (DAC) control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion. Together with the skipping-window technique, the linearity and the power consumption of the SAR ADC are improved. The impact of different window sizes on comparison cycles, DAC switching energy and the overall energy efficiency is analyzed. Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy. [ABSTRACT FROM AUTHOR]

Clock trees are commonly used to deliver clock signals to sequential elements in circuits. However, by construction, tree structures are inherently prone to failure caused by variations. The robustness of a clock tree can be improved by inserting redundancy in the form of cross links or multilevel fusion trees. Such near-tree structures can provide robustness at low cost. In this paper, we establish that the locations of the inserted redundancy are crucial in providing cost-effective robustness. We present two methods to systematically insert redundancy. The redundancy is realized by either inserting cross links or performing local merges. Moreover, we present a vertex reduction method that reduces the amount of redundancy that needs to be inserted in our near-tree structures. Empirical results show that our structures are more robust to variations and have lower power consumption compared to the state-of-the-art clock networks. Furthermore, our near-tree structures provide smooth trade-offs between cost and robustness, reducing clock skews by 11%–39% at an expense of 3%–68% higher power consumption. [ABSTRACT FROM PUBLISHER]

Remote sensing of physiological parameters could be a cost effective approach to improving health care, and low-power sensors are essential for remote sensing because these sensors are often energy constrained. This paper presents a power optimized photoplethysmographic sensor interface to sense arterial oxygen saturation, a technique to dynamically trade off SNR for power during sensor operation, and a simple algorithm to choose when to acquire samples in photoplethysmography. A prototype of the proposed pulse oximeter built using commercial-off-the-shelf (COTS) components is tested on 10 adults. The dynamic adaptation techniques described reduce power consumption considerably compared to our reference implementation, and our approach is competitive to state-of-the-art implementations. The techniques presented in this paper may be applied to low-power sensor interface designs where acquiring samples is expensive in terms of power as epitomized by pulse oximetry. [ABSTRACT FROM PUBLISHER]

In this paper we present SpikeOnChip, a custom embedded platform for neuronal activity recording and online analysis. The SpikeOnChip platform was developed in the context of automated drug testing and toxicology assessments on neural tissue made from human induced pluripotent stem cells. The system was developed with the following goals: to be small, autonomous and low power, to handle micro-electrode arrays with up to 256 electrodes, to reduce the amount of data generated from the recording, to be able to do computation during acquisition, and to be customizable. This led to the choice of a Field Programmable Gate Array System-On-Chip platform. This paper focuses on the embedded system for acquisition and processing with key features being the ability to record electrophysiological signals from multiple electrodes, detect biological activity on all channels online for recording, and do frequency domain spectral energy analysis online on all channels during acquisition. Development methodologies are also presented. The platform is finally illustrated in a concrete experiment with bicuculline being administered to grown human neural tissue through microfluidics, resulting in measurable effects in the spike recordings and activity. The presented platform provides a valuable new experimental instrument that can be further extended thanks to the programmable hardware and software. [ABSTRACT FROM AUTHOR]

Variable energy constraints affect the implementations of neural networks on battery-operated embedded systems. This paper describes a learning algorithm for randomization-based neural networks with hard-limit activation functions. The approach adopts a novel cost function that balances accuracy and network complexity during training. From an energy-specific perspective, the new learning strategy allows to adjust, dynamically and in real time, the number of operations during the network's forward phase. The proposed learning scheme leads to efficient predictors supported by digital architectures. The resulting digital architecture can switch to approximate computing at run time, in compliance with the available energy budget. Experiments on 10 real-world prediction testbeds confirmed the effectiveness of the learning scheme. Additional tests on limited-resource devices supported the implementation efficiency of the overall design approach. [ABSTRACT FROM AUTHOR]

This paper presents a sub-microwatt sub-bandgap voltage and current reference that can generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents concurrently. The voltage reference is derived from the process-insensitive silicon bandgap voltage of a bipolar junction transistor, whereas the current reference is made by combining PTAT and CTAT currents. Line regulation is improved by incorporating cascode devices without an operational amplifier (opamp). Fabricated in a standard 0.18-µm CMOS process, the proposed bandgap reference occupies an active area of 0.4 mm2. The current and voltage reference ( I REF and V REF ) are measured as 170 mV and 21 nA, respectively, while the start-up settling response is measured as 20 ms at room temperature. The average temperature coefficient of I REF and V REF is 79.8 ppm/°C and 87.93 ppm/°C across the temperature range from − 40 to 120 °C, respectively. The power consumption is 134 nW at the minimum supply voltage of 1.2 V. The power supply ripple rejection of V REF is measured as − 10 dB at 100 kHz without any filtering capacitor, when the 1.6 V input line voltage is distorted by a 300-mVp-p ripple. The measured line sensitivity of the voltage and current reference is 0.142%/V and 0.757%/V, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the performances of an Enhanced Static Segment Multiplier (ESSM) when the inputs have both uniform and non-uniform distribution. The enhanced segmentation divides the multiplicands into a lower, a middle, and an upper segment. While the middle segment is placed at the center of the inputs in other implementations, we seek the optimal position able to minimize the approximation error. To this aim, two design parameters are exploited: m, defining the size and the accuracy of the multiplier, and q, defining the position of the middle segment for further accuracy tuning. A hardware implementation is proposed for our generalized ESSM (gESSM), and an analytical model is described, able to find m and q which minimize the mean square approximation error. With uniform inputs, the error slightly improves by increasing q, whereas a large error decrease is observed by properly choosing q when the inputs are half-normal (with a NoEB up to 18.5 bits for a 16-bit multiplier). Implementation results in 28 nm CMOS technology are also satisfactory, with area and power reductions up to 71% and 83%. We report image and audio processing applications, showing that gESSM is a suitable candidate in applications with non-uniform inputs. [ABSTRACT FROM AUTHOR]

A low-power class-AB amplifier for high-fidelity headphones is presented. The linearity of a class-AB amplifier strongly depends on the loop gain over the audio band and voltage swing. In this paper, a cascode-driven mesh technique limits the number of high-swing nodes in the output stage, thereby preserving the loop gain of the preceding gain stages. A frequency compensation scheme is proposed that extends the unity-gain bandwidth (UGB) and increases the loop gain at 20 kHz. Combining these two techniques, the amplifier achieves −101.4-dB total harmonic distortion plus noise (THD+N) over the full audio band, the lowest ever reported nonlinearity among sub-milliwatt CMOS class-AB amplifiers. The amplifier delivers 51.2-mW peak power to a $16\Omega \|0.33$ -nF load while consuming 0.97 mW of total static power. It has UGB of 12.3 MHz and SNR of 108 dB. These results are consistent when measured over eight test chips. Compared to the recent prior art, the amplifier exhibits >12 dB better linearity and >14-dB dynamic range. This results in 2.5 $\times $ improvement in figure of merit (FOM = Peak Load Power/(Quiescent Power $\times $ THD+N[%])). It occupies 0.16 mm 2 in a standard 65-nm CMOS. [ABSTRACT FROM AUTHOR]

The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28-nm fully depleted silicon on insulator. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy or in the dynamic mode to increase speed, albeit with higher delay or energy consumption, respectively. In this paper, these two operational modes of the DML gates are optimally managed by a self-adjustment mechanism to increase speed or reduce the energy of gates/blocks in the design at run time. As a test case, a two-stage pipelined multiply–accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy, and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (up to 35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area. [ABSTRACT FROM AUTHOR]

Wireless body sensors are increasingly used by clinicians and researchers in a wide range of applications, such as sports, space engineering, and medicine. Monitoring vital signs in real time can dramatically increase diagnosis accuracy and enable automatic curing procedures, e.g., detect and stop epilepsy or narcolepsy seizures. Breathing parameters are critical in oxygen therapy, hospital, and ambulatory monitoring, while the assessment of cough severity is essential when dealing with several diseases, such as chronic obstructive pulmonary disease. In this paper, a low-power wireless respiratory monitoring system with cough detection is proposed to measure the breathing rate and the frequency of coughing. This system uses wearable wireless multimodal patch sensors, designed using off-the-shelf components. These wearable sensors use a low-power nine-axis inertial measurement unit to quantify the respiratory movement and a MEMs microphone to record audio signals. Data processing and fusion algorithms are used to calculate the respiratory frequency and the coughing events. The architecture of each wireless patch-sensor is presented. In fact, the results show that the small $26.67 \times 65.53$ mm2 patch-sensor consumes around 12–16.2 mA and can last at least 6 h with a miniature 100-mA lithium ion battery. The data processing algorithms, the acquisition, and wireless communication units are described. The proposed network performance is presented for experimental tests with a freely behaving user in parallel with the gold standard respiratory inductance plethysmography. [ABSTRACT FROM AUTHOR]

This paper presents a low-power coordinate rotation digital computer (CORDIC)-based reconfigurable discrete cosine transform (DCT) architecture. The main idea of this paper is based on the interesting fact that all the computations in DCT are not equally important in generating the frequency domain outputs. Considering the importance difference in the DCT coefficients, the number of CORDIC iterations can be dynamically changed to efficiently tradeoff image quality for power consumption. Thus, the computational energy can be significantly reduced without seriously compromising the image quality. The proposed CORDIC-based 2-D DCT architecture is implemented using 0.13 \mum CMOS process, and the experimental results show that our reconfigurable DCT achieves power savings ranging from 22.9% to 52.2% over the CORDIC-based Loeffler DCT at the cost of minor image quality degradations. [ABSTRACT FROM AUTHOR]

Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cutoff frequency due to the short-channel effects. To improve the low-cutoff frequency, one solution is to increase the feedback capacitors' value. This solution is not desirable, as the input capacitors have to be increased to maintain the same gain, which increases the area and decreases the input impedance of the neural amplifier. We analytically analyze the small-signal behavior of the neural amplifier and prove that the main reason for the increase of the low-cutoff frequency in advanced CMOS technologies is the reduction of the input resistance of the operational transconductance amplifier (OTA). We also show that the reduction of the input resistance of the OTA is due to the increase in the gate oxide leakage in the input transistors. In this paper, we explore this fact and propose two solutions to reduce the low-cutoff frequency without increasing the value of the feedback capacitor. The first solution is performed by only simulation and is called cross-coupled positive feedback that uses pseudoresistors to provide a negative resistance to increase the input resistance of the OTA. As an advantage, only standard CMOS transistors are used in this method. Simulation results show that a low-cutoff frequency of 1.5 Hz is achieved while the midband gain is 30.4 dB at 1 V. In addition, the power consumption is 0.6 μW. In the second method, we utilize thick-oxide MOS transistors in the input differential pair of the OTA. We designed and fabricated the second method in the 65 nm TSMC CMOS process. Measured results are obtained by in vitro recordings on slices of mouse brainstem. The measurement results show that the bandwidth is between 2 Hz and 5.6 kHz. The neural amplifier has 34.3 dB voltage gain in midband and consumes 3.63 μ W at 1 V power supply. The measurement results show an input-referred noise of 6.1 μ V rms and occupy 0.04 mm 2 silicon area. [ABSTRACT FROM AUTHOR]

In this paper, a low-power structure as an inverter-base circuit is reported for broadband applications. The focus in this study is in obtaining a low-power structure. By applying cascoded structure to an inverter as a feedforward network in the structure, the DC current and hence the power dissipation are decreased. Also, by adding a two-stage active feedback, which yields no miller capacitance, to the cascoded inverter, the structure of the TIA is completed. Simulation results in HSPICE using 90nm CMOS technology parameters show 41 dBΩ transimpedance gain, 6.5 GHz frequency bandwidth and 2.7 µArms input referred noise, which consumes only 1.67mw power at 1V supply. Results and analysis indicate that the proposed TIA is suitable to work as a low-power 10 Gbps transimpedance amplifier in an optical receiver. [ABSTRACT FROM AUTHOR]

IoT and wearable medical devices frequently require ultra-low power solutions that can support long spells of inactivity. This study presents a buck converter to control power stages using a novel pulse frequency modulation (PFM) system that reduces switching losses for low-power systems. The modulation of high and low-frequencies was demonstrated, where the high-frequencies exhibited better energy transformation between the inductor and capacitor, and the low-frequencies could be adjusted for different current loads, to reduce switching losses. This circuit is optimized for light load applications. Using voltage control oscillation (VCO), the frequency range of 0.5 MHz – 2.0 MHz can be adjusted to influence conversion efficiency for different loads. The design was simulated and then fabricated using TSMC 0.18um process. The core size was about 1500 × 1000um that includes power MOS. Measurements result an average conversion efficiency of 91% under a load of 0.1 mA – 10 mA. This chip is suitable for battery-based IoT systems, or wearable medical devices. [ABSTRACT FROM AUTHOR]