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In this study, we investigate the changes in the crystalline structure of MBE-deposited SrTiO3 layers on Si with different deviations from Sr/Ti stoichiometry as deposited but also after annealing at high temperatures (>600 °C). We show that as-grown 15 nm thick non-stochiometric SrTiO3 layers present surprisingly lower FWHM values of the (002) omega diffraction peak compared to fully stoichiometric layers of similar thickness. This can misleadingly point to superior crystalline quality of such non-stochiometric layers. However, thermal post-deposition anneals of these layers at temperatures up to 850 °C in oxygen show strong detrimental effects on the crystalline structure, surface and interface with the Si (001) substrate. On the contrary, the post-deposition anneals applied to the stoichiometric samples strongly improve the physical, optical and electrical properties of the epitaxial SrTiO3 thin films. [ABSTRACT FROM AUTHOR]

We investigate differential evolution optimization to fit Rutherford backscattering data. The algorithm helps to find, with very high precision, the sample composition profile that best fits the experimental spectra. The capabilities of the algorithm are first demonstrated with the analysis of synthetic Rutherford backscattering spectra. The use of synthetic spectra highlights the achievable precision, through which it becomes possible to differentiate between the counting statistical uncertainty of the spectra and the fitting error. Finally, the capability of the algorithm to analyze large sets of experimental spectra is demonstrated with the analysis of the position-dependent composition of a Sr x Ti y O z layer on a 200 mm silicon wafer. It is shown that the counting statistical uncertainty as well as the fitting error can be determined, and the reported total analysis uncertainty must cover both. [ABSTRACT FROM AUTHOR]

We report the synthesis and characterization of high-quality thin films of the topological semimetal (Bi2)5(Bi2Se3)7. Cryogenic magnetotransport experiments reveal strong metallic character and spin--orbit coupling in the films. By studying the temperature dependence of the electrical resistance of the topological semimetal, we observe a pronounced Kondo effect, which points toward the presence of magnetic scatterers. With the aid of density functional theory calculations, we identify Bi vacancies as intrinsic magnetic scatterers in this topological semimetal. [ABSTRACT FROM AUTHOR]

Barium titanate (BaTiO3 or BTO) is a perovskite structure material with interesting intrinsic properties, such as spontaneous ferroelectricity or electro-optical behavior, which strongly depend on thin film crystallinity. For such functional oxide systems, the pulsed-laser deposition (PLD) approach is one promising growth technique due to its precise stoichiometry control of the metals composing the perovskite crystal and higher oxygen environment compared to the classically used molecular beam epitaxy (MBE) approach. In this article, we demonstrate a BTO epitaxial layer by PLD onto an Si(001) substrate thanks to a thin pseudomorphic SrTiO3 buffer layer grown by MBE. In our study, the various investigated PLD parameters show strong impacts on the BTO polarization orientation. Hence, adjusting the growth conditions allows control of the polarization orientation, which is crucial for both electronic and optical applications. In addition, lattice parameter changes of BTO layers are investigated using x-ray diffraction and cross-sectional transmission electron microscopy, which evidenced a correlation between mismatch relaxation and oxygen growth pressure. Finally, with the analysis of BTO C–V curves, the polarization direction transition is demonstrated electrically. [ABSTRACT FROM AUTHOR]

In0.53Ga0.47As p + n diodes with different densities of extended defects have been analyzed by detailed structural and electrical characterization. The defects have been introduced during Metal-Organic Vapor Phase Epitaxy (MOVPE) growth by using a lattice-mismatched layer on a semi-insulating InP or GaAs substrate. The residual strain and indium content in the n-type In0.53Ga0.47As layer have been determined by high-resolution X-ray diffraction, showing nearly zero strain and a fixed indium ratio of 0.53. The deep levels in the layer have been characterized by Deep Level Transient Spectroscopy. The mean value of electron traps at 0.17 ± 0.03 eV below the conduction band minimum EC is assigned to the "localized" states of α 60° misfit dislocations; another broad electron trap with mean activation energies between EC− 0.17 ± 0.01 and 0.39 ± 0.04 eV, is identified as threading dislocation segments with "band-like" states. A high variation of the pre-exponential factor KT by 7 orders of magnitude is found for the latter when changing the filling pulse time, which can be explained by the coexistence of acceptor-like and donor-like states in the core of split dislocations in III-V materials. Furthermore, two hole traps at EV+ 0.42 ± 0.01 and EV+ 0.26 ± 0.13 eV are related to the double acceptor of the Ga(In) vacancy (VGa/In3-/2-) and 60° β misfit dislocations, respectively. Finally, the dislocation climbing mechanism and the evolution of the antisite defects AsGa/In are discussed for n-type In0.53Ga0.47As. [ABSTRACT FROM AUTHOR]

Herein, the carrier lifetime in ≈5 × 1016 cm−3 n‐doped InxGa1−xAs layers is studied by diode current–voltage analysis and by time‐resolved photoluminescence. Two sets of hetero‐epitaxial layers are grown on semi‐insulating InP or GaAs substrates. The first set corresponds with a constant In content p + n stack, while the second set has a fixed x = 0.53 for the n‐layer, while containing various extended defect densities by using a strain relaxed buffer with different x. This results in threading dislocation densities (TDDs) between ≈105 cm−2 and a few 109 cm−2. It is shown that the overall trend of the recombination lifetime versus TDD can be described by a first‐order model considering a finite recombination lifetime value inside a dislocation core of 1 nm. For the generation lifetime, a strong electric‐field enhancement factor is found. Also, the residual strain in the n‐layer has an impact. Overall, the safe limit for TDD depends on the type of application and on the operation conditions (reverse diode bias). [ABSTRACT FROM AUTHOR]

In this work, we present a systematic study of the effect of the stoichiometry of BaTiO3 (BTO) films grown on the Ge(001) substrate by molecular-beam-epitaxy using different characterization methods relying on beam diffraction, including reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), and selected-area electron diffraction in transmission electron microscopy. Surprisingly, over a wide range of [Ba]/[Ti] ratios, as measured by the Rutherford backscattering spectrometry, all the BTO layers exhibit the same epitaxial relationship h100iBTO(001)// 〈110〉Ge(001) with the substrate, describing a 45° lattice rotation of the BTO lattice with respect to the Ge lattice. However, varying the [Ba]/[Ti] ratio does change the diffraction behavior. From RHEED patterns, we can derive that excessive [Ba] and [Ti] generate twinning planes and a rougher surface in the non-stoichiometric BTO layers. XRD allows us to follow the evolution of the lattice constants as a function of the [Ba]/[Ti] ratio, providing an option for tuning the tetragonality of the BTO layer. In addition, we found that the intensity ratio of the 3 lowest-order Bragg peaks I(001)/ I(002), I(101)/I(002), and I(111)/I(002) derived from ω-2θ scans characteristically depend on the BTO stoichiometry. To explain the relation between observed diffraction patterns and the stoichiometry of the BTO films, we propose a model based on diffraction theory explaining how excess [Ba] or [Ti] in the layer influences the diffraction response. [ABSTRACT FROM AUTHOR]

Metrology for structural and electrical analyses at device level has been identified as one of the major challenges to be resolved for the sub-14 nm technology nodes. In these advanced nodes, new high mobility semiconductors, such as III–V compounds, are grown in narrow trenches on a Si substrate. Probing the nature of the defects, the defect density, and the role of processing steps on the surface of such structures are prime metrology requirements. In order to enable defect analysis on a (III–V) surface, a proper sample preparation for oxide removal is of primary importance. In this work, the effectiveness of different chemical cleanings and thermal annealing procedures is investigated on both blanket InP and oxide embedded InP trenches by means of scanning probe microscopy techniques. It is found that the most effective approach is a combination of an HCl-based chemical cleaning combined with a low-temperature thermal annealing leading to an oxide free surface with atomically flat areas. Scanning tunneling microscopy (STM) has been the preferred method for such investigations on blanket films due to its intrinsic sub-nm spatial resolution. However, its application on oxide embedded structures is non-trivial. To perform STM on the trenches of interest (generally <20 nm wide), we propose a combination of non-contact atomic force microscopy and STM using the same conductive atomic force microscopy tip Our results prove that with these procedures, it is possible to perform STM in narrow InP trenches showing stacking faults and surface reconstruction. Significant differences in terms of roughness and terrace formation are also observed between the blanket and the oxide embedded InP. [ABSTRACT FROM AUTHOR]

Large‐area epitaxy of layered materials is one of the cornerstones for a successful exploitation of van der Waals (vdW) materials in the semiconductor industry. The formation of 60° twin stacking faults and 60° grain boundaries is of major concern for the defect‐free epitaxial growth. Although strategies to overcome the occurrence of these defects are being considered, more fundamental understanding on the origin of these defects is highly essential. This work focuses on understanding the formation of 60° twins in (quasi‐)vdW epitaxy of 2D chalcogenides. Molecular beam epitaxy (MBE) experiments reveal the striking difference in 60° twin occurrence between WSe2 and Bi2Se3 in both quasi‐vdW heteroepitaxy and vdW homoepitaxy. Density functional theory (DFT) calculations link this difference to the interlayer vdW coupling strength at the unit cell level. The stronger interlayer vdW coupling in Bi2Se3 unit cells compared to WSe2 unit cells is explained to result in a reduced twin occurrence. Hence, such compounds show significantly more promise for defect‐free epitaxial integration. This interesting aspect of (quasi‐)vdW epitaxy reveals that the strength of interlayer vdW coupling is key for workable 2D materials and opens perspectives for other strongly coupled vdW materials. [ABSTRACT FROM AUTHOR]

Two-dimensional transition metal dichalcogenide (TMD) semiconductors have risen as an important material class for novel nanoelectronic applications. Molybdenum disulfide (MoS2) is the most representative TMD compound due to its superior stability and attractive properties for (opto-) electronic devices. However, the synthesis of single-crystalline and functional MoS2 across large-area substrates remains crucial for its successful integration in semiconductor industry platforms. Therefore, this work focuses on the study of MoS2 epitaxy via two well-established industry-compatible synthesis methods, promising for the large-area and single-crystalline integration of van der Waals (vdW) materials. These methods are molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE) and have studied MoS2 quasi-vdW heteroepitaxy on reconstructed sapphire substrates and MoS2 vdW homoepitaxy on exfoliated MoS2 flakes. By examining the MoS2 structural properties using diffraction and spectroscopy techniques, the epitaxial relation and crystal quality are assessed, which reveals insights into the prevalence of inter- and intragrain defects such as grain boundaries and sulfur vacancies. The MBE method yields superior epitaxial MoS2 registry on both sapphire and MoS2 surfaces as compared to MOVPE, although inferior defectivity arises from the typical lower MBE growth temperature and chalcogen partial pressure. Moreover, both synthesis methods generate high densities of twinned MoS2 grain boundaries, which hamper defect-free integration. As a result, this challenging integration might become an important bottleneck for industrial TMD-based applications with a low tolerance for material defects. [ABSTRACT FROM AUTHOR]

We compare the contact characteristics for Mo, Pd, and Ti on n-InGaAs layer with a range of active donor concentration from $1.6 \times 10^{18}$ cm−3 to $4.8 \times 10^{19}$ cm−3. The Fermi level pinning of 0.18 eV lower than the bottom of n-InGaAs conduction band is experimentally manifested. It is also revealed that the contact resistivity ($\rho _{\text {c}}$) of Mo/n-InGaAs contact clearly outperforms after annealing. However, for the first time, we demonstrate that the Mo/Pd (2nm)/n-InGaAs contact can achieve a $\rho _{\text {c}}~35$ % and 20% lower than a single Mo/n-InGaAs contact after annealing at 400 °C and 450 °C for 1min, respectively. [ABSTRACT FROM AUTHOR]

We use an improved AC conductance method and a modified Gray-Brown method to study fast interface traps and slow border traps in Ge-based MOS capacitors. The combined methods provide the corrected Fermi energy level (E) versus gate voltage (Vg) relationship, even in samples with high densities of traps that cause significant C-V distortion, the energy distribution of interface traps, their capture cross sections (σ), as well as slow border traps. A wide range of σ's in p-type Ge is found, indicating that there is more than one type of interface trap near the Ge valence band edge. In contrast, a constant σ near the Ge conduction band edge is observed in n-type Ge. XPS results indicate that Ge suboxides near the interface are accountable for the detected slow border traps. [ABSTRACT FROM AUTHOR]

In this work, the epitaxy of SrTiO3 and BaTiO3 perovskites on the (001)-oriented silicon substrate by molecular beam epitaxy is investigated. The heterostructures are studied by means of various structural and electrical characterization techniques. In this study especially, the authors reveal experimentally by nanobeam electron diffraction analysis the critical thickness prior relaxation of BaTiO3 grown on an SrTiO3/Si pseudosubstrate. They also propose to use a strain mediated superlattice composed of stacked [BaTiO3/SrTiO3] bilayers to prevent misfit dislocation formation. Using this approach, they could demonstrate high quality and dislocation free BaTiO3 ferroelectric layers integrated on silicon as confirmed by piezo-force microscopy techniques. [ABSTRACT FROM AUTHOR]

Abstract: Extracting plasmon‐induced hot carriers over a metal–semiconductor Schottky barrier enables photodetection below the semiconductor bandgap energy. However, interfacial carrier recombination hinders the efficiency and stability of this process, severely limiting its implementation in telecommunication. This study proposes and demonstrates the use of epitaxially grown lattice‐matched SrTiO3 for interfacial passivation of silicon‐based plasmonic Schottky devices. The devices are activated by an electrical soft‐breakdown of the interfacial SrTiO3 layer, resulting in reproducible rectified Schottky characteristics. The transition to a low resistance state of the SrTiO3 layer boosts the extraction efficiency of hot holes upon resonant plasmonic excitation, giving rise to a two orders of magnitude higher photocurrent compared to devices with a native oxide layer. Photoresponse, tunability, and barrier height studies under reverse biases as high as 100 V present superior stability with the incorporation of the SrTiO3 layer. The investigation paves the way toward plasmon‐induced photodetection for practical applications including those under challenging operating conditions. [ABSTRACT FROM AUTHOR]

Silicon does not emit light efficiently, therefore the integration of other light-emitting materials is highly demanded for silicon photonic integrated circuits. A number of integration approaches have been extensively explored in the past decade. Here, the most recent progress in this field is reviewed, covering the integration approaches of III-V-to-silicon bonding, transfer printing, epitaxial growth and the use of colloidal quantum dots. The basic approaches to create waveguide-coupled on-chip light sources for different application scenarios are discussed, both for silicon and silicon nitride based waveguides. A selection of recent representative device demonstrations is presented, including high speed DFB lasers, ultra-dense comb lasers, short (850nm) and long (2.3μm) wavelength lasers, wide-band LEDs, monolithic O-band lasers and micro-disk lasers operating in the visible. The challenges and opportunities of these approaches are discussed. [ABSTRACT FROM AUTHOR]

In this work, we report on wet-chemical defect revealing in InP fin structures relevant for device manufacturing. Both HCl and HBr solutions were explored using bulk InP as a reference. A distinct difference in pit morphology was observed between the two acids, attributed to an anisotropy in step edge reactivity. The morphology of the etch pits in bulk InP suggests that the dislocations are oriented mainly perpendicular to the surface. By studying the influence of the acid concentration on the InP fin recess in nanoscale trenches, it was found that aqueous HCl solution was most suitable for revealing defects. Planar defects in InP fin structures grown by the aspect ratio trapping technique could be visualized as characteristic shallow grooves approximately one nanometer deep. It is challenging to reveal defects in wide-field InP fins. In these structures, dislocations also reach the surface next to stack faults or twinning planes. Due to the inclined nature, dislocation-related pits are only a few atomic layers deep. Extending the pits is limited by the high reactivity of the fin sides and the strong surface roughening during etching. The process window for revealing wet-chemical defects in InP fins is limited. [ABSTRACT FROM AUTHOR]

Vertical InAs nanowires (NWs) grown on a Si substrate are promising building-blocks for next generation vertical gate-all-around transistor fabrication. We investigate the initial stage of InAs NW selective area epitaxy (SAE) on a patterned Si (111) substrate with a focus on the interfacial structures. The direct epitaxy of InAs NWs on a clean Si (111) surface is found to be challenging. The yield of vertical InAs NWs is low, as the SAE is accompanied by high proportions of empty holes, inclined NWs, and irregular blocks. In contrast, it is improved when the NW contains gallium, and the yield of vertical InxGa1-xAs NWs increased with higher Ga content. Meanwhile, unintentional Ga surface contamination on a patterned Si substrate induces high yield vertical InAs NW SAE, which is attributed to a GaAs-like seeding layer formed at the InAs/Si interface. The role of Ga played in the III-V NW nucleation on Si is further discussed. It stabilizes the B-polarity on a non-polar Si (111) surface and enhances the nucleation. Therefore, gallium incorporation on a Si surface is identified as an important enabler for vertical InAs NW growth. A new method for high yield (>99%) vertical InAs NW SAE on Si using an InGaAs nucleation layer is proposed based on this study. [ABSTRACT FROM AUTHOR]

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an \(L_{\mathrm {\mathbf {G}}}\) of 60 nm an extrinsic \(g_{\mathrm {\mathbf {m}}}\) of \(1030~\mu \) S \(/\mu \) m at \(V_{\mathrm {\mathbf {ds}}} = 0.5\) V is achieved which is a \(1.75\times \) increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to \(D_{\mathrm {{it}}}\) resulting in an SS \(_{\mathrm {{SAT}}}\) of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm \(L_{\mathrm {{G}}}\) devices. [ABSTRACT FROM AUTHOR]

Trap spectroscopy by charge injection and sensing method was applied to the \In0.53\Ga0.47\As{-}\Al2\O3 system, yielding the spatial and energetic distribution of the traps inside the \Al2\O3 layer. The trap density inside the atomic-layer-deposited (ALD) \Al2\O3 layer was found to be significantly reduced by (\NH4)2\S treatment of the InGaAs surface prior to the \Al2\O3 deposition. Indium concentration inside the \Al2\O3 layer was found to be reduced once the InGaAs surface is (\NH4)2\S treated prior to the \Al2\O3 deposition as measured by time-of-flight secondary ion mass spectroscopy, indicating indium as a possible origin of the oxide traps. The results suggest a new mechanism for the sulfur action at the InGaAs surface, which might be responsible for the transistor performance improvements observed after ( \NH4)2\S passivation. This mechanism involves sulfur as an indium diffusion/segregation barrier stabilizing the InGaAs surface during the ALD \Al2\O3 deposition, lowering the oxide trap density. This, in turn, improves the electron mobility through a reduction in the Coulomb scattering of the carriers due to border traps and improves the device drive current. [ABSTRACT FROM PUBLISHER]

We introduce an ac transconductance dispersion method (ACGD) to profile the oxide traps in an MOSFET without needing a body contact. The method extracts the spatial distribution of oxide traps from the frequency dependence of transconductance, which is attributed to charge trapping as modulated by an ac gate voltage. The results from this method have been verified by the use of the multifrequency charge pumping (MFCP) technique. In fact, this method complements the MFCP technique in terms of the trap depth that each method is capable of probing. We will demonstrate the method with InP passivated InGaAs substrates, along with electrically stressed Si N-MOSFETs. [ABSTRACT FROM AUTHOR]

The efficiency of the ammonium sulfide vapor (ASV) treatment, as opposed to the wet treatment in the liquid ammonium sulfide solution, on the performance improvement of the In0.53Ga0.47As surface-channel as well as InP-capped buried-channel metal-oxide-semiconductor field-effect-transistors (MOSFET) was demonstrated for the first time. MOSFETs were fabricated with either HCl or ASV surface treatments prior to the gate oxide deposition. ASV treatment was found to be very efficient in boosting the drive current of the transistors compared to that of the HCl treatment. It was also found that the ASV treatment leads to a lower border trap density and slightly higher oxide/semiconductor interface defect density compared to that of the HCl treatment. X-ray photoelectron spectroscopy (XPS) studies of In0.53Ga0.47As native oxide regrowth after both surface treatments identified indium sub-oxides as a possible cause of the performance degradation of the HCl treated devices. Based on this work, ASV treatment could be an efficient solution to the passivation of III-V surfaces. [ABSTRACT FROM AUTHOR]

The observation and interpretation of Frank stacking faults, Shockley stacking faults, Lomer dislocations, and 60° misfit dislocations, which have similar line shapes in the (001) In0.53Ga0.47As crystalline surface, are performed with the electron channeling contrast imaging (ECCI) technique. To minimize the backscattered electron (BSE) contrast that resulted from the surface morphology, a relatively flat region is first selected and compared with an atomic force microscopy (AFM) image and then, subsequently, examining ECCI with transmission electron microscopy (TEM)‐like invisibility criteria. By orthogonally choosing the diffraction vector g between (220) and (2‐20), misfit dislocations seem to be always visible but partially faint in the g parallel to the line direction on the surface. With respect to the image contrast, Frank stacking faults and Lomer dislocations are likely to be completely invisible for parallel g. The criteria are further confirmed by cross‐sectional TEM analysis, which shows a preferred homogeneous surface nucleation. [ABSTRACT FROM AUTHOR]

Passivation of InP surface was carried out in situ with molecular-beam-deposited high-κ Al2O3. InP samples with surface orientations of (001), (110), and (111) were investigated. An atomically smooth Al2O3/InP(001) interface was observed without interfacial layer formation. In-rich surfaces gave better interfacial quality as evidenced by the improved capacitance–voltage characteristics, exhibiting smaller frequency dispersions and minimized inversion response. The energy distributions of interfacial traps (Dit's) were revealed by conductance measurement for the samples with In-rich surfaces. The Dit's are as low as ∼1011 cm-2 eV-1 near the conduction band edge, while those near the midgap region are ∼1013 cm-2 eV-1. [ABSTRACT FROM AUTHOR]

Atomic layer deposition of Al:ZrO2 films on In0.53Ga0.47As substrates is shown to be a promising route to boost the oxide permittivity with respect to Al2O3 gate dielectrics and concomitantly take benefit from the reducing effect of the trimethylaluminum precursor on the In0.53Ga0.47As surface. We demonstrates that increasing the number of initial Al2O3 cycles in the growth sequence can improve the physical quality and the electrical response of the Al:ZrO2/In0.53Ga0.47As interface while preserving the overall composition of the oxide. [ABSTRACT FROM AUTHOR]

In this study, we investigate the limitations to sheet resistance and Hall effect characterization of ultra-shallow junctions (USJs) in In0.53Ga0.47As. We compare conventional van der Pauw and Hall effect measurements with micro four-point probe (M4PP) and micro Hall effect methods. Due to the high carrier mobility of InGaAs, we extend the micro-Hall effect position error suppression method to also take geometrical magnetoresistance into account. We find that the conventional techniques fail to measure accurately on n++/p+ USJ due to a significant leakage current, whereas the M4PP and micro Hall effect methods are able to give accurate results. Finally, we observe a significant reduction in the carrier mobility for InGaAs USJ. [ABSTRACT FROM AUTHOR]

The growth of crystalline Li-based oxide thin films on silicon substrates is essential for the integration of next-generation solid-state lithionic and electronic devices including on-chip microbatteries, memristors, and sensors. However, growing crystalline oxides directly on silicon typically requires high temperatures and oxygen partial pressures, which leads to the formation of undesired chemical species at the interface compromising the crystal quality of the films. In this work, we employ a 2 nm gamma-alumina (γ-Al 2 O 3 ) buffer layer on Si substrates in order to grow crystalline thin films of Li 4 Ti 5 O 12 (LTO), a well-known active material for lithium-ion batteries. The ultrathin γ-Al 2 O 3 layer enables the formation of a stable heterostructure with sharp interfaces and drastically improves the LTO crystallographic and electrochemical properties. Long-term galvanostatic cycling of 50 nm LTO films in liquid-based half-cells demonstrates a high capacity retention of 91% after 5000 cycles at 100 C. Rate capability tests showcase a specific charge of 56 mA h g -1 at an exceptional C-rate of 5000 C (15 mA cm -2 ). Moreover, with sub-millisecond current pulse tests, the reported thin-film heterostructure exhibits rapid Li-ion (de)intercalation, which could lead to fast switching timescales in resistive memory devices and electrochemical transistors.

The increasing scientific and industry interest in 2D MX 2 materials within the field of nanotechnology has made the single crystalline integration of large area van der Waals (vdW) layers on commercial substrates an important topic. The c-plane oriented (3D crystal) sapphire surface is believed to be an interesting substrate candidate for this challenging 2D/3D integration. Despite the many attempts that have been made, the yet incomplete understanding of vdW epitaxy still results in synthetic material that shows a crystallinity far too low compared to natural crystals that can be exfoliated onto commercial substrates. Thanks to its atomic control and in situ analysis possibilities, molecular beam epitaxy (MBE) offers a potential solution and an appropriate method to enable a more in-depth understanding of this peculiar 2D/3D hetero-epitaxy. Here, we report on how various sapphire surface reconstructions, that are obtained by thermal annealing of the as-received substrates, influence the vdW epitaxy of the MBE-grown WSe 2 monolayers (MLs). The surface chemistry and the interatomic arrangement of the reconstructed sapphire surfaces are shown to control the preferential in-plane epitaxial alignment of the stoichiometric WSe 2 crystals. In addition, it is demonstrated that the reconstructions also affect the in-plane lattice parameter and thus the in-plane strain of the 2D vdW-bonded MLs. Hence, the results obtained in this work shine more light on the peculiar concept of vdW epitaxy, especially relevant for 2D materials integration on large-scale 3D crystal commercial substrates.

An imperative factor in adapting GeSn as the channel material in CMOS technology, is the gate-oxide stack. The performance of GeSn transistors is degraded due to the high density of traps at the oxide-semiconductor interface. Several oxide-gate stacks have been pursued, and a midgap Dit obtained using the ac conductance method, is found in literature. However, a detailed signature of oxide traps like capture cross-section, donor/acceptor behavior and profile in the bandgap, is not yet available. We investigate the transition region between stoichiometric insulators and strained GeSn epitaxially grown on virtual Ge substrates. Al2O3 is used as high-κ oxide and either Ge1-xSnxO2 or GeO2 as interfacial layer oxide. The interface trap density (Dit) profile in the lower half of the bandgap is measured using deep level transient spectroscopy, and the importance of this technique for small bandgap materials like GeSn, is explained. Our results provide evidence for two conclusions. First, an interface traps density of 1.7 × 10(13) cm(-2)eV(-1) close to the valence band edge (Ev + 0.024 eV) and a capture cross-section (σp) of 1.7 × 10(-18) cm(2) is revealed for GeSnO2. These traps are associated with donor states. Second, it is shown that interfacial layer passivation of GeSn using GeO2 reduces the Dit by 1 order of magnitude (2.6 × 10(12) cm(-2)eV(-1)), in comparison to GeSnO2. The results are cross-verified using conductance method and saturation photovoltage technique. The Dit difference is associated with the presence of oxidized (Sn(4+)) and elemental Sn in the interfacial layer oxide.

On-chip optical interconnects still miss a high-performance laser monolithically integrated on silicon. Here, we demonstrate a silicon-integrated InP nanolaser that operates at room temperature with a low threshold of 1.69 pJ and a large spontaneous emission factor of 0.04. An epitaxial scheme to grow relatively thick InP nanowires on (001) silicon is developed. The zincblende/wurtzite crystal phase polytypism and the formed type II heterostructures are found to promote lasing over a wide wavelength range.