41 results on '"Raghavan, Praveen"'
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2. Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs
3. Single- and multilayer graphene wires as alternative interconnects
4. Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes
5. Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model
6. EMPIRE: Empirical power/area/timing models for register files
7. Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems
8. Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios
9. DART—a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
10. Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
11. Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures
12. An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors
13. Locality optimization in a compiler for wireless applications
14. Distributed loop controller for multithreading in unithreaded ILP architectures
15. Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI.
16. Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules.
17. Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology.
18. MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts.
19. Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node.
20. Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier.
21. A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less.
22. Impact of Wire Geometry on Interconnect RC and Circuit Delay.
23. Comparison of short-channel effects in monolayer MoS2 based junctionless and inversion-mode field-effect transistors.
24. Architectural strategies in standard-cell design for the 7 nm and beyond technology node.
25. Benchmarking of MoS2 FETs With Multigate Si-FET Options for 5 nm and Beyond.
26. Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node.
27. A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency.
28. Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era.
29. Technology/Circuit/System Co-Optimization and Benchmarking for Multilayer Graphene Interconnects at Sub-10-nm Technology Node.
30. Vertical GAAFETs for the Ultimate CMOS Scaling.
31. System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.
32. Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates.
33. Implications of BTI-Induced Time-Dependent Statistics on Yield Estimation of Digital Circuits.
34. Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication.
35. Future Software-Defined Radio Platforms and Mapping Flows.
36. Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.
37. Bilayer Graphene Tunneling FET for Sub-0.2 V Digital CMOS Logic Applications.
38. Polarity control in WSe2 double-gate transistors.
39. Exchange-driven Magnetic Logic.
40. Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes.
41. Polarity control in WSe2 double-gate transistors.
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