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Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (∼3× faster while simultaneously consuming ∼3× less energy) compared to Si/SiGe FinFET. The ATOs provide <50% EDP benefits. All analyses are performed at the same off-state leakage current density (≤100 nA per micron of FET width) and power density (≤100 W/cm2of chip area). This analysis provides insights into the sources of CNFET EDP benefits and addresses key questions for deeply-scaled technologies. For instance, while contact resistance is a concern for sub-10 nm nodes, CNFETs still provide up to 6.0× EDP benefit (versus Si/SiGe FinFETs) using CNFET contact resistance values already experimentally achieved for 9 nm contact length. [ABSTRACT FROM AUTHOR]

Standard-cell design, technology choices, and place and route (P&R) efficiency are deeply interrelated in CMOS technology nodes below 10 nm, where lower number of tracks cells and higher pin densities pose increasingly challenging problems to the router in terms of congestion and pin accessibility. To evaluate and downselect the best solutions, a holistic design-technology co-optimization approach leveraging state-of-theart P&R tools is thus necessary. We adopt such an approach using the imec N7 technology platform, with contacted poly pitch of 42 nm and tightest metal pitch of 32 nm, by comparing post P&R area of an IP block for different standard cell configurations, technology options, and cell height. Keeping the technology node and the set of ground rules unchanged, we demonstrate that a careful combination of these solutions can enable area gains of up to 50%, comparable with the area benefits of migrating to another node. We further demonstrate that these area benefits can be achieved at isoperformance with >20% reduced power. As at the end of the CMOS roadmap, conventional scaling enacted through pitch reduction is made more and more challenging by constraints imposed by lithography limits, material resistivity, manufacturability, and ultimately wafer cost, the approach shown herein offers a valid, attractive, and low-cost alternative. [ABSTRACT FROM AUTHOR]

A novel sub-threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9 T-SRAM cell offers an improved access time in comparison to the 8 T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8 T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at VDD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Self-aligned multiple patterning, due to its low overlay error, has emerged as the leading option for 1-D gridded back-end-of-line (BEOL) in sub-14-nm nodes. To form actual routing patterns from a uniform “sea of wires,” cut masks are needed for line-end cutting or realization of space between routing segments. The line-end cutting results in nonfunctional (i.e., dummy fill) patterns that change wire capacitance, and hence design timing and power. Therefore, to remove such dummy fill patterns, extra 2-D block masks are used. However, 2-D block masks cannot remove arbitrary dummy fill patterns, due to design rule constraints on the block mask shapes. In this paper, we address the timing-aware optimization of 2-D block mask layouts under various sets of mask rules that are derived from mask patterning technology options (e.g., 193i and 193d) for foundry 7-/5-nm (N7/N5) BEOL. Our central contribution is a mixed integer linear programming (MILP) optimization that minimizes timing impact due to dummy metal segments while satisfying block mask rules and metal density constraints. We also propose a distributed optimization flow to improve the scalability. With our optimizer, we recover up to 84% of the worst negative slack impact from dummy segments, with up to 64% dummy removal rate. We further extend our MILP to a co-optimization of cut and block masks. This paper gives new insights into fundamental limits of benefit from emerging cut and block mask technology options. [ABSTRACT FROM AUTHOR]

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling. [ABSTRACT FROM PUBLISHER]

The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of standard latch-type sense amplifier (SA), which is one of the critical components of high performance memories; the analysis is done by incorporating the impact of process, voltage, and temperature variations (in order to investigate the severity of the integral impact) and by considering different workloads and four technology nodes (i.e., 45, 32, 22, and 16 nm). The results show the importance of taking the SA degradation into consideration for robust memory design; the SA degradation depends on the application and technology node, and the sensing delay can increase with 184.58% for the worst case conditions at 16 nm. The results also show that the BTI impact for nominal conditions at 16 nm reaches a 12.10% delay increment. On top of that, when extrinsic conditions are considered, the degradation can reach up to 168.45% at 398 K for 16 nm. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque magnetoresistance random access memory is a major contender for static random access memory replacement in embedded caches at advanced fin field effect transistor nodes. It suffers, however, from the low resistance difference between the bistable states of the magnetic tunnel junction (MTJ). Variability on MTJ resistance and access transistors makes reliable read-out even more challenging. This triggered the use of complementary cells for low level caches needing high performance. This paper, focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell’s three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%. The novel variation resilient write operation also uses all three transistors and takes advantage of the inherent MTJ characteristics and complementary operation of the cell. This increases the write performance by $2\times $ and reduces the write energy by $3\times $ compared with the 2T 2MTJ cell and by $1.5\times $ compared with the 1T 1MTJ cell. [ABSTRACT FROM PUBLISHER]

We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low- $k$ damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technology node. The capacitance is simulated by means of a 2D field solver (Raphael) by Synopsys. The impact of line dimensions is analyzed for the case of 32 nm pitch interconnects, which are representative of the 7 nm logic technology node. We show that for aspect ratios greater than 1, the resistance is more sensitive to variations of the line width rather than of the line height, because of the higher surface scattering induced by the sidewall interfaces, which are closer to each other compared with the top and bottom interfaces. For capacitance, low- $k$ sidewall damage exacerbates capacitance sensitivity to line dimensions and, for typical interconnect schemes, the impact of line width variations dominates over variations of the line height. We demonstrate that for a given pitch and dielectric stack height, the RC delay can be significantly reduced by targeting wider and deeper damascene trenches, that is, by trading capacitance for resistance, and that an optimal wire geometry for RC delay minimization exists. In addition, we show that a given RC delay can be achieved with several geometries and, therefore, $R$ and $C$ pairs, which represents a useful degree of freedom for designers to optimize system-level performance. As an application, we analyze a possible 7 nm technology scenario and show that wide and deep damascene trenches can mitigate the impact of the increased wire resistance on circuit delay. [ABSTRACT FROM AUTHOR]

Conventional junctionless (JL) multi-gate (MuG) field-effect transistors(FETs) require extremely scaled channels to deliver high on-state current with low short-channel effect related leakage. In this letter, using ultra-thin 2D materials (e.g., monolayer MoS2), we present comparison of short-channel effects in JL, and inversion-mode (IM) FETs. We show that JL FETs exhibit better sub-threshold slope (S.S.) and drain-induced-barrier-lowering (DIBL) in comparison to IM FETs due to reduced peak electric field at the junctions. But, threshold voltage (VT) roll-off with channel length downscaling is found to be significantly higher in JL FETs than IM FETs, due to higher source/drain controlled charges (dE/dx) in the channel. Further, we show that although VT roll-off in JL FETs improves by increasing the gate control, i.e., by scaling the oxide, or channel thickness, the sensitivity of threshold voltage on structural parameters is found out to be high. [ABSTRACT FROM AUTHOR]

Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed. [ABSTRACT FROM AUTHOR]

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET. [ABSTRACT FROM PUBLISHER]

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power. [ABSTRACT FROM PUBLISHER]

Emerging 4G wireless communication systems need to deliver much higher data rates, more flexibility, and a significantly higher energy efficiency than current systems. To cope with this immense increase of requirements, new design approaches are a necessity. This paper focuses on the design of an advanced multiple-input–multiple-output (MIMO) detector, which is typically a bottleneck in the wireless receiver. In the proposed template-based design approach innovative architecture concepts, such as very wide register and distributed loop buffer, and algorithm-architecture co-optimizations are combined. The resulting MIMO detector processor, which is scalable to eight and more antennas, achieves a high area efficiency of 571 GOPS/ \mathrmmm^2 and a high energy efficiency of 3.3 GOPS/mW in the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm technology. By exploiting the dynamically varying requirements, the proposal has the potential to achieve a higher average energy efficiency than an application-specific integrated circuit (ASIC) equivalent. However, a penalty in total area consumption exists. The proposed architecture style offers an interesting and a very promising tradeoff in between the traditional ASIC and the other programmable processor solutions. [ABSTRACT FROM PUBLISHER]

For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in 10-nm technology, considering capacitance due to metal pattering and device variability to set target read current for different variants of SRAM architecture to determine technology high-density (HD) SRAM cell. The VT-targeting methodology brings into play the worst case read and write margins available for SRAM cell to determine nominal device VT by tuning the work function of metal gate. Analysis shows that for minimum leakage current, 112 SRAM cell is optimum, whereas for the same area of 0.0546~\mu \mathrm{m}^{\mathrm {2}} with 50% higher leakage, 122 SRAM outperform by 5% and 20% improved read and write margins, respectively. The 122 SRAM as HD cell reduces the cost of the technology by sharing P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) VT mask with the high threshold voltage logic devices, whereas the 112 SRAM device shares only NFET VT mask. The 111 SRAM can achieve target performance at lesser area of 0.048~\mu \mathrmm^\mathrm 2 by compromising read stability, which will result in lower yield. At 64-nm pitch, litho-etch litho-etch (LELE) double-patterned gate impacts device performance and alleviates variability; hence the read margin of SRAM cell should consider an additional 1\sigma \mathrm {\mathbf {rsnm}} margin to retain the same yield in 10-nm-technology era. [ABSTRACT FROM AUTHOR]

Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness. [ABSTRACT FROM AUTHOR]

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

3D integration is being explored as a viable alternative to overcome limitations faced by mobile MPSoC platforms in traditional 2D designs. TSV based interdie connection is the most widely used approach currently. Although, TSV dimensions are scaling down, they still impose a restriction on the interdie connections density and the granularity at which 3D partitioning can be carried out. These limitations will aggravate in future scaled technologies. Alternatives such as Cu-Cu bonding need to be explored to achieve very fine-pitch and high density interdie connections. In this letter, we carry out a system architecture level comparison for a complex MPSoC platform instantiated for wireless PHY processing (WLAN and LTE). We compare 2D and 3D using: 1) TSVs with \mu bump and RDL (F2B); and 2) Cu-Cu bonding (F2F). We show significant gains in 3D as compared to 2D. We also show that F2B and F2F have different system level architecture requirements, and that their impact on parameters at interconnect and system architecture level varies. [ABSTRACT FROM PUBLISHER]

In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution. [ABSTRACT FROM PUBLISHER]

This paper describes the implications of bias temperature instability (BTI)-induced time-dependent threshold voltage distributions on the performance and yield estimation of digital circuits. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The impact of using normally distributed threshold voltages, imposed by state-of-the-art design approaches, is contrasted with our defect-centric approach. Extensive Monte Carlo simulation results are shown for static random access memory cell and ring oscillator structures. [ABSTRACT FROM PUBLISHER]

Modern portable embedded devices require processors that can provide sufficient performance for demanding multimedia and wire- less applications. At the same time they have to be flexible to support a wide range of products and extremely energy efficient to provide a long battery life. Coarse Grained Reconfigurable Architectures (CGRAs) potentially meet these constraints by providing a mix of flexible computational resources and large amounts of programmable interconnect. The vast design space of CGRAs complicates the development of optimized processors. Most effort has been spent on improving the performance. However, the energy cost of the programmable interconnect is becoming more expensive and this cost can no longer be neglected. In this work we present an energy- and performance-aware exploration for the interconnect of a CGRA and show that important tradeoffs can be made for those metrics. This will en- able designers to develop more efficient architectures, tuned to a targeted application domain. [ABSTRACT FROM AUTHOR]

We propose a bilayer graphene (BLG) tunneling field-effect-transistor (TFET) suitable for digital CMOS logic circuits. The ultimate performance limit of this structure is evaluated by solving the quantum transport equations in nonequilibrium Green’s function framework. A bandgap opening is induced in BLG using both vertical electric field and top–bottom asymmetric chemical doping. To overcome the limitations of nonabrupt p-i-n junctions using practical process methods, source/drain regions are created using work-function engineered metal-graphene contacts. We evaluate the performance of BLG-TFET by taking doping gradient due to contact induced doping into account. Our BLG-TFET exhibits a subthreshold slope as low as 35 mV/dec, and I\mathrm{{\scriptstyle ON}}/I\mathrm{{\scriptstyle OFF}} as high as 2910 for a supply voltage of 0.2 V. The proposed BLG-TFET shows promise for ultralow-power applications, particularly in low to medium speed applications. [ABSTRACT FROM AUTHOR]

Direct exchange interaction allows spins to be magnetically ordered. Additionally, it can be an efficient manipulation pathway for low-powered spintronic logic devices. We present a novel logic scheme driven by exchange between two distinct regions in a composite magnetic layer containing a bistable canted magnetization configuration. By applying a magnetic field pulse to the input region, the magnetization state is propagated to the output via spin-to-spin interaction in which the output state is given by the magnetization orientation of the output region. The dependence of this scheme with input field conditions is extensively studied through a wide range of micromagnetic simulations. These results allow different logic operating modes to be extracted from the simulation results, and majority logic is successfully demonstrated.

Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figure-of-merits (FOMs) e.g. delay, and energy-delay product. In this paper, we present guidelines for 2D material based FETs to meet sub-10 nm high performance logic requirements focusing on material requirement, device design, energy-delay optimization for the first time. We show the need for 2D materials with smaller effective mass in the transport direction and anisotropicity to meet the performance requirement for future technology nodes. We present novel device designs with one such 2D material (monolayer black-phosphorus) to keep Moore's alive for the HP logic in sub-5 nm gate length regime. With these device proposals we show that below 5 nm gate lengths 2D electrostatistics arising from gate stack design becomes more of a challenge than direct source-to-drain tunneling for 2D material-based FETs. Therefore, it is challenging to meet both delay and energy-delay requirement in sub-5 nm gate length regime without scaling both supply voltage (V DD ) and effective-oxide-thickness (EOT) below 0.5 V and 0.5 nm respectively.

As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. In this perspective two-dimensional transition metal dichalcogenides, such as MoS2 and WSe2, have recently attracted considerable interest thanks to their electrical properties. Here, we report the first experimental demonstration of a doping-free, polarity-controllable device fabricated on few-layer WSe2. We show how modulation of the Schottky barriers at drain and source by a separate gate, named program gate, can enable the selection of the carriers injected in the channel, and achieved controllable polarity behaviour with ON/OFF current ratios >10(6) for both electrons and holes conduction. Polarity-controlled WSe2 transistors enable the design of compact logic gates, leading to higher computational densities in 2D-flatronics.