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A low-noise amplifier (LNA) design with the operation of concurrent dual-band for Global Navigation Satellite System (GNSS) receivers with single channel is presented in this work. This LNA structure has an inductively degenerated cascode architecture and is pseudo-differential, operating at two frequencies simultaneously (1.2 GHz and 1.57 GHz). Two noise reduction/cancellation techniques, using load capacitor and feedforward path, respectively, are proposed resulting in an excellent improvement in the noise figure (NF). The input matching circuit uses both series and parallel resonant components to enable concurrency. The adopted pseudo-differential structure results in input balun elimination. Inductively degenerated cascode topology provides both input impedance and optimum noise impedance matching. The soundness of the proposed approach has been demonstrated in a 0.18-µm CMOS technology by TSMC. Simulation results show that at 1.2 GHz and 1.57 GHz the LNA achieves −13 dB and −11 dB of input matching, 24.6 dB and 24.7 dB of gain, 1.47 dB and 1.43 dB of NF, respectively. The input-referred 1-dB compression point (IP1dB) is around −16 dBm, while the input-referred third-order intercept point (IIP3) achieves −2.2 dBm at 1.2 GHz and −0.6 dBm at 1.57 GHz. The LNA draws about 13 mA from a 1.8-V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents a lumped scalable model for spiral inductors in a radio frequency (RF) gallium nitride (GaN) technology on silicon substrate. The model has been developed by exploiting electromagnetic (EM) simulations of geometrically scaled spiral inductors. To this aim, the technology substrate, i.e., the metal back-end-of-line along with dielectric and semiconductor layers of the adopted GaN process, has been validated by means of experimental data and then used to define the EM simulator set-up for the spiral inductors. The proposed model adopts a simple π-topology with only seven lumped components and predicts inductor performance in terms of inductance, quality factor (Q-factor) and self-resonance frequency (SRF) for a large range of geometrical parameters of the spiral (i.e., number of turns, metal width, inner diameter). [ABSTRACT FROM AUTHOR]

This paper presents for the first time a quad-core oscillator based on a very compact interstacked transformer that tightly couples the four cores without oscillation mode ambiguity thanks to its strong magnetic coupling factor. As a proof of concept, a 19.125 GHz oscillator for a narrowband 77 GHz radar system was designed in 28 nm fully depleted silicon-on-insulator CMOS technology with a general purpose back-end-of-line. The soundness of the proposed quad-core oscillator topology is demonstrated by comparison with state-of-the-art quad-core solutions, highlighting a significant advantage in terms of area occupation and power consumption. The proposed topology can be profitably exploited in several RF/mm-wave applications, such as radar and wireless communication systems. [ABSTRACT FROM AUTHOR]

This brief gives an overview of recent advancements in CMOS automotive radar sensors, focusing on the most critical circuit design at mm-wave frequencies. Highly scaled CMOS technologies enable very low-power consumption, reduced costs, and higher data processing capacity and integration compared to state-of-the-art SiGe BiCMOS chip-set solutions commonly adopted in commercial products. The very bottleneck is still represented by the radio front-end due to the challenging requirements of long-range radars. Circuit topologies and design tradeoffs are here discussed with reference to critical building blocks of the mm-wave radar front-end, reporting circuit implementations for a 77-GHz long-range radar sensor in a 28-nm fully-depleted silicon-on-insulator CMOS technology. [ABSTRACT FROM AUTHOR]

The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss). Based on this analysis, a wideband lumped model is developed, whose parameters are related to layout and technological data through closed-form expressions. Model accuracy is demonstrated by comparing simulated and measured S-parameters, coil inductance, magnetic coupling coefficient, and maximum available gain of several transformers with scaled layout geometry. The self-resonance frequency is also employed as a figure-of-merit to demonstrate model accuracy at very high frequency. Index Terms--Integrated transformers, layout scaling, lumped modeling, on-wafer measurements, RF integrated circuits (ICs).

In this paper, a design methodology for the optimization of transformer-loaded RF circuits is presented. The optimization procedure is based on a novel figure of merit for the integrated transformer (namely the transformer characteristic resistance), which was introduced to quantify its performance when operated as a tuned load. Using the proposed approach, a highly linear up-converter for 5-GHz wireless LAN applications was implemented in a 45-GHz-[f.sub.T] SiGe HBT technology. The circuit achieved an output l-dB compression point of 4.5 dBm and a power gain of 18 dB, while drawing only 34 mA from a 3-V power supply. Index Terms--Figure of merit, integrated transformer, SiGe HBT, transformer characteristic resistance (TCR), tuned load, up-converter, wireless LAN (WLAN).

A lumped scalable model for spiral inductors in silicon bipolar technology has been developed. The effect of three different cross sections on inductor performance was first investigated by comparing experimental measurements. Using both the results of this analysis and three-dimensional electromagnetic simulation guidelines, several circular inductors were integrated on a radial patterned ground shield for model validation purposes. The model employs a novel equation for series resistance with only one fitting parameter extracted from experimental measurements. All other model elements were related to technological and geometrical data by using rigorous analytical equations. The model was validated using one- and two-port measured performance parameters of 45 integrated inductors, and excellent agreement was found for all considered geometries up to frequencies well above self-resonance. Index Terms--Bipolar technology, integrated inductors, lumped model, patterned ground shield.

This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs. [ABSTRACT FROM AUTHOR]

This paper presents a 77-GHz automotive radar receiver in a 28-nm fully depleted silicon-on-insulator CMOS technology. It exploits a mixer-first direct-conversion architecture to trade-off noise and linearity performance. The receiver is composed of a 77-GHz downconverter, a variable-gain amplifier, and a switched-capacitor low-pass filter. It adopts an effective and robust approach for leakage suppression due to the TX to RX crosstalk, which overcomes both gain and linearity limitations. The receiver draws an overall quiescent current as low as 27 mA from a 1-V supply voltage and provides an overall gain up to 75 dB with a noise figure of 8.2 dB. Despite the low supply voltage, an excellent blocker immunity of −9.5 dBm is achieved along with an output 1-dB compression point as high as −1.5 dBV. [ABSTRACT FROM AUTHOR]

This article presents a $W$ -band power amplifier (PA) for automotive radar applications. It was designed in a 28-nm fully depleted silicon-on-insulator CMOS technology with a transition frequency of around 270 GHz and a standard back-end-of-line. The circuit adopts a pseudo-differential topology with coupling transformers, which allow both compact matching networks and layout-optimized interstage interconnections. The power stage exploits a transformer-based folded-cascode structure that is very suitable for low-voltage mm-wave power applications. The PA is able to deliver a saturated output power as high as 13.5 dBm at 77 GHz with a power-added efficiency of 14.5%, while using a power supply as low as 1 V. The linear power gain is 26.5 dB and the current consumption is 150 mA. The PA occupies a core die size of $700\,\,\mu \text{m}\,\,\times 200\,\,\mu \text{m}$. [ABSTRACT FROM AUTHOR]

In this paper, the effect of a metal patterned ground shield (PGS) on the performance of monolithic inductors is investigated. To this aim, three spiral inductors integrated in a 28‐nm fully depleted (FD) silicon‐on‐insulator (SOI) CMOS technology are analyzed by means of a 3‐D FEM‐based commercial software. The inductors have been designed at different operating frequencies in the RF and mm‐wave ranges to better explore the effect of the PGS. Extensive analysis revealed that the shield is able to improve the quality factor (Q‐factor) only of the inductor operated at the lowest frequency (ie, K‐band). On the contrary, it has a detrimental effect on the Q‐factor of the inductors working at higher frequencies. This is mainly due to induced losses in the PGS itself, which are so high to frustrate the substrate loss reduction. This result gives a different perspective to the adoption of the PGS for CMOS integrated inductors, which is largely recommended to improve inductor performance in the current state of the art. [ABSTRACT FROM AUTHOR]

An effective codesign approach for harvesting systems is described in this article, which is based on a CMOS differential-drive rectifier and an inductively coupled loop (ICL) antenna. The proposed approach acts on both the rectifier and the antenna and aims at optimizing the system performance in terms of efficiency and input sensitivity for a given load specification. Moreover, a rectifier solution is also proposed to enhance the circuit performance by properly driving the transistor bulks without additional components. An RF harvesting system operating at 868 MHz was implemented, which is made up of an ICL antenna on FR-4 substrate and a rectifier fabricated in the 0.13- $\mu \text{m}$ CMOS technology. Measurements in the anechoic chamber show an overall efficiency performance of 34% with an RF input power as low as −21.5 dBm while considering 2.4 V and 1 $\mu \text{A}$ as load specifications. [ABSTRACT FROM AUTHOR]

This brief presents a variable-gain amplifier (VGA) for automotive radar applications integrated in a 28-nm fully depleted (FD) silicon-on-insulator (SOI) CMOS technology. The amplifier operates at a power supply as low as 1 V and guarantees 30-dB linear-in-dB gain variation with a 3-dB step. The back-gate of the MOS transistors has been exploited to implement a back-gate control-based offset cancelation loop, thus avoiding the use of inter-stage coupling capacitors that introduce frequency limitations due to parasitic capacitances. The VGA exhibits a bandwidth from 100 kHz to 20 MHz, which is compliant with typical frequency-modulated continuous wave (FMCW) radars. It also guarantees a 1-dB compression point (${P} _{\mathrm{ 1dB}}$) better than −36 dBm and an input-referred noise (IRN) of 12.5 nV/ $\surd $ Hz and 7 nV/ $\surd $ Hz at 1 MHz and 10 MHz, respectively, with a power consumption as low as 1.7 mW. [ABSTRACT FROM AUTHOR]

This brief demonstrates a fully contactless wafer-level testing based on UHF radio identification (RFID) technology enriched by high-quality on-chip antenna. The antenna, which uses exactly the same tag IC area (i.e., 0.45 mm2), exploits a low-cost post-process consisting of a thick dielectric layer and a copper metal, thus significantly improving the quality factor with respect to a standard CMOS implementation. Contactless wafer-level testing of a tag array is performed by simultaneous inductive coupling with a customized near-field reader. With a 27-dBm standard UHF RFID reader, a reading range up to 2.5 mm is demonstrated at 865 MHz. Anti-collision algorithm and memorized x–y device coordinates allow IC identification on the wafer under test to be achieved. Thanks to its cost-effectiveness, the proposed approach can be easily extended to general purpose IC contactless testing. [ABSTRACT FROM AUTHOR]

This paper presents the design and experimental characterization of a power transfer system performing a dc–dc conversion with on-chip galvanic isolation. The converter is operated in the VHF band, which enables fully integration of all the required components in silicon technology. It consists of only two silicon dice, i.e., a power oscillator with an on-chip isolation transformer and a full-bridge rectifier, which are fabricated in 0.35–µm BCD and 0.13–µm CMOS technology, respectively. A thick SiO2 layer was used, which guarantees galvanic isolation between the transformer windings. A co-design procedure for the system building blocks is proposed, which aims at optimizing the dc–dc converter performance in terms of power efficiency at a given power density. Thanks to the adopted approach, a maximum output power up to 980 mW is demonstrated with a power efficiency of 29.6%. This paper outperforms previously reported integrated inductive step-up converters in terms of power per silicon area (up to 105 mW/mm2), while providing on-chip galvanic isolation without any discrete devices or post-processing steps. [ABSTRACT FROM PUBLISHER]

This brief presents a fully integrated dc–dc converter consisting of only two CMOS chips, which are a power oscillator with an integrated transformer and a full-bridge rectifier. A thick inter-metal oxide layer guarantees a galvanic isolation rating as high as 5 kV. A current-reuse hybrid-coupled oscillator is proposed, which is based on a three-winding tapped isolation transformer and improves both output power and silicon area occupation with respect to previous works. The converter is operated at 5-V power supply and is able to deliver up to 300-mW dc power at 10-V output voltage while exhibiting a power density and a power efficiency of 36 mW/mm2 and 24%, respectively. [ABSTRACT FROM PUBLISHER]

A high-performance ultrahigh-frequency amplitude shift keying (ASK) detector for low-power radio-frequency (RF) receivers is proposed. The circuit is based on a high-gain common-source topology with a feedback loop that provides adaptive biasing. Hence, high sensitivity and rail-to-rail input operation are achieved along with low power consumption. The detector was implemented in a standard 130-nm complementary metal–oxide–semiconductor technology. Sensitivity measurements demonstrate correct detection of a 2-Mb/s ASK-modulated 915-MHz signal with a peak level and a modulation index of around 200 mV and 5%, respectively, which means an envelope signal amplitude of as low as 5 mV. The circuit draws less than 3.4\ \mu\mboxA from a 1.2-V power supply while operating with rail-to-rail RF variations and modulation indexes from 5% to 100%. This performance makes the detector suitable for batteryless systems with RF energy harvesting. [ABSTRACT FROM AUTHOR]

This paper presents the design of on-chip micro-antennas for package-scale galvanic isolators based on RF planar coupling. A step-by-step design procedure is proposed, which aims at the maximization of the weak electromagnetic coupling between the RX and TX antennas integrated on side-by-side co-packaged chips to enable both high isolation rating and common-mode transient immunity thanks to the high dielectric strength and low capacitive parasitics of a molding compound-based galvanic barrier, respectively. Micro-antenna design guidelines are drawn, highlighting the main relationship between coil coupling performance and their layout parameters, which are often in contrast with respect to traditional integrated inductor ones. [ABSTRACT FROM AUTHOR]

This article presents a 24/77-GHz transmitter chipset for automotive radar sensors implemented in a 160/175-GHz fT/fmax SiGe BiCMOS technology. The chipset adopts a dual-band architecture consisting of a 24-GHz section for ultra-wideband short-range radar operation, which is also exploited to drive the 77-GHz long-range radar transmitter front-end. The proposed design adopts a single 24-GHz frequency synthesizer to implement both radar operation modes. The transmitter chipset is able to deliver a maximum output power of 3 dBm and 12 dBm at 24 GHz and 77 GHz, respectively. The 24-GHz transmitter demonstrates to operate with pulse widths of 0.5 ns and 1 ns in compliance with the transmission mask designed by ETSI. The 77-GHz transmitter exhibits a power gain of 20 dB, an output power of 12 dBm, and an output referred 1-dB compression point of 9.5 dBm, while drawing 155 mA from a 2.5-V supply voltage. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:782-786, 2013; View this article online at wileyonlinelibrary.com. DOI: 10.1002/mop.27425 [ABSTRACT FROM AUTHOR]

This paper presents a Colpitts-based voltage-controlled oscillator (VCO) for W-band radar applications. In the proposed circuit, the oscillation signal is directly drawn from the switching transistor bases by means of the primary winding of a transformer tank, while the secondary winding drives the output buffer. This solution improves both tuning range and oscillation swing with respect to traditional millimeter-wave VCO topologies without increasing power supply. The oscillator is implemented in a 0.13-\mu\ m SiGe BiCMOS technology, along with high-frequency dividers to enable low-frequency testing. The VCO exhibits a phase noise of -\99.3 dBc/Hz at 1-MHz offset from an oscillation frequency of 76 GHz and a tuning range of 4.9% with a consumption of 65 mW at 2.5-V power supply. The VCO is also used to drive a two-stage power amplifier in a fully integrated W-band transmitter that is able to deliver an overall output power as high as 15 dBm at 76 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a pseudodifferential power amplifier for 77-GHz automotive radar. The circuit is fabricated in a SiGe HBT BiCMOS technology featuring bipolar transistors with fT/f\max of 230/280 GHz. The amplifier adopts a transformer-coupling current-reuse approach to improve both gain and efficiency. An interstacked transformer is also profitably adopted to reduce output losses due to the differential-to-single-ended conversion. The amplifier exhibits a saturated power, a peak power-added efficiency, and a gain of 14.5 dBm, 9%, and 25 dB, respectively, thus achieving a first-rate figure-of-merit as high as 4755. [ABSTRACT FROM PUBLISHER]

This paper presents a 15-dBm power amplifier for 77-GHz automotive radar applications, which is fabricated in a 0.13-\mu\ m SiGe:C BiCMOS process featuring bipolar transistors with f T / f\max of 230/280 GHz. The circuit consists of a two-stage pseudodifferential cascode with fully integrated input/output matching networks. State-of-art performance is achieved with the proposed design algorithm and layout optimization. The amplifier demonstrates a figure-of-merit of 2500 achieving a 22.5-dB power gain and a power-added efficiency of 7.5% at 77 GHz, while drawing 130 mA from a 2.5-V voltage supply. [ABSTRACT FROM AUTHOR]

This letter presents a 77-GHz power amplifier implemented in a SiGe BiCMOS technology featuring bipolar transistors with 160/175-GHz f/ f. The circuit adopts a two stage differential topology with integrated input/output matching networks. The amplifier performance is considerably improved thanks to proper input/output LC resonant networks, which cancel out the ground-plane parasitic effect. Matching networks use stacked transformers for impedance matching, differential-to-single-ended conversion, and electro-static discharge protection. The circuit achieves a power gain of 18.5 dB, a maximum output power of 11.6 dBm, with 4.2% power-added efficiency, and an output 1-dB compression point of 9.3 dBm. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1413-1416, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25972 [ABSTRACT FROM AUTHOR]

In this letter, a novel structure for mm-wave integrated transformers is presented. The proposed transformers, namely, interstacked, exploit mixed interleaved/stacked coils, which allow increasing the magnetic coupling with respect to stacked devices, providing full geometrical/electrical symmetry. An extensive comparison between interstacked and conventional structures demonstrates the benefits of the proposed configuration in terms of the most significant figures of merit for integrated transformers. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 2160–2163, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25385 [ABSTRACT FROM AUTHOR]

A lumped scalable model of silicon integrated inductors for RF IC design is presented. It was validated up to 20 GHz using measured performance parameters of more than 70 single-ended and differentially driven spirals covering 0.2- to 8.3 nH inductance values. Excellent accuracy, full geometrical scalability, compactness and high capability for implementation in circuit simulators promote the proposed model as a reliable time-saving design tool. Two circuital example, i.e., 5-GHz down-converter and 10-GHz VCO, are also presented to demonstrate its use in practical cases. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009. [ABSTRACT FROM AUTHOR]

This paper reviews state-of-the-art architectures for galvanically isolated DC-DC converters with data transmission for low-power applications. Such applications do not have stringent requirements, in terms of power efficiency, but ask for very compact, highly integrated implementations. To this aim, architecture simplicity is crucial, especially when data transmission and/or output power regulation are required. Since the bottleneck of galvanically isolated systems is the isolation device (i.e., typically a stacked thick oxide or polyimide transformer), the reduction of the number of isolated links, while preserving both power and data functionalities, is the more effective strategy to increase the level of integration, reduce the form factor, and have a lower cost per channel. Specifically, this review compares the pros and cons of different architectures that address this challenge differently from traditional solutions. [ABSTRACT FROM AUTHOR]

In this article, a 24-GHz low-noise amplifier for vehicular short-range radar applications is presented. The circuit, fabricated in a 0.13-μm SiGe:C BiCMOS process, consists of three fully differential transformer-loaded cascode stages, including a gain-control functionality. The amplifier exhibits a 35-dB power gain and a noise figure of 3.4 dB, providing a reverse isolation better than -60 dB. By using a 1-bit gain control, the LNA achieves an input 1-dB compression point of -12 dBm. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2013–2016, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23584 [ABSTRACT FROM AUTHOR]

A 5-GHz transmitter front-end for 802.11a and HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-fT silicon bipolar technology. The transmitter includes a digitally controlled linear-in-dB variable-gain up-converter and a three-stage linear power amplifier. At a 3-V supply voltage, the front-end exhibits a 23.5-dBm output 1-dB compression point, 35-dB maximum power gain, and 30-dB dynamic range. The dB-linear gain error is lower than ±0.8 dB. The transmitter is able to comply with the stringent error vector magnitude requirement of the standard up to a 19-dBm output power level. [ABSTRACT FROM AUTHOR]

This paper presents a switched capacitor low-pass filter in a 28-nm fully depleted silicon on insulator CMOS technology for 77-GHz automotive radar applications. It is operated at a power supply as low as 1 V and guarantees 5-dB in-band voltage gain while providing out-of-band attenuation higher than 36 dB and a programmable passband up to 30 MHz. A double sampling technique is adopted, which allows high operating frequency to be achieved while saving power. Moreover, low-voltage biasing and common-mode feedback circuits are exploited to guarantee an almost rail-to-rail output voltage swing. The proposed filter provides an output 1-dB compression point as high as 8.7 dBm with a power consumption of 9 mW. To the authors' knowledge, this is the first SC-based implementation of a low pass filter for automotive radar applications. [ABSTRACT FROM AUTHOR]

This paper reviews state-of-the-art approaches for galvanically isolated DC-DC converters based on radio frequency (RF) micro-transformer coupling. Isolation technology, integration level and fabrication issues are analyzed to highlight the pros and cons of fully integrated (i.e., two chips) and multichip systems-in-package (SiP) implementations. Specifically, two different basic isolation technologies are compared, which exploit thick-oxide integrated and polyimide standalone transformers, respectively. To this aim, previously available results achieved on a fully integrated isolation technology (i.e., thick-oxide integrated transformer) are compared with the experimental performance of a DC-DC converter for 20-V gate driver applications, specifically designed and implemented by exploiting a stand-alone polyimide transformer. The comparison highlights that similar performance in terms of power efficiency can be achieved at lower output power levels (i.e., about 200 mW), while the fully integrated approach is more effective at higher power levels with a better power density. On the other hand, the stand-alone polyimide transformer approach allows higher technology flexibility for the active circuitry while being less expensive and suitable for reinforced isolation. [ABSTRACT FROM AUTHOR]

Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power to be reduced. The DCO has been implemented in 110 nm CMOS technology. It generates output signal in frequency range from 1.52 GHz to 1.6 GHz and consumes 1.1 mW from 1.5 V supply voltage. The measured phase noise equals −116 dBc/Hz at 1 MHz offset from 1.575 GHz output signal. [ABSTRACT FROM AUTHOR]

A 17.8–34.8 GHz (64.6%) locking range current-reuse injection-locked frequency multiplier (CR-ILFM) with dual injection technique is presented in this paper. A dual injection technique is applied to generate differential signal and increase the power of the second-order harmonic component. The CR core is proposed to reduce the power consumption and compatibility with NMOS and PMOS injectors. The inductor-capacitor (LC) tank of the proposed CR-ILFM is designed with a fourth-order resonator using a transformer with distributed inductor to extend the locking range. The self-oscillated frequency of the proposed CR-ILFM is 23.82 GHz. The output frequency locking range is 17.8–34.8 GHz (64.6%) at a 0-dBm injection power without any additional control including supply voltage, varactor, and capacitor bank. The power consumption of the proposed CR-ILFM is 7.48 mW from a 1-V supply voltage and the die size is 0.75 mm × 0.45 mm. The CR-ILFM is implemented in a 65-nm CMOS technology. [ABSTRACT FROM AUTHOR]

A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge pump architecture consists of an operational power amplifier (OPA), switches, three D flip-flops (DFFs) and passive devices. A phase error compensation technique is introduced in the charge pump to reduce the locking time. The current mismatch, which is mainly due to the leakage current, is below 1% for a large output voltage headroom of 84% of the supply voltage. An 18.4% reduction in the settling time is realized by the proposed design. [ABSTRACT FROM AUTHOR]

Millimeter wave, especially the high frequency millimeter wave near 100 GHz, is one of the key spectrum resources for the sixth generation (6G) mobile communication, which can be used for precise positioning, imaging and large capacity data transmission. Therefore, high frequency millimeter wave channel sounding is the first step to better understand 6G signal propagation. Because indoor wireless deployment is critical to 6G and different scenes classification can make future radio network optimization easy, we built a 6G indoor millimeter wave channel sounding system using just commercial instruments based on time-domain correlation method. Taking transmission and reception of a typical 93 GHz millimeter wave signal in the W-band as an example, four indoor millimeter wave communication scenes were modeled. Furthermore, we proposed a data-driven supervised machine learning method to extract fingerprint features from different scenes. Then we trained the scene classification model based on these features. Baseband data from receiver was transformed to channel Power Delay Profile (PDP), and then six fingerprint features were extracted for each scene. The decision tree, Support Vector Machine (SVM) and the optimal bagging channel scene classification algorithms were used to train machine learning model, with test accuracies of 94.3%, 86.4% and 96.5% respectively. The results show that the channel fingerprint classification model trained by machine learning method is effective. This method can be used in 6G channel sounding and scene classification to THz in the future. [ABSTRACT FROM AUTHOR]

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation. [ABSTRACT FROM AUTHOR]

In this paper, a 24 GHz direct conversion receiver (DCR) for frequency-modulated continuous-wave (FMCW) ranging radar based on low flicker noise mixer in 90 nm silicon-on-insulator (SOI) CMOS technology is presented. A low-noise and low-power low-noise-amplifier (LNA) adopting simultaneous noise and input matching (SNIM) method is designed. Neutralized technology and boost inductor are introduced to improve performance. The measurement results of standalone LNA show that the peak gain is 17.2 dB at 23.8 GHz and the −3 dB bandwidth is around 2.2 GHz from 22.8 GHz to 25 GHz. The LNA achieves an average 3 dB NF within the 24 GHz band. A current-bleeding mixer is used to lower noise and the factors influencing flicker noise have been discussed. Proper element values and local oscillator (LO) power have been chosen to make the mixer low-noise. Measurement results illustrate that the receiver exhibits 20.3 dB peak gain, 7 dB SSB noise figure (NF) and −22 dBm IP1dB. Flicker noise of the mixer and the receiver are measured respectively and the noise knee-point of receiver is observed 60 kHz. The receiver consumes only 16 mW with chip area of 0.65 mm2 including pads. The results demonstrate that the proposed receiver can be a promising candidate for FMCW ranging radar. [ABSTRACT FROM AUTHOR]

The Tianwen-1 of China is expected to land and explore on the planet Mars in May 2021, carrying a Mars Rover-mounted Subsurface Penetrating Radar (RoSPR) system. A VHF band ultra-wideband (UWB) monopole antenna integrated on the Mars Rover, and described in this paper, has been designed for the subsurface exploration of Mars tens of meters deep. Conventional antenna design methods usually prove difficult in taking into account several key parameters such as miniaturization, broadband characteristics and radiation efficiency. Moreover, there is almost no special research on the reliability of antennas. For this purpose, a miniaturized air-coupled monopole antenna integrated with the Mars Rover has been designed. The overall length of the antenna is 0.13 λ at the lowest operating frequency. In addition, the classical Wu–King profile is improved, which not only satisfies the operating bandwidth of the antenna, but also increases the gain by 3–4 dB. In the design, the innovative application of planar embedded resistance greatly enhances the reliability of the antenna and thereby ensures that the antenna can work on Mars for a long term. This is the first application of this antenna design method in the aerospace field. Because it is difficult to test the low-frequency antenna accurately, a 1:4 scale model of the antenna and Rover is fabricated to equivalently measure the radiation characteristics of the antenna. Furthermore, the performance and practicability of the antenna and radar system are verified on the glacier. [ABSTRACT FROM AUTHOR]

In this article, we tackle the question of evaluating the dimension of the data space in the phase retrieval problem. With the aim to achieve this task, we first exploit the lifting technique to recast the quadratic model as a linear one. After that, we evaluate analytically the singular values of the lifting operator, and we quantify the dimension of the data space by counting the number of "significant" singular values. In the last part of the article, we show some numerical results in order to corroborate our analytical prediction on the singular values' behavior of the lifting operator and on the dimension of the data space. The analysis is performed for a 2D scalar geometry consisting of an electric current strip whose square magnitude of the radiated field is observed on multiple arcs of circumference in Fresnel zone. [ABSTRACT FROM AUTHOR]

This paper presents an extensive comparison of two 28-nm CMOS technologies, i.e., standard and mm-wave-optimized (i.e., thick metals and intermetal oxides) back-end-of-line (BEOL). The proposed comparison is carried out at both component and circuit level by means of a quantitative analysis of the actual performance improvements due to the adoption of a mm-wave-optimized BEOL. To this end, stand-alone transformer performance is first evaluated and then a complete mm-wave macroblock is investigated. A 77-GHz down-converter for frequency modulated continuous wave (FMCW) long-range/medium range (LR/MR) radar applications is exploited as a testbench. For the first time, it is demonstrated that thicker metals and intermetal oxides do not guarantee significant improvements at mm-wave frequencies and a standard (low-cost) BEOL is competitive in comparison with more complex (expensive) ones. [ABSTRACT FROM AUTHOR]

This paper exploits an effective approach to overcome the breakdown limitations of traditional galvanic isolators based on chip-scale isolation barriers, thus achieving a very high isolation rating (i.e., compliant with the reinforced isolation requirements). Such an approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips. Standard packaging along with proper assembling techniques can be profitably used to go beyond 20-kV surge voltage without using expensive or exotic isolation components. As a proof of concept, a bidirectional data transfer system based on RF planar coupling able to withstand an isolation rating as high as 25 kV has been designed in a low-cost standard 0.35-µm CMOS technology. Experimental measurements demonstrated a maximum data rate of 40 Mbit/s using a carrier frequency of about 1 GHz. The adopted approach also guarantees a common mode transient immunity (CMTI) of 250 kV/µs, which is a first-rate performance in view of next generation galvanic isolators for wide-bandgap power semiconductor devices, such as gallium nitride high-electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs. [ABSTRACT FROM AUTHOR]