Search

As the use of integrated radar sensors is becoming more common not only in traditional military and automotive but also in medical and industrial applications, the requirements for a radar sensor diversify. For some applications, bandwidth is critical, primarily defining the capability to distinguish targets. Mostly, varying the frequency of an oscillator in the mmWave and THz range is realized by tuning a dc voltage to a variable capacitance. While this is typical for integrated transceivers in silicon-germanium (SiGe) technology, the tunability of a single voltage-controlled oscillator (VCO) limits the bandwidth. This work presents an approach to overcome this limitation by using two simultaneously tuned VCOs combined with a mixer. The oscillators are tuned simultaneously in opposing directions, resulting in an ultra-wideband signal at the mixer's output. The resulting tuning range is the addition of both of the VCOs' respective tuning ranges. The transceiver is realized using the B11HFC SiGe technology, featuring VCOs at center frequencies of 52 GHz and 108 GHz, respectively. The transceivers' output with a center frequency of 111 GHz is continuously tunable over a range of 73.6 GHz (66%). Furthermore, the phase noise contributions from both VCOs along a receiver test are presented.

The increasing dominance of inverter-based resources (IBRs) in power generation leads to significantly faster frequency dynamics in modern power systems. Therefore, the secondary control within the classical hierarchical structure must operate significantly faster. However, high communication burdens are inherent to centralized implementations of secondary control. This paper proposes a faster, distributed model predictive control (MPC) scheme for secondary frequency control of inverter-based power systems. The controller predicts the IBRs’ local frequency dynamics by considering the impact of the primary control of nearby IBRs. To obtain an optimal model-predictive control problem consisting of distributable subproblems, we introduce a novel trimming procedure to the frequency divider concept, an analytical formulation that estimates the local frequency at system buses. These subproblems have a tunable degree of mutual coupling. The presented distributed MPC achieves fast, error-free frequency regulation in the presence of abrupt load changes while also being robust to communication losses of participating IBRs. By design, the distributed control relies on a sparse neighbor-to-neighbor communication structure and uses local MPC problems that do not scale in complexity with system size. Numerical simulations of the IEEE 39-bus system and an extended CIGRE medium voltage power system demonstrate the fast performance of the proposed distributed MPC scheme for secondary frequency control.

With the large-scale grid connection of new energy, the frequency stability of power system is facing great challenges. Due to the larger inertia of thermal power units, the potential of primary frequency modulation can be deeply explored. The feedback signal of primary frequency modulation system was decomposed by frequency division device to obtain signals of different frequency bands, and appropriate frequency dead band interval was set for signals of different frequency bands, so that the thermal power units can be controlled and adjusted by frequency division, thus improving and improving the primary frequency modulation performance of thermal power units. In order to study the influence of unit frequency division control on the primary frequency modulation capability of the system, the primary frequency modulation model of the power system was built in the simulation software. The simulation results under different working conditions show that the frequency division control can effectively improve the system frequency modulation performance. In addition, the coordinated control system model of the boiler was also introduced. Through the analysis of the main steam pressure of the boiler, it is verified that this strategy not only strengthens the primary frequency regulation ability of the unit, but also improves the stability of the unit. [ABSTRACT FROM AUTHOR]

The paper presents a non-inductive broadband energy-efficient active balun based on a differential pair, intended for use in the input block of a frequency divider for 22nm technology. The developed device can operate in the frequency range from 2 GHz to 60 GHz with a supply voltage of 0.8 V and consume less than 3 mA. The special feature of the developed active balun is that it does not have inductive components, which reduces its size and signal loss. Amplitude of the output signal in working frequency range is from 450 mV to 200 mV. Signal gain in the range from 1-60 GHz varies from -10 dB up to 4 dB. The size of the circuit on the chip is 48x34 um. The device allows you to receive a stable signal at high data transfer rates and provides energy savings due to low current consumption.

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz. [ABSTRACT FROM AUTHOR]

This paper proposes a temperature sensor based on temperature-frequency conversion using 180 nm CMOS technology. The temperature sensor consists of a proportional-to-absolute temperature (PTAT) current generating circuit, a relaxation oscillator with oscillation frequency proportional to temperature (OSC-PTAT), a relaxation oscillator with oscillation frequency independent of temperature (OSC-CON), and a divider circuit cascaded with D flip-flops. Using BJT as the temperature sensing module, the sensor has the advantages of high accuracy and high resolution. An oscillator that uses PTAT current to charge and discharge capacitors to achieve oscillation, and utilizes voltage average feedback (VAF) to enhance the frequency stability of the oscillator is tested. Through the dual temperature sensing process with the same structure, the influence of variables such as power supply voltage, device, and process deviation can be reduced to a certain extent. The temperature sensor in this paper was implemented and tested with a temperature measurement range of 0–100 °C, an inaccuracy of +0.65 °C/−0.49 °C after two-point calibration, a resolution of 0.003 °C, a resolution Figure of Merit (FOM) of 6.7 pJ/K2, an area of 0.059 mm2, and a power consumption of 32.9 μW. [ABSTRACT FROM AUTHOR]

In recent years, sound source localization, as a passive localization technique with higher safety and convenience compared with other localization techniques such as active emission of electromagnetic waves, has received more and more attention in academia. This paper researches and improves the far-field sound source localization algorithm based on the generalized cross-correlation method (GCC) Time Difference of Arrival (TDOA) estimation algorithm and completes the design and implementation of the microphone array sound source localization system. This paper adds a frequency divider to the traditional generalized correlation time delay estimation algorithm for pre-processing, sampling, and localization of sound source acoustic waves and adopts a low-cost microphone array deployment scheme as far as possible to improve the flexibility and practicality of the localization system; at the same time, the "Minimum Sphere Method" is used at the back end of the algorithm to classify the localization coordinates at different frequencies and, finally, output reasonable sound source coordinates. In the back-end of the algorithm, the "Minimum Sphere Method" is used to classify the localization coordinates at different frequencies and, finally, output the reasonable sound source coordinates. The experimental results show that the sound source localization system designed in this paper has good performance in terms of localization accuracy and cost-effectiveness and overcomes the failure of the generalized mutual correlation algorithm in the original application of high noise environment and multi-source environment localization. [ABSTRACT FROM AUTHOR]

Low-phase noise and wideband phased-locked loops (PLLs) are crucial for high-data rate communication and imaging systems. Sub-millimeter-wave (sub-mm-wave) PLLs typically exhibit poor performance in terms of noise and bandwidth due to higher device parasitic capacitances, among other reasons. In this regard, a low-phase-noise, wideband, integer-N, type-II phase-locked loop was implemented in the 22 nm FD-SOI CMOS process. The proposed wideband linear differential tuning I/Q voltage-controlled oscillator (VCO) achieves an overall frequency range of 157.5–167.5 GHz with 8 GHz linear tuning and a phase noise of −113 dBc/Hz @ 100 KHz. Moreover, the fabricated PLL produces a phase noise less than −103 dBc/Hz @ 1 KHz and −128 dBc/Hz @ 100 KHz, corresponding to the lowest phase noise generated by a sub-millimeter-wave PLL to date. The measured RF output saturated power and DC power consumption of the PLL are 2 dBm and 120.75 mW, respectively, whereas the fabricated chip comprising a power amplifier and an integrated antenna occupies an area of 1.25 × 0.9 mm2. [ABSTRACT FROM AUTHOR]

This work presents the Complex Frequency Divider Formula (CFDF), an explicit equation for the complex frequencies (CFs) of the voltage of every bus of a power system in terms of a linear combination of the CFs of the currents injected by the devices connected to the network. The coefficients of this linear combination depend on the topology of the system, voltages and currents. The CFDF carries valuable information on the impact of every device on the dynamic of the voltage and frequency of any particular bus of the system. The formulation is exact, as it does not require any simplification of the dynamic model of the system. The CFDF is implemented in two benchmark systems to show its potential in static and dynamic analysis in different scenarios. Finally, relevant notes on the applications of the proposed formula are outlined. • Generalization of the frequency divider formula. • Equation for the complex frequency of bus voltages in terms of devices dynamics. • Analytical solution of the proposed formula in terms of existing variables. • Specific expressions for the complex frequency of the current of common devices. [ABSTRACT FROM AUTHOR]

The letter describes a novel, continuum-based approach, to capture the evolution of electromechanical dynamics in a power network following a disturbance. Such approach is based on the frequency divider formula (FDF), which was recently proposed by the third author. A key point in obtaining the frequency divider formula (FDF) as a consequence of a continuum, is to show that the spatial rate of change, at a given time, of the frequency along a lossless line is constant. The proposed derivation is then compared with the electromechanical wave approach (EWA), which has been discussed in the literature in a variety of hues and is aimed at modeling the propagation in a power system of frequency oscillations following a disturbance. The discussion illustrates similarities and differences between FDF and electromechanical wave approach (EWA). [ABSTRACT FROM AUTHOR]

Herein, a systematic approach for designing loop topology circuits, such as ring oscillators (ROs), latches, and frequency dividers, is proposed. The design flow is devised to implement the target circuits with minimum power dissipation at the desired operating frequency. Using a modified $C/I_{\text {DS}}$ methodology, several design examples in different technology nodes are provided showing less than ±5% error in the estimated circuit performance, confirmed by experimental data in 0.18 ${\mu }\text{m}$ technology. A standardized procedure has been developed to extract fundamental device characteristics for different technology nodes, which are subsequently fed into an optimizer script. Examples for implementing current-steering ROs and frequency dividers will be provided. The proposed approach can be employed to custom design high-speed sequential logic circuits, as well as voltage-controlled oscillators (VCOs), digitally controlled oscillators (DCOs), and frequency dividers for applications such as clock generators, sequential circuits, and serial data transceivers in modern integrated systems. [ABSTRACT FROM AUTHOR]

Three tuning-less ultra-wide locking range (LR) transformer-based millimeter-wave (mm-wave) injection-locked frequency dividers (ILFDs) are presented. An eighth-order transformer-based resonator is proposed to improve the LR without an extra tuning mechanism or chip area. The operation principle of high-order transformer-based resonator in ILFDs based on the impedance diagram is analyzed. By comparing different high-order transformer-based resonators, the proposed resonator is the best option for the ultra-wide LR ILFD design. Also, the design considerations and tradeoffs of the implemented resonator are discussed. Furthermore, an inductive gain peaking technique is adopted to ensure start-up conditions and achieve low power consumption. Three ILFDs are designed and fabricated in 40-nm CMOS technology. The first chip exhibits a best-in-class LR of 104.5% from 28.8 to 91.9 GHz while consuming 5.8 mW with a 0.9-V power supply. The second chip achieves the best figure of merit (FoM) up to 26.6 GHz/mW and 79.6% from 31- to 72-GHz LR with a 0.5-V power supply. The third chip obtains an LR of 108.9% from 20 to 67.8 GHz while consuming 4.9 mW with a 0.9-V power supply. Furthermore, 6-dB phase noise differences of the three chips are achieved, which is close to the theoretical value. [ABSTRACT FROM AUTHOR]

This paper presents a 9.4 ~ 20.6 GHz low‐noise phase‐locked loop (PLL) in 0.13‐μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four‐core Colpitts voltage‐controlled oscillato array with 2‐bit switched capacitors and 2‐bit‐control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection‐locking behavior model of the dual‐mode prescaler is quantitatively analyzed, which is proved to be effective through the tape‐out. The fabricated proposed PLL achieves the average phase noise of −100.5 dBc/Hz at 1‐MHz offset, wideband locking range of 74.7% and the high FOMT of 183.3 dBc/Hz. It occupies an area of 8.4 mm2, and its maximum power consumption is 319.7 mW. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a unified nonlinear injection locking model of a large class of 1:2 frequency dividers. The model is valid for two-stage dividers, injected with two-phase or single-phase current or voltage sources. We show that this class of dividers can be rigorously analyzed using the theory of planar nonlinear dynamical systems. We provide accurate compact expressions for the locking range, amplitude, frequency and phase noise. The formulas are validated for two types of frequency dividers using simulations. [ABSTRACT FROM AUTHOR]

This brief presents the modeling and design of a static current-mode logic, divide-by-2 frequency divider for mm-wave frequency synthesis. An optimized design procedure based on the $RC$ delay model and insights into the nonlinear mixing conversion gain of the injection-locking model are presented and leveraged towards the design of an inductor-less 28-nm CMOS prototype that achieves 72 GHz maximum input frequency and power-delay product of 21.5 fJ. Performance can be tuned to 66 GHz and 16.9 fJ, respectively, via lowering the supply voltage. In addition to standalone measurements with an off-chip input signal, a fundamental-frequency dual-core voltage-controlled oscillator provides on-chip and realistic input signal generation. [ABSTRACT FROM AUTHOR]

This paper proposes a temperature sensor based on temperature-frequency conversion using 180 nm CMOS technology. The temperature sensor consists of a proportional-to-absolute temperature (PTAT) current generating circuit, a relaxation oscillator with oscillation frequency proportional to temperature (OSC-PTAT), a relaxation oscillator with oscillation frequency independent of temperature (OSC-CON), and a divider circuit cascaded with D flip-flops. Using BJT as the temperature sensing module, the sensor has the advantages of high accuracy and high resolution. An oscillator that uses PTAT current to charge and discharge capacitors to achieve oscillation, and utilizes voltage average feedback (VAF) to enhance the frequency stability of the oscillator is tested. Through the dual temperature sensing process with the same structure, the influence of variables such as power supply voltage, device, and process deviation can be reduced to a certain extent. The temperature sensor in this paper was implemented and tested with a temperature measurement range of 0–100 °C, an inaccuracy of +0.65 °C/−0.49 °C after two-point calibration, a resolution of 0.003 °C, a resolution Figure of Merit (FOM) of 6.7 pJ/K2, an area of 0.059 mm2, and a power consumption of 32.9 μW.

Low-phase noise and wideband phased-locked loops (PLLs) are crucial for high-data rate communication and imaging systems. Sub-millimeter-wave (sub-mm-wave) PLLs typically exhibit poor performance in terms of noise and bandwidth due to higher device parasitic capacitances, among other reasons. In this regard, a low-phase-noise, wideband, integer-N, type-II phase-locked loop was implemented in the 22 nm FD-SOI CMOS process. The proposed wideband linear differential tuning I/Q voltage-controlled oscillator (VCO) achieves an overall frequency range of 157.5–167.5 GHz with 8 GHz linear tuning and a phase noise of −113 dBc/Hz @ 100 KHz. Moreover, the fabricated PLL produces a phase noise less than −103 dBc/Hz @ 1 KHz and −128 dBc/Hz @ 100 KHz, corresponding to the lowest phase noise generated by a sub-millimeter-wave PLL to date. The measured RF output saturated power and DC power consumption of the PLL are 2 dBm and 120.75 mW, respectively, whereas the fabricated chip comprising a power amplifier and an integrated antenna occupies an area of 1.25 × 0.9 mm2.

In recent years, sound source localization, as a passive localization technique with higher safety and convenience compared with other localization techniques such as active emission of electromagnetic waves, has received more and more attention in academia. This paper researches and improves the far-field sound source localization algorithm based on the generalized cross-correlation method (GCC) Time Difference of Arrival (TDOA) estimation algorithm and completes the design and implementation of the microphone array sound source localization system. This paper adds a frequency divider to the traditional generalized correlation time delay estimation algorithm for pre-processing, sampling, and localization of sound source acoustic waves and adopts a low-cost microphone array deployment scheme as far as possible to improve the flexibility and practicality of the localization system; at the same time, the “Minimum Sphere Method” is used at the back end of the algorithm to classify the localization coordinates at different frequencies and, finally, output reasonable sound source coordinates. In the back-end of the algorithm, the “Minimum Sphere Method” is used to classify the localization coordinates at different frequencies and, finally, output the reasonable sound source coordinates. The experimental results show that the sound source localization system designed in this paper has good performance in terms of localization accuracy and cost-effectiveness and overcomes the failure of the generalized mutual correlation algorithm in the original application of high noise environment and multi-source environment localization.

This research work presents the analysis, design, and characterization of a concept for an mm-wave divide-by-4 frequency divider utilizing an extended true single-phase clock (E-TSPC) and a TSPC divide-by-2 stage. The divider operates from 16 to 70 GHz from a 0.8-V supply with the highest power consumption of 0.35 mW. Operating frequencies up to 53 GHz were reached with a supply voltage of only 0.5 V at 0.12-mW power consumption. The self-resonance frequency of the circuit is adjustable through backgate biasing from 40 up to 70 GHz at 0.9-V supply, allowing a reduction in the required input power in this frequency range. Locking ranges up to 114% have been measured by changing only the backgate voltage. The circuit design is illustrated in detail and supported with original analysis and an explicit expression to calculate the self-oscillation frequency of the E-TSPC divider. The presented circuit was fabricated on a 22-nm fully depleted silicon-on-isolator complementary metal–oxide–semiconductor (CMOS) technology and occupies an active area of $3.4 ~\mu \text{m}^{2}$. The circuit requires the lowest power consumption and area among state-of-the-art RF frequency dividers, while it demonstrates the second widest adjustable operating frequency range and the second highest self-resonance frequency for CMOS D-flip-flop frequency dividers. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Though Current Mode Logic has excellent features like higher switching speed and reduced crosstalk due to small output swing, there exists numerous flaws such as static power dissipation, non-suitable for power-down modes and comparably higher design complexity of load resistors. To address the aforementioned worries, this article incorporates a dynamic current mode design approach having active load and controlled current source to configure an improved (2/3) dual modulus prescaler. Simulation results of the proposed circuit using Cadence Virtuoso platform for 90 nm CMOS at 1.2 V supply depict a power consumption of 2.517 mW when driven by a high frequency of 2 GHz. The phase noise and output noise are found to be − 147.001 dBc/Hz and − 181.7 dB at 1 MHz offset while it reads a self-oscillation frequency of 5 GHz. The variation tolerance of the design is proved via 5% skew-based simulation at all corners; whereas the correct functionality at 28 nm UMC justifies its scalability. [ABSTRACT FROM AUTHOR]

An injection‐locked frequency divider (ILFD) with the low‐power divide‐by‐4 feature for K‐band applications in a 0.18 μm CMOS process is reported in this letter. Output differential signals (f0 = 4f0‐3f0) are obtained by the third‐harmonic signals (3f0) from the free‐running core mixing with injection signals (4f0) through injection transistors in the proposed ILFD. This improves the locking range and saves power consumption by employing an inductive resonator technique and double cross‐coupled transistor pairs without the help of varactors. For the proposed ILFD, the measured free‐running frequency is 5.126 GHz and input injection frequencies at an input power level of 0 dBm are from 19.4 to 21.4 GHz. From a supply voltage of 1.5 V, the proposed ILFD core only dissipates 4.2 mW. [ABSTRACT FROM AUTHOR]

High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 $\times $ compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal–oxide–semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm2. It consumes 370 $\mu \text{W}$ from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has −7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a −22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4. [ABSTRACT FROM AUTHOR]

Copyright of Experimental Technology & Management is the property of Experimental Technology & Management Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A fault-tolerant hardening-by-design frequency divider has been proposed for clock and data recovery in a 28-nm CMOS process. By means of the mandatory updating mechanism, the proposed divider can update the state of the D flip-flops from an error state to a correct state so as to avoid single-event transient (SET) accumulation in different finite-state machines (FSMs). Our proposed divider also does not destroy the original structure and can, thus, greatly reduce performance degradation. Laser tests show that the threshold of the proposed divider can be significantly improved. The heavy-ion experiment shows good SET/single-event upset (SEU) tolerance during the ion strike under 83.7 MeV·cm2/mg.

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Postlayout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74-μW power consumption for the high-speed design and a maximum frequency of 10 GHz with 53-μW power consumption for the minimum PDP design. [ABSTRACT FROM AUTHOR]

A 73 ~ 106 GHz divide-by-2 injection-locked frequency-divider (ILFD2) using 90 nm CMOS technology is presented. To achieve a wide locking range, an optimal transistor width ratio of the injection transistor (or mixer) and cross-coupled transistors (CCT) is adopted. To enhance the operation frequency, distributed LC network is used as the load of the CCT. To enhance the input sensitivity, an input power matching network is included in the injection transistor. In addition, for further locking ranging enlargement, the inductive peaking and forward-body-bias techniques are used in the injection transistor for raising its quadrature output current (or conversion gain). The ILFD2 consumes 4.92 mW, and achieves an excellent phase noise of – 106.2 dBc/Hz (at 1 MHz offset from the output frequency of 50 GHz). The ILFD2 achieves a wide locking-range of 33 GHz (73–106 GHz (36.9%)), covering the 77 GHz automotive radar frequency band and the 94 GHz imaging radar frequency band. The ILFD2 can be operated at a low input power of – 60 dBm, one of the best input sensitivities ever reported for a W-band CMOS ILFD2. The core area of the ILFD2 is only 0.014 mm2. [ABSTRACT FROM AUTHOR]

TDCs formed by ring oscillators are arrayable, scalable, and low power, making them suitable for SPAD-based TCSPC 3D imaging systems. The TDC precision affects the ranging accuracy and, hence, the quality of the reconstructed 3D image. This brief studies the jitter of ring-oscillator-based TDCs as a function of their full-scale-range and derives an expression for the TDC total jitter. The introduced behavioral model describes three different regions of the SNR for TDCs. A peak-SNR design-point is identified. Increasing the full-scale-range of the TDC beyond this point entails increased jitter and, thus, ultimately a declining SNR. The analysis is validated using post-layout simulations of a ring-oscillator-based TDC designed in 65nm CMOS. A TDC resolution degradation factor defines the TDC jitter behavioral model. It is consistent with FOMs that have been used in the past to evaluate TDCs and clarifies their underlying assumptions. [ABSTRACT FROM AUTHOR]

This paper reports an injection‐locked frequency divider (ILFD) with a divide‐by‐five feature, a built‐in balun, and low power consumption fabricated in a standard 0.18 μm CMOS process. By employing a fourth harmonic (4f0) enhancement technique realized in a stacked cross‐coupled pair and mixing with an injection signal (5f0) through injection transistors, an output signal (f0 = 5f0‐4f0) is obtained without using extra passive devices. The built‐in balun is employed to transfer a single‐ended signal to differential signals injected into injection transistors. The proposed ILFD improves the locking range without the help of varactors and the power dissipation by adopting two cross‐coupled transistor pairs. The proposed ILFD has the free‐running frequency of 4.3 GHz and the injection frequencies from 21.1 to 22.1 GHz at an input power level of 0 dBm. The proposed ILFD core only consumes 3.75 mW from a supply voltage of 1.5 V. [ABSTRACT FROM AUTHOR]

In this work, a dual-mode (divide-by-2 and divide-by-3) dynamic frequency divider is presented. A tunable delay gated ring oscillator (TDGRO) topology is proposed for dual-mode operation and bandwidth extension. It uses a 130-nm gate length SiGe BiCMOS technology with the $f_{t}$ and $f_{\mathrm {max}}$ of 250 and 370 GHz, respectively. Verification shows that it works at $W$ -band from 70 to 114 GHz (47.8% bandwidth) for divide-by-2 and works at $D$ -band from 105 to 160 GHz (41.5% bandwidth) for divide-by-3. This divider can be used in integrated phase-locked loops (PLLs) at millimeter-wave frequencies. [ABSTRACT FROM AUTHOR]

Summary: In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology. [ABSTRACT FROM AUTHOR]

This letter proposes an optimization-free technique to estimate the parameters of voltage dependent loads through the measurements of only the load active and reactive power consumption and frequency deviations at the load bus. The technique is shown to be a relevant consequence of the dependency of power flow equations on the bus voltage phase angles. The WSCC 9-bus and the IEEE 14-bus systems serve to illustrate the proposed technique. [ABSTRACT FROM AUTHOR]

An injection-locked frequency divider topology for wide locking-range and high-order division is presented. Based on the theoretical analysis of the locking-range and injection locking characteristic, we propose locking-range enhancement techniques and high-order dividing topology. Fabricated in a 0.18-μm BiCMOS process, three test circuits are designed with only a standard CMOS, aiming at input frequency ranges of 7.8, 11.1, and 11.7 GHz. The 7.8-GHz divide-by-2 ILFD consumes 2.9 mW with a locking range of 692 MHz operated from a 1.5 V supply. The optimized dual injection method improves the locking range by a factor of 10. The 11.1-GHz divide-by-3 ILFD employs an even-harmonic phase tuning technique and the proposed technique improves the locking range by 25%. The core of the 11.1-GHz ILFD consumes 6.15 mW from a 1.8 V supply. For the 11.7-GHz divide-by-3 ILFD, a self-injection technique is proposed that utilizes harmonic conversion and self-injection to improve phase-noise, locking-range, and input sensitivity simultaneously. By employing harmonic tuning and self-injection, odd-order division is enabled with 47.8% enhancement in the locking-range and 15.7-dBc/Hz reduction in phase noise.

To meet the specification of the qubits in our laboratory, a 0.4 kA·cm−2 superconducting rapid single flux quantum (RSFQ) circuit was designed and successfully fabricated with an improved Nb-based self-aligned lift-off process. This circuit consists of a single-flux-quantum (SFQ) pulse generator, a Josephson transmission line (JTL) and a T-flip flop (TFF), and it acts as a frequency divider. The values of the inductors in this circuit were extracted using InductEX and the basic function of this circuit was confirmed using the simulation software WRspice before fabrication. After fabrication, the basic parameters of this circuit were measured at ~ 2.5 K in a Janis He-3 cryostat. This work laid the theoretical and experimental basis for the future research on the RSFQ-qubit control circuits. [ABSTRACT FROM AUTHOR]

A low power and wide locking-range W-band (75–110 GHz) divide-by-2 direct injection-locked frequency-divider (DILFD) using standard 90 nm CMOS technology is reported. To enhance the operation frequency, distributed LC network is used as the load of the crossed-coupled transistors. To improve the input sensitivity, a power matching network is included at the injection terminal of the switch transistor. In addition, to enhance the frequency locking range, body bias technique (i.e. a body resistor in conjunction with a zero body-source bias) is adopted in the switch transistor to reduce its threshold voltage. The result shows that a wide locking-range of 23.5 GHz [from 69.5 to 93 GHz (28.9%)], covering the 77–81-GHz-band for short range automotive radar system and 81–86-GHz-band for high-speed point-to-point wireless communication access system, was achieved. The DILFD can be operated at a low input power of − 35 dBm, one of the best input sensitivity ever reported for a W-band CMOS divider. The power consumption of the DILFD was only 3 mW from a 0.7 V power supply. The chip area was only 0.76 × 0.66 mm2 excluding the test pads. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor topology. The first ILFD3 (ILFD31) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower cross-coupled transistors and then inject the source terminals of the upper cross-coupled transistors. The second ILFD3 (ILFD32) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower cross-coupled transistors. Due to the strong second harmonic signal (2finj) at the source terminals of the upper cross-coupled transistors, there are notable locked fundamental signals (finj) at the drain terminals of the upper cross-coupled transistors. ILFD31 occupies a chip area of 0.744 × 0.859 mm2 (i.e. 0.639 mm2), consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5-95.9 GHz). ILFD32 occupies a chip area of 0.87 × 0.775 mm2 (i.e. 0.674 mm2), consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8-109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s. [ABSTRACT FROM AUTHOR]

Frequency divider is digital circuit which is widely used in wireless communication, frequency dividers can be realized by using flip flops such as toggle type or delay type flip flops. We have tested the utilization of a true single phase clocking (TSPC) technique based D Flip-Flop implemented as a high-frequency divider-by-2 circuit. This divider consists of one TSPC D-flip-flops (D-FF). To achieve high-speed operations as well as downsize the circuit, the NOR functions are implemented into the TSPC D-FF. We have designed the frequency divider using 32nm CMOS process. The power consumption and operating frequency of the proposed divider was investigated. In the measurements, we have confirmed that the frequency is divided by 2 at higher frequency of 10 GHz clock with power consumption of 71.9065 nW. The circuit is implemented for the purpose of low-power high-frequency division applications for wireless local area netwok applications. [ABSTRACT FROM AUTHOR]

This letter proposes a precise frequency-dependent model for power systems that takes into account spatial variations of the frequency in the network during a transient. In the proposed approach, boundary conditions are synchronous machine rotor speeds and the variation of the frequency is based on the concept of frequency divider recently proposed by the authors. The proposed model leads to a more accurate simulation of transient conditions than conventional models for angle and voltage stability analysis. This letter discusses the theoretical background of the proposed model and compares it with the standard transient stability model, as well as with a fully-fledged dynamic phasor model through a 1479-bus dynamic model of the all-island Irish transmission system. [ABSTRACT FROM AUTHOR]

This paper presents a novel mixed-signal low-power dual-band square/triangular waveform generator (WFG) chip with a wide low-frequency tuning range for medical bio-electric stimulation therapy. It consists of a relaxation oscillator comprising a hysteresis Schmitt trigger and a timing integrator, along with frequency divider (FD) stages and path selector output for driving an electrode from 16 selectable channels. It was fabricated using Global Foundries 8RF-DM 130-nm CMOS process with a supply voltage of ±1 V for the oscillator and +1 V for logic circuits. The WFG provides an output of around 1.5 Vp-p at a nominal low oscillation frequency of 17 kHz using small-size on-chip passive components of values 10 kΩ and 10 pF. The WFG core (band I) can be tuned in the range 6.44-1003 kHz through bias current adjustment, while a lower frequency (band II) in the range 0.1 Hz-502 kHz can be provided digitally through a ÷2 stage. The power consumption was only 0.457 mW for the WFG and 2.1 mW for the FD circuit while occupying a total silicon area of only 18 426 μm2.

A transformer-based high-order resonator is proposed to improve the locking range (LR) of the millimeter-wave injection-locked frequency dividers (ILFDs). The LR limitations on ILFDs are discussed, and the operating principles of the proposed high-order resonator are analyzed based on their flattened phase response. The inductive gain peaking technique and the tail current source requirement are further analyzed for low power considerations. Two chips are fabricated in a 65-nm CMOS process to implement the proposed techniques: the first one measures an LR of 62.9% from 27.9 to 53.5 GHz while consuming 5.8 mW from a 1-V power supply and the second chip achieves an LR of 62.7% from 32.4 to 61.9 GHz while consuming only 1.2 mW from a 0.42-V power supply. The best figure of merit can achieve up to 24.7 GHz/mW. [ABSTRACT FROM AUTHOR]

In this paper, a algorithm which is used for carrier frequency offset (CFO) estimation is proposed in coherent optical communications system with binary phase-shift keying (BPSK) modulation. The proposed algorithm utilizes the frequency divider to broaden the range of the estimation algorithm. In a 5-GBaud coherent BPSK system, simulation results show that when 12dB signal-to-noise ratio (SNR) and 512 samples are utilized, a 8 frequency divider can expand the range of the frequency offset estimation from [-0.5GHz, +0.5GHz] to [-4GHz, +4GHz] and the CFO estimation error can be obtained less than 5MHz. The paper presents a novel algorithm that features the large estimation range for carrier frequency offset while estimation error is not enlarged. The experimental results verified the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

This paper presents a new analytic approach for static frequency divider design. It consists of derivations of analytic expressions for the self-oscillation frequency and frequency divider oscillation condition, based on the device-level circuit parameters only. Additionally, an analytic expression for frequency divider sensitivity is obtained based on injection-locking theory. The proposed approach is verified against measurement results of a static frequency divider, fabricated in SiGe BiCMOS 0.13- \mu \textm process. This approach enables fast preliminary frequency divider design based on time- and resource-efficient simulations. [ABSTRACT FROM PUBLISHER]

In this paper, the large signal operation of the ring oscillator based injection locked frequency divider is analyzed considering the trade-offs among the operating frequency, locking range and power consumption. A large signal model is used to reveal several key findings such as voltage-limited locking ranges and asymmetry between the upper and lower locking bands. They are applied to the optimize the dividers maintaining a good balance among design considerations. Several prototypes, including the divide-by-2 with 3 and 5 stages of inverters, divide-by-3 and divide-by-5, are implemented in a standard 0.18 µm CMOS technology to verify the operation under a large injected signal. As an extension, dual-modulus prescalers are further designed by the integration of switches for different ways of signal mixing. Measurements results show the proposed divide-by-2/3 unit and a divide-by-8/9 with this unit are able to work up to 8 GHz and 4.0 GHz with maximum power consumption of 0.7 mW and 1.5 mW respectively. [ABSTRACT FROM AUTHOR]

Oscillators are often followed by square wave forming circuits and frequency dividers. Traditionally, the level of the phase noise, transferred from the oscillator outputs to the square waves obtained is calculated ignoring the correlations in the oscillator phase noise spectrum. In this paper, accurate expressions are derived, taking into account the phase noise mechanisms in the oscillators. The phase noise power spectral densities are calculated in both the traditional way and by using the proposed expressions and they are compared. The situations where the proposed expressions can be useful are identified. [ABSTRACT FROM AUTHOR]

This paper introduces the key elements of a novel low-power, high precision localization system based on Time-Difference-of-Arrival (TDOA) distance measurements. The combination of multiple localizable sensor nodes, leads to an ad hoc network. Besides the localization functionality this ad hoc network has the additional advantage of a communication interface. Due to this a flexible positioning of the master station for information collection and the detection of static and mobile nodes is possible. These sensor nodes work in the 24 GHz ISM (Industrial Scientific and Medical) frequency range and address several use cases and are able to improve various processes for production scheduling, logistics, quality management, medical applications and collection of geo information. The whole system design is explained briefly. Its core component is the frequency modulated continuous wave (FMCW) synthesizer suitable for high performance indoor localization. This research work focuses on power and size reduction of this crucial system component. The comparison of the first and second generation of the system shows a significant size and power reduction as well as an increased precision.

This paper presents a power-efficient CMOS frequency divider (FD) with wide-band programmable division ratio and quadrature outputs for high-speed data transmission applications. The proposed FD consists of a power-efficient programmable divider (PD), a complementary volt-age-to-time converter based duty-cycle correction circuit, and a compact quadrature divider (QD). In the chain of PD, a sense-amplifier based dynamic flip-flop is proposed for 2/3 divider cell to achieve high-speed operation with significantly reduced power consumption. In addition, a simple but effective QD based on two pseudo-differential voltage-controlled tri-state inverters, is beneficial for generating precise quadrature output signals. Measurement results in 40-nm CMOS process show that the proposed FD achieves a wide division range from 16 to 254 and operates up to 14.8 GHz while consuming the power of 540.6 μW at 1.1-V supply, and occupying the active area of 0.00267 mm (114.6 μm × 23.3 μm). [ABSTRACT FROM AUTHOR]

This paper presents a symmetric review of academic and accomplished research endeavors in the field of Sub-Sampling Phase Locked Loop (SSPLL) design. Adequate emphasis has been given to understand the yearn for development of Sub-Sampling PLLs. Techniques that have emerged over the recent few years in context of better FOM, Jitter and Phase Noise reduction while maintaining extraordinary circuit performance in Sub-Sampling PLLs with CMOS/VLSI technology, have been captured in this paper. Consecutively, the main inspiration of this study is to present an overview of the PLL fundamentals, furtherance from analog to Digital PLL and various noises encountered in the different PLL components, important for the reader to have a better understanding about the design and analysis of Sub-Sampling PLLs. [ABSTRACT FROM AUTHOR]

Distributed injection-locked frequency division is introduced as a method to increase the locking range beyond that of conventional injection-locked frequency dividers. It is analytically shown that continuous frequency division can be achieved over a frequency range that spans over multiples of the self-oscillation frequency of the core divider. Design techniques in millimeter-waves are discussed in detail. A proof-of-concept prototype, realized in a foundry 130-nm BiCMOS SiGe HBT technology, achieves a measured locking range of 35–44 and 41–59.5 GHz while consuming 3.8 mW from a 1.15-V supply. [ABSTRACT FROM PUBLISHER]

High speed and low power are the main challenges in modern VLSI design. The proposed paper presents swift frequency divider circuit using MCML (MOS Current Mode Logic). The divider operates up to 60GHZ clock frequency. The implementation is carried by using 45nm cadence virtuoso tool. The presented logic consumes 2.5mW from 1.2V supply. The phase noise of the proposed frequency divider is 150dBc/Hz at 60GHz offset. [ABSTRACT FROM AUTHOR]