33 results on '"Ronse, K."'
Search Results
2. Metal stack optimization for low-power and high-density for N7-N5
3. Impact of a SADP flow on the design and process for N10/N7 metal layers
4. Opportunities and challenges in device scaling by the introduction of EUV lithography
5. High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout
6. Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell
7. Full field EUV lithography: lessons learned on EUV ADT imaging, EUV resist and EUV reticles
8. Lithography options for the 32nm half pitch node and beyond
9. Imaging performance of the EUV alpha semo tool at IMEC
10. EUV pattern shift compensation strategies
11. Investigation of mask defectivity in full field EUV lithography
12. Assessment of EUV reticle blank availability enabling the use of EUV tools today and in the future
13. Progress in 193nm immersion lithography at IMEC
14. Progress in ArF immersion lithography
15. EUV pattern shift compensation strategies.
16. Imaging performance of the EUV alpha semo tool at IMEC.
17. Full field EUV lithography: lessons learned on EUV ADT imaging, EUV resist and EUV reticles.
18. Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield.
19. Lithography for sub-90nm applications.
20. Optical lithography techniques for 0.25 /spl mu/m and below: CD control issues.
21. Optical Lithography Techniques for 0.25 μm and Below.
22. Lithography as a critical step for low-k dual damascene: from 248 nm to 193 nm.
23. Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits
24. Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield
25. ArF lithography for the 130 and 100 nm technology nodes
26. Optical lithography techniques for 0.25 μm and below: CD control issues
27. Lithography for sub-90nm applications
28. Lithography as a critical step for low-k dual damascene: from 248 nm to 193 nm
29. A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
30. Status and challenges of extreme-UV lithography.
31. ArF lithography for the 130 and 100 nm technology nodes.
32. Feasibility demonstration of 0.18 /spl mu/m and 0.13 /spl mu/m optical projection lithography based on CD control calculations.
33. Progress in ArF immersion lithography.
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