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This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

This paper presents a cycle by cycle Frequency Shift Keying (FSK) demodulator, able to demodulate a FSK signal with 1% frequency modulation index (MI), in a single cycle. Based on the proposed demodulation scheme, a high rate data transmission link can be established through a high-Q inductive coupling link, breaking the basic tradeoff between the power transfer efficiency (PTE) and data rate in single carrier wireless power and data transfer systems. Designed and simulated with $0.18\mu m$ CMOS process, the proposed FSK demodulator, detects successfully a 5Mbps data with a carrier frequency of 5MHz. A test chip is fabricated in 180nm CMOS technology. Measurement results shows that the demodulator is able to demodulate the cycle-by-cycle modulated FSK signals with low modulation index of 2.5%, with a BER of $1.24\times 10^{-5}$. [ABSTRACT FROM AUTHOR]

Inhomogeneous linear ordinary differential equations (ODEs) and systems of ODEs can be solved in a variety of ways. However, hardware circuits that can perform the efficient analog computation to solve them are rarely in the literature. To address such problems, this paper proposes a general method of using a memristor-capacitor (M-C) circuit to solve inhomogeneous linear ODEs and systems of ODEs of any order in initial value problems. The M-C circuit can match the coefficients of the equations sought by adjusting the memristor resistance value according to the coefficient formula proposed in the paper, which has higher programmability. Then, some ODEs and systems of ODEs are given in the paper as examples to evaluate the proposed method. According to the comparison results based on MATLAB software simulation and the simulation based on OrCAD software, the designed M-C circuit has an effective improvement in speed and the accuracy exceeds 99.95% in software simulation. Based on practical verification, this paper gives the actual M-C circuit experiment based on PCB. Moreover, the proposed method can be used to quickly solve the object motion state in the spring mass damping system in actual engineering, and the accuracy can reach 99.98%. [ABSTRACT FROM AUTHOR]

High step-up converters are often used in photovoltaic applications due to low voltage of photovoltaic modules. In this paper, a study of several voltage step-up cells added on primary and secondary sides of an isolated dc-dc SEPIC (single ended primary inductor converter) is made, in order to increase its static gain and synthesize a family of converters. To perform this study and select the most appropriate resulting converter, theoretical and comparative analyzes are accomplished. They include a brief description of each converter, tables and curves with relevant information, such as voltage gain, voltage stresses and component count, and the identification of the use of coupled inductor or transformer based on the analysis of dc magnetizing current. Moreover, theoretical analysis and experimental results on a 50 kHz and 200 W prototype of selected isolated SEPIC with voltage doubler cell are presented to validate the proposed topology and concept. [ABSTRACT FROM AUTHOR]

Deep learning training involves a large number of operations, which are dominated by high dimensionality Matrix-Vector Multiplies (MVMs). This has motivated hardware accelerators to enhance compute efficiency, but where data movement and accessing are proving to be key bottlenecks. In-Memory Computing (IMC) is an approach with the potential to overcome this, whereby computations are performed in-place within dense 2-D memory. However, IMC fundamentally trades efficiency and throughput gains for dynamic-range limitations, raising distinct challenges for training, where compute precision requirements are seen to be substantially higher than for inferencing. This paper explores training on IMC hardware by leveraging two recent developments: (1) a training algorithm enabling aggressive quantization through a radix-4 number representation; (2) IMC leveraging compute based on precision capacitors, whereby analog noise effects can be made well below quantization effects. Energy modeling calibrated to a measured silicon prototype implemented in 16 nm CMOS shows that energy savings of over $400\times $ can be achieved with full quantizer adaptability, where all training MVMs can be mapped to IMC, and $3\times $ can be achieved for two-level quantizer adaptability, where two of the three training MVMs can be mapped to IMC. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

Eight-switch three-phase post-fault inverter (ESTPI) is widely used as the reconfigured topology of three-phase three-level neutral point clamped DC/AC inverter when open-circuit fault occurs. A key technical challenge for the ESTPI is the post-fault controller design. The existing post-fault control approaches for the ESTPI suffer from the difficulty in trading off the current tracking performance, neutral point voltage (NPV) balancing and common mode voltage (CMV) levels. To solve this problem, this paper proposes an improved predictive current control algorithm. The proposed algorithm contributes to achieve accurate output current tracking while greatly reducing the CMV with a balanced NPV. Simulation and experimental results are presented to validate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

A new active building block namely, subtractor connected first-generation current conveyor (S-CCI) is introduced in this paper. A simulated floating inductor (SFI) and two new quadrature oscillators (QOs) employing only one S-CCI are introduced as application examples. The introduced SFI employs two resistors with a single matching requirement and a grounded capacitor. Each of the introduced QOs has one grounded resistor, one floating resistor, and two grounded capacitors without any matching problems. Non-ideality analyses are performed. Furthermore, a third-order filter application is given. A layout of the S-CCI in $0.18 \mu \text{m}$ technology occupying the area of about $71\,\,\mu \text{m}\,\,\times 44\,\,\mu \text{m}$ is given. Also, numerous post layout simulations based on the SPICE program are accomplished. Moreover, several experiments are realized to confirm the theory. [ABSTRACT FROM AUTHOR]

In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology. [ABSTRACT FROM AUTHOR]

Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel-physics-based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this paper, for the first time, we demonstrate hardware implementation of recurrent SNN using proposed low-power, low-area, and low-leakage band-to-band-tunneling (BTBT) based neurons. A low-power thresholding circuit is proposed. We further propose a predistortion technique to linearize a nonlinear neuron without any area and power overhead. We establish the equivalence of the proposed neuron with the ideal LIF neuron to demonstrate its versatility. The tunneling regime enables a high input impedance in the BTBT neurons (few $\text{G}\Omega$) to enable a voltage input without loading the synaptic array. To verify the effect of the proposed neuron, a 36-neuron recurrent SNN is fabricated in GF-45nm PDSOI technology. We achieved 5000x lower energy-per-spike at a similar area and 10x lower standby power at a similar area and energy-per-spike. Such overall performance improvement enables brain scale computing. [ABSTRACT FROM AUTHOR]

A well-performed capacitive power transfer (CPT) system highly depends on its compensation to achieve load-independent (LI) output and zero phase angle (ZPA) operation. It is particularly meaningful to maintain these objectives under various misalignments. This paper is devoted to a general and comprehensive method to study and explore all the potential high-order compensations. The coupler parameter variation is evaluated under different types of misalignment, and misalignment-insensitive (MI) parameters are properly designed for MI resonance. A general and straightforward decomposition and synthesis method is then proposed to generate the high-order resonant tanks. With the help of inverse ABCD parameters, all tank candidates are further judged by their capability for LI output and ZPA operation. Finally, two example CPT systems are built to verify the LI output and ZPA operation under misalignment. [ABSTRACT FROM AUTHOR]

Many energy harvesters (EH) deliver an ac voltage and require a rectifier as a consequence. This paper describes how the rectifier affects the power flow transmitted from the EH to the load and how to tackle the different voltage amplitudes. This study has been performed using analytical calculations, numerical modeling and experiments. To reach the maximum power transfer, conventional methods apply a fraction of the open-circuit voltage delivered by the EH. In contrast, this study points out that the optimum operating point must be shifted by a quantity depending on the rectifier characteristics. This difference is particularly important when the EH provides relatively small ac voltages. Two classic rectifiers are covered: a diode bridge (DB) and a MOSFET bridge (MB). An approximated solution of the analytical model is proposed and allows to optimize the EH without cumbersome numerical computations. Experiments are conducted first with a function generator and then with an electromagnetic EH prototype. The outcomes from the analytical model and the numerical model are in good agreement with the experimental results. A new regulation method is proposed for maximizing the power transferred from the ac EH to the load. [ABSTRACT FROM AUTHOR]

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- $\mu \text{m}$ standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved $\sim 1.24\times $ more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%. [ABSTRACT FROM AUTHOR]

In this paper, a highly efficient gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) Doherty power amplifier (DPA) from 4.6 to 5.5 GHz with the consideration of the influence of the peaking transistor’s output capacitor $(C_{\mathrm {out}}$) operated in Class-C state is presented. Based on the load-modulation behavior analysis, the effect of the $C_{\mathrm {out}}$ of the peaking transistor on the performance of the wideband DPA has been theoretically analyzed for the first time by directly evaluating the value of the peaking transistor’s $C_{\mathrm {out}}$. A hybrid matching technique has been proposed to ensure that the DPA can realize a proper load-modulation with high back-off efficiency in a wide bandwidth. In this method, the peaking transistor is matched using a simple T-shape band-pass type network with the $C_{\mathrm {out}}$ of the peaking transistor in Class-C operation state compensated properly, while the carrier transistor is matched using a 2-point matching method. For verification, a wideband GaN MMIC DPA with the frequency range of 4.6 to 5.5 GHz was designed using a 0.25- $\mu {\mathrm{ m}}$ GaN on silicon-carbon high-electron-mobility transistor process. Experimental results show that the fabricated DPA can realize the output power of 41.1-41.6 dBm and the drain efficiency (DE) of 57.6%-63.3% at saturation in the whole frequency band. The measured DE at 6-dB power back-off is 51%-56.4%. Good linearity with high average efficiency performance was obtained when excited by a 160-MHz modulated signal after linearization. [ABSTRACT FROM AUTHOR]

This paper deals with nonlinear control of a single-phase half-bridge interleaved buck shunt active power filter (HBIB-SAPF) with a nonlinear load. The control objective for the system is twofold: performing power factor correction by compensating for harmonics and reactive current consumed by the nonlinear load from one hand and tightly regulating the HBIB converter DC capacitor voltage. Both objectives are accomplished using a two-loop nonlinear controller. The inner loop acts on the switching devices so that the active filter current tracks its reference with the aim of ensuring a unity power factor. This loop is tackled using backstepping technique and Lyapunov approach. The outer loop is responsible for regulating the DC capacitor voltage to its desired value, using a PI controller with a pre-filter. The stability analysis of the closed-loop system is formally performed by using the averaging theory. The validity of the designed nonlinear controller is checked by simulations in Matlab/SimpowerSystem showing its robustness and accuracy under various operating conditions. [ABSTRACT FROM AUTHOR]

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to $4.63\times $ lower minimum power consumption and slightly better FoM values than CSROs. [ABSTRACT FROM AUTHOR]

The main focus of this paper is the presentation of reliable methods for the determination of the optimum coloring of a graph, commonly known in the literature as vertex coloring problem. It has been shown that networks of capacitively coupled oscillators can be used to solve vertex coloring problems. In this paper we address the negative impact of an unbalanced number of couplings for the oscillators on the performance of the network and compensate for this non-uniform coupling structure by an adjustment in the network itself. The negative effect of the memristor device-to-device variability of the NbOx memristor on the array functionality will be investigated and reduced via an adaptation of the memristor operating point. The main improvement in network performance is achieved by setting up a control procedure allowing the network to bypass the local solutions and converge to the global one. Two strategies inspired by global optimization algorithms will be proposed to allow the network to overcome sub-optimal solutions, and find the solution corresponding to the absolute minimum of a performance measure function of the vertex coloring problem. [ABSTRACT FROM AUTHOR]

An energy-harvesting interface that incorporates a continuously scalable-conversion-ratio (CSCR) switched-capacitor (SC) dc-dc converter with maximum power point tracking (MPPT) is introduced in this paper. By exploiting unique characteristics of a CSCR SC converter, an MPPT based on the hill climbing algorithm is implemented with a real-time power monitoring scheme with a frequency-mapped sampling capacitor DAC, allowing variation-tolerant MPPT for various types of energy sources. The harvestable voltage range is significantly extended by a step-up/down convertible CSCR SC converter, and the voltage conversion efficiency is further improved with matrix-structured and load-mapped power switches. With the test chip fabricated in 28nm FDSOI technology, the proposed energy harvesting interface shows peak conversion efficiency of 89% and average efficiency of > 80% for 60-2, $794~\mu \text{W}$. MPPT efficiency of > 97 % is confirmed with energy harvesting measurement with a solar cell. [ABSTRACT FROM AUTHOR]

In a capacitive wireless power transfer system, due to the pF-level coupling capacitance, resonant inductors are commonly used at the primary side to boost voltage and at secondary side to boost the current. However, the inductors are bulky, in particular when it comes to integration, thereby not preferred by some space-sensitive applications like smartphones, smart glasses and headphones. This paper proposes a capacitive wireless power transfer architecture with no inductors at the receiver side. A high conversion ratio step down switched capacitor converter (SCC-CPT), rather than inductors, is used to compensate for the impedance mismatch between the secondary side of the capacitive coupler and the load. The analysis method and its associated design procedure of the SCC-CPT system is developed with the target of clarifying the tradeoffs among the secondary side efficiency, coupler voltage stress, receiver side integrability, and the primary side compensation network gain. Finally, a 7.5 W, 12 MHz SCC-CPT prototype was constructed to validate the proposed analysis and design. The measured system efficiency is 75.6 % at 7.5 W output, and the secondary side switched capacitor converter efficiency is 96.4 %. [ABSTRACT FROM AUTHOR]

This paper presents a monolithically integrated E-band amplifier multiplier chain (AMC) developed in 130 nm SiGe BiCMOS process. This E-band AMC is composed of a 25 GHz 1:1 power divider, two 25 GHz driver amplifiers (DA1,2), a 75 GHz passive frequency tripler, and a 75 GHz power amplifier (PA). By applying a bypass tuning capacitor based power enhancing technique in the single-ended DA and PA, the output power and power-added-efficiency (PAE) of the AMC have been effectively improved. Benefiting from the proposed passive tripler core with second harmonic suppression function, and the impedance matching network with frequency selection characteristics, the AMC presents better harmonic suppression performance compared with the conventional topology. The bias circuits with temperature compensation are applied to the DA and PA to ensure the performance of the AMC when the temperature changes. The AMC has a measured output power exceeding 0 dBm in the entire E-band frequency range with a peak output power of 10.9 dBm at 77 GHz, and exhibits a record PAE of 8.25 %. Within the 3 dB operating frequency range from 69 to 87 GHz, the rejection of fundamental and second harmonics are better than 33.5 dB. The AMC can work properly between −40°C and 125 °C with the proposed temperature compensation bias circuits. [ABSTRACT FROM AUTHOR]

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively. [ABSTRACT FROM AUTHOR]

The paper considers a relevant class of networks containing memristors and (possibly) nonlinear capacitors and inductors. The goal is to unfold the nonlinear dynamics of these networks by highlighting some main features that are potentially useful for real-time signal processing and in-memory computing. In particular, an analytic treatment is provided for dynamic phenomena as the presence of invariant manifolds, the coexistence of different regimes, complex dynamics and attractors and the phenomenon of bifurcations without parameters, i.e., bifurcations due to changing the initial conditions of the state variables for a fixed set of circuit parameters. The paper also addresses the issue of how to design pulse independent voltage or current sources to steer the network dynamics through different manifolds and attractors. Two relevant examples are worked out in details, namely, a variant of Chua’s circuit with a memristor and a nonlinear capacitor and a relaxation oscillator with a memristor and a nonlinear inductor. In the latter example, the paper also studies the effect on manifolds and coexisting dynamics when real memristive devices are accounted for using a class of extended memristor models. The analysis is conducted by means of a recently developed technique named flux-charge analysis method (FCAM). Numerical simulations are presented to confirm the theoretic findings. [ABSTRACT FROM AUTHOR]

This paper presents a buffer-embedded noise-shaping SAR ADC, whose input buffer separates the capacitive DAC (CDAC) and the sampling capacitor (CS) at the input and output of the input buffer. This compensates for the non-linearity of the input buffer and reduces the CS value, resulting in a significant power saving in the input buffer. This buffer-embedded architecture enables the effective implementation of the following passive loop filter and enhances energy efficiency. A bootstrapping switch in the feedback CDAC is coupled to the output of the buffer, thereby avoiding a signal dependency due to the parasitic capacitance of the switch. The buffer-embedded noise-shaping SAR ADC occupies 0.08mm2 in a 65 nm CMOS process and features a parasitic input capacitor of 0.2 pF. It achieves 73.8 dB SNDR, 77 dB DR and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. Including the power consumption of the input buffer, the ADC consumes only 2.1 mW. [ABSTRACT FROM AUTHOR]

Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA. [ABSTRACT FROM AUTHOR]

This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard $0.18~\mu \text{m}$ CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes $1.53~\mu \text{W}$ with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling. [ABSTRACT FROM AUTHOR]

This paper investigates an ultra-broadband sampling technique based on charge sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration times. The charge sampling technique is mathematically analyzed in detail and compared to conventional switched-capacitor sampling. The mathematical analysis allows to predict the sampler bandwidth as well as the degradation of sampling precision due to analog circuit impairments such as integrator gain error, integration capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore, design, simulation, and measurement results of an ultra-broadband charge sampler IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits (ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results suggest that charge sampling using an IHC is a viable concept for ultra-broadband sampling. [ABSTRACT FROM AUTHOR]

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/ƒ noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (ƒch) same as the sampling frequency (ƒs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/√Hz input-referred noise density, 1.9 μ V offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. [ABSTRACT FROM AUTHOR]

This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums for MAC operation with multi-bit weights, the proposed macro implements analog weighted sums for energy-efficient bit-scalable MAC operations with a novel series-coupled merging scheme. A test chip with a 16-kb SRAM macro is fabricated in 28-nm FDSOI process, and the measured macro throughput is 125.2-876.5 GOPS for weight bit-precision varying from 2 to 8. The macro also achieves energy efficiency ranging from 18.4 TOPS/W for 8–b weight to 119.2 TOPS/W for 2-b weight. [ABSTRACT FROM AUTHOR]

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A. [ABSTRACT FROM AUTHOR]

This paper presents an integrated ultra-low-power (ULP) wireless sensor system-on-chip (SoC) that can be used for voltage sensing in both Internet of Things applications and bio-potential monitoring. In order to increase the energy efficiency of the analog front-end (AFE), we propose a noise and power efficient push-pull low noise instrumentation amplifier (LNIA) with a built-in ripple reduction loop based on capacitor reuse. A low-power ISM-band harmonic injection locked on-off-keying transmitter (OOK-TX) is also implemented for energy efficient wireless connectivity. Circuit implementations, design considerations, and detailed analysis are presented to improve the overall energy efficiencies of the SoC including the AFE, TX and, the power management unit. The proposed ULP-SoC is fabricated in 130 nm CMOS technology with a total area of 1.92 mm2. The total power consumption of the proposed system-on-chip is 197.1 μW which is one of the lowest among state-of-the-art wireless sensor SoC. [ABSTRACT FROM AUTHOR]

In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514 S/s prototype (ReDAC1) and on a 11-bit, 10.5 kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68 LSB (1.53 LSB) maximum INL, 1.54 LSB (1.0 LSB) maximum DNL, 76.4 dB (67.9 dB) THD, 79.7 dB (71.4 dB) SFDR and 71.3 dB (63.3 dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB). [ABSTRACT FROM AUTHOR]

A cascaded mode-switching sub-sampling PLL with quadrature dual-mode voltage waveform-shaping oscillator is proposed in this paper. The dual-mode voltage waveform-shaping oscillator is introduced to extend the tuning range and improve phase noise performance at mm-wave frequency, simultaneously. Meanwhile, the dual-mode quadrature topology is investigated to reduce the phase noise and quadrature phase error, compared to conventional quadrature oscillator. Then, the proposed oscillator is applied in a cascaded PLL with divider-less mode-switching sub-sampling loop, which can obtain the merits of high frequency-resolution, low loop noise, and wide frequency locking range. Both the dual-mode voltage waveform-shaping oscillator and the cascaded PLL are verified and fabricated in a 28-nm CMOS process. The FoM and FoMT of the oscillator at 10 MHz offset are −188.2 dBc/Hz and −200.7 dBc/Hz respectively. The proposed PLL prototype exhibits a frequency range from 22.8 to 33.9 GHz with a typical power consumption of 41.7 mW. The phase noise across the frequency band is from −104.1 to −108.2 dBc/Hz at 1 MHz offset. The jitter FoMj is −236.2 dB. [ABSTRACT FROM AUTHOR]

This paper proposes a novel T-type multilevel inverter (MLI) based on the switched-capacitor technique. The proposed inverter not only achieves that the maximum voltage stress of the switches is less than the input voltage but also has a voltage boost capability, which makes it suitable in high voltage applications. It is worth mentioning that the proposed inverter features two topology extension schemes which help it achieve a higher output level and voltage gain. With the merit of low voltage stress and reduced power devices, a seven-level inverter can be achieved using only two capacitors. Moreover, capacitor voltage self-balancing capability can simplify the complexity of the circuit and control. The topology, operating principle, modulation strategy and analysis of the capacitor of the inverter are presented. The superiorities of the proposed inverter are investigated by comparing with recently proposed hybrid MLIs and switched-capacitor MLIs. Finally, a seven-level prototype is constructed to validate the correctness of the theoretical analysis and the feasibility and effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design. [ABSTRACT FROM AUTHOR]

In this paper we are going to analyze the settling-time in single-, two- and three-stage amplifiers with the intent of deriving approximate but useful design equations that include the effects of the zeros and of the slew-rate limitations. The analysis is mainly devoted to the definition of an approach for the design of three-stage CMOS operational transconductance amplifiers from settling-time specifications. A design example is carried out to validate the proposed approach. [ABSTRACT FROM AUTHOR]

This paper presents the design and measurement of an RF energy harvesting and power management unit that operates across a wide range of available input power, from −24 to +15dBm. The system comprises an adaptive impedance matching network, a single-stage cross-coupled differential-drive rectifier, a start-up charge pump, an adaptive buck-boost converter, a maximum power point tracking (MPPT) circuit and a control loop to regulate the load voltage. The MPPT circuit controls the switching frequency of the buck-boost converter and configures the impedance matching network, optimizing the interfaces between the rectifier and antenna and between the rectifier and the storage capacitor, guaranteeing that the power is being harvested at maximum efficiency. To boost the rectifier output, to accumulate energy in the storage capacitor and to provide energy to the load, a single-inductor buck-boost converter that has two inputs and three outputs is used. Circuit techniques that reduce the power consumption of the control circuits and that allow for adapting the interfaces between the antenna, the rectifier and the load are presented. The peak harvesting efficiency of the system is 40.2%, when presented with an RF source of -9.1dBm available power and 403.5MHz frequency. [ABSTRACT FROM AUTHOR]

A design methodology for making magnetic coupling wireless power transfer (MC-WPT) systems resonate at given frequencies is proposed in this paper. Proposing such a method not only can improve the energy efficiency against frequency splitting, but also can satisfy the requirement of frequency standards and then promote its industrial application. The method is based on eigenvalues configuration and comprehensively considers all electric parameters. The quantitative relationship between the performance indexes and electric parameters is derived, based on which the expected electric parameters can be quickly and accurately determined. The design theory and design flow are provided, and practical systems are designed, simulated and measured to show the effectiveness of the proposed method. The results show that the proposed method can: 1) eliminate frequency splitting to make MC-WPT systems resonate at a given frequency; 2) utilize frequency splitting to make MC-WPT systems resonate at two given frequencies. [ABSTRACT FROM AUTHOR]

This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about 11% compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced 15% at the same frequency. The prototype structures are fabricated in a standard 65 nm CMOS technology and measurements demonstrate that the proposed CCO operates from 0.7 – 1.2 V supply with maximum frequencies of 80 MHz and energy/cycle ranging from 0.11 – 0.38 pJ over the tuning range. Further, system level simulations show that the nonlinearity in current-frequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear analytical model for an inverter-based switched-capacitor Class-D RF power amplifier (SCDPA). The root causes of the SCDPA AMAM and AMPM nonlinearities are studied. The major factors affecting SCDPA nonlinearities are identified as the unequal on-resistances of selected cell and unselected cell. Specifically, time-varying resistance of the switch, different transistor responses during the transition and parasitic resistance on the supply path (IR drop) are analyzed. Then, the system-level result, like EVM and power spectral density, can be obtained with nonlinear behavior of PA. The results of model calculation, schematic simulation, and measurement are presented and compared with validate the model both on transistor level and system level. This paper, for the first time, provides an accurate design guidance to enable fast architecture study and quick circuit-level prototype with close-to-optimum component initial parameters. It can be expanded to more architectures, therefore helps to pave the path to future design automation for highly linear SCDPAs. [ABSTRACT FROM AUTHOR]

Device mismatch is a key concern for high-resolution data converters. This paper presents a comprehensive study of the error-feedback (EF)-based mismatch error shaping (MES) technique. EF MES overcomes the key challenge of the classic dynamic element matching-based MES whose complexity grows exponentially with the number of bits; however, the prior EF MES comes with the limitations of limited shaping capability and reduced dynamic range. This paper demonstrates how to perform more advanced EF MES for various types of data converters. Moreover, this paper also proposes the use of digital prediction to address the dynamic range loss issue. [ABSTRACT FROM AUTHOR]

This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8–3.3-V, 0.18- $\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm2 output power density, and good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

In this paper, four control strategies for DC-DC buck converters are proposed, compared and analyzed: a single-loop adaptive control strategy (SA), a double-loop adaptive control strategy (DA), a single-loop disturbance observer-based control strategy (SDOB) and a double-loop disturbance observer-based control strategy (DDOB). First, the nominal system without considering the parametric uncertainties of the DC-DC buck converter is built to help develop the SA and DA. The SA is built by adaptive and backstepping control approaches, and the DA is set up by adaptive and sliding mode control approaches. Additionally, a model considering parametric uncertainties is introduced, giving the opportunity to develop the SDOB and DDOB. The SDOB is developed using a designed disturbance observer and backstepping control technique, and the DDOB is synthesized using a designed disturbance observer and sliding mode control method. Finally, the advantages and disadvantages of the four proposed control strategies are compared and analyzed through experiments. [ABSTRACT FROM AUTHOR]

This paper presents a novel CMOS peak detect and hold (PDH) circuit scheme for pulsed time of flight (ToF) Lidar application. The proposed PDH circuit, which is one part of analog front end (AFE) circuit of Lidar receiver, is used to widen the narrow input pulse width, aiming to easily digitize the pulse amplitude through a low-speed and low-cost ADC in pulsed ToF Lidar application. The reset voltage clamped to the common-mode level of the input pulse voltage is beneficial to reduce the pedestal error voltage. Meanwhile, the auto-adjust charging current scheme is employed to decrease the peak error through rejecting the overshoot voltage in the proposed PDH circuit. The circuit was implemented and fabricated in a 65-nm CMOS technology. The proposed PDH circuit can detect the pulse voltage with a pulse amplitude range from ~20 mV to ~500 mV and a minimum pulse width of 5 ns. The measured results show that the maximum absolute and relative errors are less than 16 mV and 4.5%, respectively. The layout area of the proposed PDH circuit is equal to $0.17\times 0.14$ mm2. [ABSTRACT FROM AUTHOR]

This paper proposes a high area-efficiency 14-bit column-parallel successive approximation register (SAR) analog-to-digital converter (ADC) for array sensors. A novel hybrid capacitor digital-to-analog converter (CDAC) based on the charge transfer is utilized to increase the area efficiency. It consists of a 9-bit split CDAC and a 5-bit serial CDAC. A foreground digital calibration is employed to compensate for the linearity error caused by the capacitor mismatch and bridge parasitic capacitor. The prototype was designed and fabricated in a 130-nm CMOS technology. Sampling at 200KS/s, the total power consumption is $57~\mu \text{W}$. With the digital calibration, the proposed ADC achieves the Spurious Free Dynamic Range (SFDR) of 89.14 dB and the Differential Nonlinearity (DNL) of 0.87/-0.99 LSB. The single ADC occupies an active area of $15\times 1450\,\,\mu \text{m}^{2}$ and the area efficiency is only $6.77~\mu \text{m}^{2}$ /code. [ABSTRACT FROM AUTHOR]

First-in first-out (FIFO) queues are ubiquitous building blocks in modern system-on-chips. Big FIFOs are often realized as static random access memories (SRAMs), and in many cases account for a significant portion of the area and power consumption of integrated circuits (ICs). Gain-cell embedded DRAM (GC-eDRAM) technology is an embedded memory alternative to the pervasive SRAM technology in ICs. It consumes less silicon area and less power than SRAM, but has the drawback of access blockage caused by its periodic data refreshing. In this paper we leverage the unique access patterns implied by the FIFO scheme to design a FIFO realized with GC-eDRAM. We show that such a FIFO is functionally indistinguishable from a FIFO realized with SRAM. The proposed FIFO has no access blockage time due to refresh, and no data integrity issues, and so can be used as an out-of-the-box replacement for FIFOs in existing and future designs, while providing as much as a $2\times $ reduction in both area and power as compared to SRAM. [ABSTRACT FROM AUTHOR]

In this paper, we propose a fully-integrated reconfigurable charge pump in a 0.18- $\mu \text{m}$ CMOS process; this converter is applicable for self-powered Internet-of-Things applications. The proposed charge pump uses a two-dimensional frequency modulation technique, which combines both the pulse-frequency modulation (PFM) and pulse-skip modulation (PSM) techniques. The PFM technique adjusts the operating frequency of the converter according to the variations in the load current, and the PSM technique regulates the output voltage. The proposed two-dimensional frequency modulation technique can improve the overall power conversion efficiency and the response time of the converter under light load conditions. A photovoltaic cell was chosen as the input source of the proposed converter. To adapt to the variations in the output voltage of a photovoltaic cell under different light illumination intensities, we built a reconfigurable converter core with multiple power conversion ratios of 2, 2.5, and 3 for the regulated output voltage of 1.2 V when the input voltage ranged from 0.53 V to 0.7 V. Our measurement results prove that the proposed capacitive power converter could achieve a peak power conversion efficiency of 80.8%, and the efficiency was more than 70% for the load current that ranged from $10~\mu \text{A}$ to $620~\mu \text{A}$. [ABSTRACT FROM AUTHOR]

This paper presents a switched capacitor network (SCN)-based bandgap voltage reference (BGR) circuit designed and implemented in a 65nm standard CMOS process with a wide temperature range, high precision, low supply voltage and low power consumption for IoT device application. The proposed BGR employs a 2x charge pump with ripple optimization design to supply the ${V} _{\mathbf {EB}}$ generator, which can relax ${V} _{\mathbf {DD}}$ from 0.9V to 0.5V.A proportional to absolute temperature (PTAT) current source is proposed to bias the PNP BJT in order to reduce the nonlinearity of ${V} _{\mathbf {EB}}$. Moreover, a voltage divider SCN with low leakage consideration to form the complementary to absolute temperature (CTAT) voltage is designed to reduce the nonlinearity of its coefficient, while a series-parallel SCN with adjusted clock swing to form the PTAT voltage is designed to improve the line regulation of the BGR. The measurement result shows that the proposed BGR has a temperature coefficient (TC) of 42 ppm/°C at 0.5V supply within −40 °C to 120 °C. The line regulation is 3.2mV/V or 0.64%/V from 0.5V to 1V. Based on 6-chip test result, it shows a $3\sigma / \mu $ variation of 3.08% before trimming, while 0.36% after trimming. [ABSTRACT FROM AUTHOR]

This paper presents an NMOS digital low-dropout regulator (LDO) with fast transient response and ultra-low quiescent current, to provide a tunable power supply for near-threshold voltage computing circuits in internet-of-things (IoT) devices. An LDO with an NMOS power transistor can enjoy the intrinsic fast transient response of the source-follower-like power stage, contributing to the proportional (P) part of the control loop. A shift-register-based digital control serves as an excellent candidate for the integral (I) part of the control loop. In addition, we propose a NAND-gate-based high-pass analog path (NAP) as the derivative (D) part of the loop, making the whole control scheme a complete PID control, therefore, achieving a fast transient response. We fabricated two versions of the prototype chip, one with a 35 pF on-chip load capacitor and a fast-transient on-chip load, and the other with no load capacitor, in 28-nm CMOS. The proposed NMOS digital LDO with NAP can handle the load transient of 160 mA/ns with 810-nA quiescent current, achieving 117-mV voltage undershoot. With the proposed techniques, we can achieve nearly two orders of better FoM when comparing it to the state-of-the-art works. [ABSTRACT FROM AUTHOR]

This paper introduces a 12 bit 2.5 bit/cycle SAR-based pipeline ADC employing a self-bias gain boosting amplifier. The single-stage amplifier achieves a low-frequency gain of 37 dB, while consuming 1.3 mW of power consumption with 1.3 V of analog power supply. A 2.5 bit/cycle SAR ADC realizes as the sub-ADC in each stage, and reduces both power consumption and silicon area. A two-channel sampling architecture is employed to double the sampling rate and thereby maximize circuit efficiency. A digital calibration technique is used to reduce non-linearity and mismatches due to the RDAC, as well as gain error and offset of the open-loop residue amplifier. The prototype ADC was fabricated in TSMC 40-nm technology, and consumes 10.71 mW with 1.1 V / 1.3 V digital / analog power supplies. When operating at 125 MS/s, the ADC achieves an SFDR of 66.59 dB before calibration and 80.3 dB after calibration when measured at Nyquist frequency. The experimental results show a Walden FoM of 101 fJ/c.-s. before calibration and 47 fJ/c.-s. after calibration. [ABSTRACT FROM AUTHOR]