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In this paper, we describe a design of a mixed-signal circuit for an binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication [ABSTRACT FROM AUTHOR]

The performance of nanoscale semiconductor technologies has become susceptible to high temperatures and aging phenomena. While guard-bands have conventionally been used to combat degradation-induced timing violations, approximations have recently been leveraged to compensate for degradations in lieu of adding timing guard-bands, without a loss in performance. However, only simple approximation techniques such as truncation have been considered in prior work. In this paper, a wide range of approximate arithmetic circuits including adders and multipliers using various sophisticated approximation techniques are investigated to cope with aging- and temperature-induced degradations. To this end, approximate circuits are first characterized for their delay increase under degradations. With this, we then determine the approximation level required to compensate for guard-bands under different degradations. Degradation-aware logic synthesis results show that the simple use of truncated arithmetic circuits leads to a higher quality loss compared to using other approximate circuits. However, a truncated multiplier has the lowest error distance towards a reliable operation in 10 years. The approximate multipliers with configurable error recovery are most suitable when the level of degradation is higher, e.g., at a temperature of 70 °C. The characterization of degradation at the circuit level is then used for design exploration at the architecture level without the need for further gate-level simulations. For three different image processing applications, experimental results show that guard-bands can be mitigated while maintaining an output result with a high visual quality. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations. [ABSTRACT FROM AUTHOR]

Single-electron transistors (SETs) exhibit a unique characteristic of Coulomb oscillation which can find many digital applications with area efficiency. More specifically, both MOS and SET devices can be used to implement XOR gates with almost the same area costs regardless of the number of their inputs, outperforming pure CMOS solutions. As multiple-input XOR gates are abundant in the finite field polynomial multiplication which represents the most frequent computation in elliptic curve cryptosystem, hybrid SET-MOS technology can substantially reduce the area cost for this application. This paper presents polynomial multiplication architectures with hybrid SET-MOS transistors and explores Karatsuba-algorithm based multiplication for further area optimization. Simulations show that the proposed hybrid SET-MOS implementations can typically provide around 37% savings in terms of gate count compared to their traditional CMOS counterparts. [ABSTRACT FROM AUTHOR]

This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads ($\text{C}_{\mathrm {L}}$) and operating frequencies (${f}_{\mathrm {s}}$). The circuit consumed a power between 610 $\mu \text{W}$ and $850~\mu \text{W}$ across the measured deadtime ranges while $\text{C}_{\mathrm {L}} =12$ pF, $\text{V}_{\mathrm {dd}} =3.3$ V, and $\text{f}_{\mathrm {s}}=200$ kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of $150\mu $ m $\times 260\mu \text{m}$. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum $\text{T}_{\mathrm {DLH}}$ and optimal $\text{T}_{\mathrm {DHL}}$ at $\text{I}_{\mathrm {Load}} =25$ mA is improved by 12% compared to a converter with a fixed deadtime of $\text{T}_{\mathrm {DLH}} =\,\,\text{T}_{\mathrm {DHL}} =12$ ns. [ABSTRACT FROM AUTHOR]

This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm2. The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported. [ABSTRACT FROM AUTHOR]

This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC’s resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. [ABSTRACT FROM AUTHOR]

Recent studies on integrated circuits interconnections are mainly concentrated on the analysis of crosstalk and delay, by taking the trade-off between accuracy, speed, and complexity into consideration. The new idea of this paper is to apply the convex optimization method to analyze crosstalk and delay of the lossy coupled interconnections in identical and non-identical forms. For this purpose, a simple and comprehensive model is proposed to cover the functional and dynamic crosstalk in a computationally-effective way. More specifically, various case studies are determined to analyze the transient response of the coupled transmission lines with arbitrary excitation sources in the presence of both capacitive and inductive coupling characteristics. To validate the model, the numerical and Advanced Design System (ADS) simulation results are compared to indicate the desired accuracy. The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively. In addition, the computational speed of the proposed method is about twice higher than ADS and HSPICE. The proposed model is extendible to handle ${N}$ coupled lines, making it appropriate to model complex integrated circuit interconnections. [ABSTRACT FROM AUTHOR]

Computing systems working in harsh environment is prone to suffer from radiation-induced soft errors; for example, Single Event Upsets (SEUs) and Single Event Transients (SETs) are the major reliability issue for circuits fabricated with nanoscale technology nodes. In this paper, we proposed a low-cost SET and SEU error tolerant flip-flop (SETU-TOFF). Based on the traditional flip-flop, two high-level sensitive redundant latches are added to latch the input data at different times, and a voter is designed for the correct output. It removes the timing overhead of temporal redundancy from the critical path of the systems. Comparing with the existing designs presented in literatures, SETU-TOFF has comprehensive fault tolerant capability with lower overheads; moreover, it doesn’t increase significant latency of the flip-flops. We use the SETU-TOFF cells to protect a pipeline of an OpenRISC microprocessor. Fault injection simulations show that SETU-TOFF can achieve 100% protection for the pipeline with negligible performance loss; additionally, it can detect and correct errors in real time without extra system control logic and clocks for errors recovery. [ABSTRACT FROM AUTHOR]

This paper proposes a distributed cooperative control strategy for cyber-physical microgrids in a distributed sparse network with communication delays by using predictive control theory, which enables each distributed generator (DG) unit to achieve voltage restoration. In the proposed control strategy, we first design a primary droop-free model predictive controller to make the output voltage track its nominal set points timely, with the neighbor-based error information a secondary distributed coordinated predictive controller is then proposed to actively compensate the general communication delays for cyber-physical microgrids caused by low-bandwidth communication networks. Sufficient conditions, in terms of communication network connectivity and control gains for the system stability are derived by using the tools of special matrix theory and algebraic graph theory. The proposed control protocols are fully distributed and can be implemented through a sparse communication network and thus, satisfy the plug-and-play feature of the future smart grid. The effectiveness of the control strategy in compensating communication delays is also verified by real-time simulation experiments in OPAL-RT on a test microgrid. [ABSTRACT FROM AUTHOR]

This paper presents a new architecture, based on CORDIC and parabolic synthesis methodology, for computing Nth root of a complex number. The proposed architecture uses the pretreatment for normalization and parabolic synthesis method to calculate the Nth root of modulus of the input complex number and performs the conversion between the plane coordinate form and the polar coordinate form of the complex number by CORDIC, which not only ensures the accuracy but also has an ultra-low computation latency. MATLAB simulation result indicates that our proposed method can calculate the Nth root of the complex numbers in the form of fixed-point number with an error of $2.16 \boldsymbol {\times {10^{ - 6}}}$. Under TSMC 40nm CMOS technology, the report shows that the area consumption is $27390.72 \boldsymbol {\mu m^{2}}$ at the frequency of 1GHz and the power consumption is 2.3549mW. More importantly, the computation latency of the proposed architecture is only 60.18% of the latest architecture in the same calculation accuracy. [ABSTRACT FROM AUTHOR]

This paper deals with global synchronization problem of multiple discrete-time Markovian jump memristor-based neural networks (DTMJMNNs) with mixed mode-dependent delays via a novel event-triggered impulsive coupling control (ETICC). The parameters of the multiple DTMJMNNs and the mixed time delays (both discrete and distributed delays) switch randomly according to a Markov chain. In the ETICC strategy, the controller does not work all the time, but only works at impulse instants determined by specific events. In particular, the coupling matrix can be non-Laplacian. By using the Lyapunov stability theory, linear matrix inequalities (LMIs), and the Kronecker product, some sufficient conditions for global synchronization of multiple DTMJMNNs under the event-triggered strategy are derived. Two examples are presented to test the validity of the theoretical analysis results. [ABSTRACT FROM AUTHOR]

This paper proposes to utilize intentional time delays as part of controllers to improve the damping of electromechanical oscillations of power systems. Through stability theory, the control parameter settings for which these delays in Power System Stabilizers (PSSs) improve the small signal stability of a power system are systematically identified, including the key parameter settings for which stability regions in the parameter plane remain connected for effective operation. The paper shows that PSSs with two control channels can be effectively designed to achieve best damping characteristics for a wide range of delays. Analytical results are presented on the One-Machine Infinite-Bus (OMIB) electromechanical power system model. To demonstrate the opportunities in more realistic dynamic models, our results are then implemented via numerical analysis on the IEEE standard 14-bus system. [ABSTRACT FROM AUTHOR]

With the advancement of technology, the size of transistors and the distance between them are reducing rapidly. Therefore, the critical charge of sensitive nodes is reducing, making SRAM cells, used for aerospace applications, more vulnerable to soft-error. If a radiation particle strikes a sensitive node of the standard 6T SRAM cell, the stored data in the cell are flipped, causing a single-event upset (SEU). Therefore, in this paper, a Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T (SARP12T) SRAM cell is proposed to mitigate SEUs. To analyze the relative performance of SARP12T, it is compared with other recently published soft-error-aware SRAM cells, QUCCE12T, QUATRO12T, RHD12T, RHPD12T and RSP14T. All the sensitive nodes of SARP12T can regain their data even if the node values are flipped due to a radiation strike. Furthermore, SARP12T can recover from the effect of single-event multi-node upsets (SEMNUs) induced at its storage node-pair. Along with these advantages, the proposed cell exhibits the highest read stability, as the ‘0’-storing storage node, which is directly accessed by the bitline during read operation, can recover from any upset. Furthermore, SARP12T consumes the least hold power. SARP12T also exhibits higher write ability and shorter write delay than most of the comparison cells. All these improvements in the proposed cell are obtained by exhibiting only a slightly longer read delay and consuming slightly higher read and write energy. [ABSTRACT FROM AUTHOR]

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell. [ABSTRACT FROM AUTHOR]

In the Mesochronous Pipeline (MP), the clock period is the maximal of differences between the maximum/minimum delays of all stages. This value is less than the maximum delay between the memory elements, so MP is operating faster than the conventional pipeline (CP). To take full advantages of MP, in this paper, Automated Mesochronous Pipeline Scheduler (AMPS) for high performance digital circuits, is proposed which provides all allowed partitioning options generated by register allocation procedures obtained with varying maximum delay differences of stages. This allows a designer to select from design space produced by AMPS based on the desired specification. Unlike the traditional MP, AMPS utilizes automated scripts to extract the timing characteristics of the synchronizers and gates. This enables a designer to explore trade-offs between latency, power, and frequency. To evaluate our toolset, an 8-bit Carry Increment Adder (CIA), a 4-bit Binary-Coded Decimal (BCD) adder, a 4-bit ALU, and a set of circuits from ISCAS85 and ISCAS89 benchmarks are considered. All circuit level simulations are performed in the 65nm CMOS standard technology node. AMPS improves the frequency for its best solutions about 127.94% (on average) in comparison to the conventional pipeline scheme. [ABSTRACT FROM AUTHOR]

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1st-order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account. [ABSTRACT FROM AUTHOR]

This paper presents a time-interleaved analog-to-digital converter mismatch calibration, which can be adapted to any interleaving factor and calibrate offset, gain, time skew and bandwidth mismatches. Moreover, the proposed scheme utilizes a non-return-to-zero pilot signal, avoiding the high-resolution requirements of sinusoidal generators. In addition, there are no multiplications in the detection path in contrast with the state-of-the-art approaches. Consequently, the proposed calibration presents the smallest complexity in terms of hardware requirements compared to previous work (to the author’s knowledge). Therefore, the proposed calibration can be made with the smallest area and power consumption. Numerical simulations show an SNDR improvement of 49.52 dB for a 12-bit 4-channel TI-ADC and an SNDR improvement of 29.64 dB for an 8-bit 32-channel TI-ADC when random mismatches are applied. The measurement results show an SNDR improvement of 24.68 dB for a 3.6 GS/s 2-channel TI-ADC experimental board. [ABSTRACT FROM AUTHOR]

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to periodically realign the clock phase to the rising edge of data. The frequency information is extracted by comparing the rising edge of the data and the clock after aligning the phase using a bang-bang phase detector (BBPD). Additionally, a low power injection-locked two-stage ring digitally controlled oscillator (ILDCO) is employed to provide four-phase quadrature clock and significantly reduce the power consumption. Based on the proposed architecture, the fabricated CDR consumes only 5.8 mW from a 0.9 V supply, while being able to extract the clock signal from 6.15 to 10.9 Gb/s input data with a measured jitter tolerance (JTOL) of 0.15 UIpp at the highest frequency, indicating that the CDR meets the OC-192 mask. Furthermore, the proposed CDR demonstrates a substantial improvement in the power efficiency of 0.58 pJ/bit. [ABSTRACT FROM AUTHOR]

Quasi-consensus tracking problems of uncertain multi-agent systems are investigated in this paper. By integrating impulsive control theory with event-triggered mechanism, a new hybrid event-triggered impulsive consensus protocol is presented, under which the information transmission of agents occurs at a sequence of state-dependent instants. Based on Lyapunov method, several quasi-consensus criteria of uncertain multi-agent systems are constructed, as well as the relation among control gains, event parameters, consensus error level, and convergence rate is established. It shows that the hybrid event-triggered control strategy benefits to save the energy cost of information transmission and control cost between agents compared with the time-triggered scheme, and it is effective to achieve quasi-consensus tracking objective of considered systems. Finally, the Zeno behavior is shown to be ruled out, and some simulation examples are proposed to demonstrate the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

To improve the voltage and power sharing of distributed generations, the hierarchical controls are widely used in microgrids while the dependent communication network makes it difficult to ensure the performance under limited bandwidth. In this paper, a predictive voltage hierarchical controller is designed. With the delayed secondary PI compensation signals, an inner-loop robust control is designed in the primary controller, ensuring stable voltage tracking. Then, a predictive controller is designed to provide neighbor and local predictions, such that the data integrity is improved by an accurate predictive compensation under bidirectional data-loss. Final case study results verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Although the cyber-physical system stability is widely studied, scholars focus more on system stability with communication time delay. Therein, grid-connected inverters with the digital control system are regarded as one simplest and typical cyber-physical system. Meanwhile, the switching/sampling frequency of the inverter is always selected as low as possible from an efficiency viewpoint, resulting in unavoidable delay time. This delay time is apt to cause the system instability, which is more prone to severity under weak grid. To this end, this paper provides a minimum switching/sampling frequency for grid-connected inverters. Firstly, the system impedance model with equivalent delay time is constructed, which is based on padé approximate approach. This equivalent delay time consists of three parts, i.e., sampling delay time in cyber/physical level, calculation delay time in cyber level and pulsewidth modulation delay time in physical level, which reflects the cyber-physical interaction impact. Furthermore, the stability forbidden criterion is applied to make the switching/sampling frequency solving process become Hurwitz matrix identification problem through space mappings. Based on these space mappings, an adaptive step search approach is adopted to obtain the minimum switching/sampling frequency. Finally, the proposed approach can well evaluate the system stability under different frequencies through simulation and experiment. [ABSTRACT FROM AUTHOR]

This paper presents signal-independent background calibration for timing errors in time-interleaved ADCs, using a random ramp-based calibration signal. A prototype 10-b 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the SNDR is 50.1 dB at Nyquist while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Freezing the calibration after convergence improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step. [ABSTRACT FROM AUTHOR]

As is known to all that the Lyapunov-Krasovskii functional (LKF) has played a vital role in studying the fixed-time (FXT) stability of the time-delayed Filippov discontinuous systems. When investigating the FXT stability of the time-delayed discontinuous systems, the interesting topic is to provide the more relaxed conditions imposed on the LKF and obtain the more accurate settling-time (ST). This paper aims to investigate the new FXT stability lemma with more relaxed conditions for the time-delayed Filippov discontinuous systems. By using some novel inequality techniques and analytical methods, the new FXT stability lemma is established and more accurate ST is estimated. The traditional discussion about $0 < V < 1$ and $V \geq 1$ is not required. For the purpose of validation, FXT stabilization of discontinuous inertial networks with mixed time delays is considered. By using differential inclusions theory and the new FXT stability lemma, the delay-dependent FXT stabilization criteria are derived. It is the first time to derive the delay-dependent FXT stabilization criteria for the discontinuous inertial networks. Finally, examples are given to show the effectiveness of the established results. [ABSTRACT FROM AUTHOR]

In this paper, the robust $H_{\infty }$ control problem is studied for the inductively coupled power transfer (ICPT) process with coil misalignment, energy bounded interference and time-varying delay. The problem of coil misalignment between the primary and secondary coils are considered, and the time varying coupling coefficient are described in a sojourn-probability-based switch model. A set of random variables are utilized to describe the sojourn probabilities of the finite modes of the coil misalignment. It should be pointed out that the sojourn probability of the $i$ th subsystem is obtained by the off-line statistical test instead of prescribed by hand, which is of more closer physical significance due to its engineering practice. Corresponding to the proposed switching systems, a set of controllers with time-varying delays are constructed. By resorting to the Lyapunov stability theory, the matrix analysis, and the stochastic analysis tools, the delay-dependent sufficient criteria with less conservatism are derived to guarantee the mean square stability of the ICPT system and the given interference attenuation level $\gamma $. The feedback gains of the desired controller can be readily obtained by using the control toolbox in Matlab software. Three cases of the illustrative examples without exception verify the effectiveness of the suggested modeling method and control scheme. [ABSTRACT FROM AUTHOR]

This paper aims to investigate the event-based extended dissipative state estimation problem for memristor-based Markovian neural networks in the presence of hybrid time-varying delays and sensor nonlinearity. To tackle the effect caused by information latching, sudden interference and environmental variation, the Markov jump model is employed to describe the memristor-based neural network. Besides, an event-triggered scheme is introduced to economize the cost of communication. Then some novel conditions are presented, which guarantee that the augmented error system is stochastically stable with an extended dissipative performance. The existence criterion of the desired mode-dependent estimator is also obtained in terms of linear matrix inequalities. Finally, simulation results are provided to show the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Channel emulator is an important tool to evaluate communication system performance at the physical link, and network levels. In this paper, a new discrete 3D non-stationary geometry-based stochastic model (GBSM) for UAV to vehicle (U2V) channels is proposed, which considers 3D scattering space, 3D trajectory, and 3D antenna array. And a tailed channel emulator is developed on a field programmable gate array (FPGA) platform. All channel parameters, i.e., the power, delay, and phase are calculated by FPGA hardware for the first time instead of software or pre-storage method. Meanwhile, a Greedy CORDIC-based exponential calculation method for generating massive complex sinusoids is designed and implemented. The latency is reduced by 50% than traditional CORDIC method. By further utilizing the compact architecture with time division scheme, the hardware resource is significantly reduced from 16.51% to 7.55% for 16-bit data width. Meanwhile, the fixed-point output statistical properties are also derived for quantitatively validation. Finally, the U2V channel under the campus scenario is reproduced by the proposed emulator. The generated results demonstrate that the statistical properties are consistent well with the theoretical and ray tracing ones, which verifies the correctness of both proposed channel model and emulator. [ABSTRACT FROM AUTHOR]

Approximate computing is an efficient approach for reducing computational costs. This method involves a trade-off between computational accuracy and the circuit’s power consumption, delay, and area. However, the accuracy requirements may differ for different applications. In some situations, precise results are required. Therefore, this paper proposes an accuracy-configurable radix-4 adder (ACRA), which uses the power gating technique to turn on or turn off the partial logic gates of an adder element dynamically to compute accurate or approximate results. When the ACRA operates in the approximate mode, the partial sum of one adder element is modified to reduce the error distance between the approximate and accurate results. A comparison of the ACRA with two state-of-the-art accuracy-configurable adders indicated that the ACRA achieved the best trade-off between the power–delay product and computational accuracy. In addition, in the image processing experiment conducted in this study, under half-approximate computation, the peak signal-to-noise ratio of the ACRA was less than 1 dB and its structural similarity index measure was maintained above 0.99. These results are superior to those obtained for other accuracy-configurable adders. [ABSTRACT FROM AUTHOR]

Ring oscillators, with capacitive load intended for frequency tuning, can fail to sustain stable oscillations. Failure depends on the size of the load capacitors and their equivalent series resistance. This paper first describes the failing mechanism from an intuitive perspective. It then develops an analytical model and provides the equations for the minimum load capacitance and the range of equivalent series resistance at which the ring oscillator fails. The dependency on the number of stages of the ring oscillator as well as the trans-conductance and impedance of its gain stages are also examined. Confirmed by simulations, the model shows that the failing region reduces significantly for ring oscillators with 7 or more stages but that it can be a serious concern for 5 and especially 3-stage ring oscillators. [ABSTRACT FROM AUTHOR]

This paper implements a wide aperture high-resolution true time delay for frequency-uniform beamforming gain in large-scale phased arrays. We propose a baseband discrete-time delay-compensating technique to augment the conventional phase-shift-based analog or hybrid beamformers. A generalized design methodology is first developed to compare delay-compensating analog or hybrid beamforming architecture with their digital counterpart for a given number of antenna elements, modulation bandwidth, ADC dynamic range, and delay resolution. This paper shows that delay-compensating analog or hybrid beamformers are more energy-efficient for high dynamic-range applications compared to true-time-delay digital beamformers. To demonstrate the feasibility of our proposed technique, a four-element analog delay-compensating baseband beamformer in 65-nm CMOS is prototyped. A time-interleaved switched-capacitor array implements the discrete-time delay-compensating beamformer with a wide delay range of 15-ns and 5-ps resolution. Measured power consumption is 47 mW with frequency-uniform array gain over 100-MHz modulated bandwidth, independent of angle of arrival. The proposed delay compensation scheme is scalable to accommodate the delay differences for large antenna arrays with higher range/resolution ENOB compared with prior art. [ABSTRACT FROM AUTHOR]

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06 ×/1.08 ×/1.36 × shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03 ×/1.09 ×/1.12 ×/1.15 ×/1.17 × shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33 ×/1.6 ×/2.4 × higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13 ×/1.32 ×/1.37 ×/1.42 ×/1.5 × higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31 ×/2.42 ×/2.55 ×/3.04 × lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ VDD = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead. [ABSTRACT FROM AUTHOR]

This paper addresses the finite-time event-triggered control problem for nonlinear semi-Markovian switching cyber-physical systems (S-MSCPSs) under false data injection (FDI) attacks. Compared with the traditional time-triggered mechanism, the proposed event-triggered scheme (ETS) can effectively avoid network resource waste. Considering the network-induced delay in the modeling, a closed-loop system model with time delay is established in the unified framework. By the use of a mode-dependent piecewise Lyapunov-Krasovskii functional (LKF), stochastic finite-time stability (SFTS) criteria are established for the resultant closed-loop system. Then, some solvability conditions are established for the desired finite-time controller in light of a linear matrix inequality framework. Finally, an application example of vertical take-off and landing helicopter model (VTOLHM) is provided to demonstrate the effectiveness of the theoretical findings. [ABSTRACT FROM AUTHOR]

With the rapid development and globalization of the semiconductor industry, hardware security has emerged as a critical concern. New attacking and tampering methods are continuously challenge current hardware protection methods. Combating these powerful attacks is of great importance in securing hardware devices. This paper proposes a novel framework to protect Physical Unclonable Function (PUF) against modeling attacks, denominated as Noisy PUF (NoPUF). NoPUF exploits structural unpredictability to improve overall security. We present several PUF architectures under the proposed framework that could reconfigure a conventional reliable PUF to a noisy PUF. The reconfigured PUF becomes inherently unreliable and hence achieves a higher resistance against modeling attacks. Moreover, since only a small portion of the Challenge-Response Pairs (CRPs) are required for authentication, the designer can use the information obtained from the initial reliable PUF configuration to find CRPs, which are still reliable in the noisy PUF configuration for authentication. Exploiting such information asymmetry between designer and attacker is the nexus of the proposed NoPUF design methodology. Experimental results show that we can achieve a maximum attacker and designer accuracy difference of 44.79% for a 64-stage NoPUF candidate architecture while ensuring high reliability for selected challenges. [ABSTRACT FROM AUTHOR]

This paper presents a wide input range active rectifier using a bipolar-CMOS-DMOS (BCD) process with a high voltage conversion ratio (VCR) and high power conversion efficiency (PCE). The proposed rectifier ensures safe and robust operation under large input voltage variations, which can be caused by changes in the magnetic coupling or loading conditions. It supports an input voltage range 3–12 V with the adaptive delay-compensated active operation of the power switches. An active signal clamper and voltage-time hybrid gate control circuit with two compensation loops was proposed for the optimal gate transition of low-side NMOS switches. For high-side PMOS switches, a fully integrated low-power-consuming high-side driver is proposed to replace the conventional high-side gate driving structure. The proposed active rectifier was fabricated through a TSMC 0.18 μm BCD process. The measurement results show that the proposed rectifier achieves stable and well-delay-compensated active operation, resulting in a high VCR and PCE with a wide output power range from 4.5 to 288 mW. Peak VCR and PCE of 96.8% and 93.7%, respectively, were achieved. [ABSTRACT FROM AUTHOR]

Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains a serious challenge that motivates the support of multiple SFQ clock domains. Towards this end, this paper analyzes the impact of setup time violations and metastability in SFQ circuits comparing the derived analytical models to their CMOS counterparts. It also proposes new techniques to reduce the average latency in metastability-tolerant SFQ synchronizers, and evaluates their effects on the layout and critical margin of the design. It further extends the proposed model to estimate the Mean Time Between Failure (MTBF) of flip-flop-based synchronizers and shows that their MTBF with the current feature sizes is unaffected by noise, similar to CMOS. Finally, it curve fits this model to simulations using the state-of-the-art SFQ5ee process and shows that a two-flop SFQ synchronizer with a clock frequency of 25 GHz has an estimated MTBF of ~106 years. [ABSTRACT FROM AUTHOR]

The issue of finite-time stabilization (FTS) for the memristor-based inertial neural networks (MINNs) with mixed time-varying delays (MTVDs) is researched by virtue of a new analytical method in this brief. First, an appropriate reliable control strategy is proposed for MINNs, which takes the influence of actuator failures into account. Second, by combining Lyapunov functional theory with new analysis techniques, novel theoretical results to guarantee the FTS for the concerned MINNs are acquired, and the desired reliable controller gains are obtained simultaneously. In additions, compared with the previous research works, the FTS results obtained in this paper are established directly from the MINNs themselves without using variable transformation method. In the end, two simulations are exploited to show the correctness and practicability of the acquired theoretical results. [ABSTRACT FROM AUTHOR]

This article discusses methods of parametric and structural-parametric synthesis of resonators, which contain transmission line segments of the same length. These methods allow optimizing resonators of various configurations with different segments number $N$ and characteristic impedances $Z_{0i}$. We will call optimal resonators if they have a minimum ratio $m = Z_{\mathrm {0max}}/Z_{\mathrm {0min}}$ at given ratio between the critical frequencies (poles and zeros of the input impedance). The input impedances of the resonators under consideration at the Richards’ frequency variable $S$ are described by the reactance functions of $N$ degree: $Z^{N}(S)$. The parametric synthesis refers to stepped impedance resonators (SIRs). The structural-parametric synthesis refers to resonators of a more general form, which contain open- and short-circuited stubs. The methods are based on two states established in this paper: the order of the reactance function $Z^{N}(S)$ should be the minimum possible ($N = N_{\mathrm {min}}$) to implement the required ratio between certain critical frequencies; the characteristic impedances of the composite sections $Z_{0i}$ take only two values $Z_{\mathrm {0min}}$ or $Z_{\mathrm {0max}}$. These methods were used to synthesize different resonators useful for practical application. With the help of the structural-parametric synthesis, the resonators of a more complex configuration are synthesized, which significantly exceed SIRs. The results of the measurements and simulation are presented. [ABSTRACT FROM AUTHOR]

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about 11% compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced 15% at the same frequency. The prototype structures are fabricated in a standard 65 nm CMOS technology and measurements demonstrate that the proposed CCO operates from 0.7 – 1.2 V supply with maximum frequencies of 80 MHz and energy/cycle ranging from 0.11 – 0.38 pJ over the tuning range. Further, system level simulations show that the nonlinearity in current-frequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training. [ABSTRACT FROM AUTHOR]

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional- ${N}$ multiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48ps root-mean-square (RMS) jitter in fractional- ${N}$ and integer- ${N}$ modes, respectively. The fractional spur is less than −59.0dBc, and the reference spur is −64.5dBc. The power consumptions are 1.85mW and 1.22mW, corresponding to figures of merit (FOM) of −240.4dB and −245.5dB. [ABSTRACT FROM AUTHOR]

The key enabling factor for Spin Wave (SW) technology utilization for building ultra low power circuits is the ability to energy efficiently cascade SW basic computation blocks. SW Majority gates, which constitute a universal gate set for this paradigm, operating on phase encoded data are not input output coherent in terms of SW amplitude. Thus, their cascading requires information representation conversion from SW to voltage and back, which is by no means energy effective. In this paper, a novel conversion free SW gate cascading scheme is proposed that achieves SW amplitude normalization by means of a directional coupler. After introducing the normalization concept, we utilize it in the implementation of three simple circuits and, to demonstrate its bigger scale potential, of a 2-bit inputs SW multiplier. The proposed structures are validated by means of the Object Oriented Micromagnetic Framework (OOMMF) and GPU-accelerated Micromagnetics (MuMax3). Furthermore, we assess the normalization induced energy overhead and demonstrate that the proposed approach consumes $1.25 \times $ to $1.5 \times $ less energy when compared with the transducers based conventional counterpart. Finally, we introduce a normalization based SW 2-bit inputs multiplier design and compare it with functionally equivalent SW transducer based and 16nm CMOS designs. Our evaluation indicates that the proposed approach provided $1.34 \times $ and $6.25 \times $ energy reductions when compared with the conventional approach and 16nm CMOS counterpart, respectively, which demonstrates that our proposal is energy effective and opens the road towards the full utilization of the SW paradigm potential and the development of SW only circuits. [ABSTRACT FROM AUTHOR]

This paper develops fundamental limits of digital phased arrays and proposes to use this as a map for the future technology investment in this area. Phased arrays, which are becoming ubiquitous in everything from vehicles, to communication systems including cell phones, to drones, satellites, and of course military applications. There is a recent trend toward digital phased arrays where each element in the antenna array is digitized. This allows monolithic integrated circuit integration as well as providing new capability due to digital signal processing. Digital phased arrays are increasingly being implemented with reconfigurable logic. Digitization and reconfigurability comes at a cost of power, which is increasingly becoming the limitation in these systems. This paper develops the fundamental energy limits of digital computation, applies this to phased arrays, and discusses directions for potential future digital phased array development. [ABSTRACT FROM AUTHOR]

This paper presents an analytical method for the performance evaluation of the correlation-based impulse radio (IR) receivers, which detect the data based on synchronizing the received signal with a locally generated template pulse. In this paper, a phase interpolation technique is employed to preserve synchronization accuracy with low power consumption. The analytical method computes the spectral density of jitter at the phase interpolator output, resulting from both flicker and thermal noise components. The analysis considers the aliasing phenomenon due to the sampling of the noise to predict the induced jitter accurately. Bit error rate (BER) of the receiver is also statistically estimated in terms of the induced jitter on the template pulse, the noise effect of the receiver chain, and the template signal level. The proposed estimation procedure is validated by comparing its results with transient noise simulations. It is shown that increasing the template signal range in the correlator and improving the linearity of the phase interpolation transfer curve, at a given power consumption, enhances the receiver sensitivity by 2 and 3.5 dB, respectively. The BER estimation results also reveal that the effect of the template signal jitter on the sensitivity of the correlation-based IR receivers becomes dominant with the increasing input signal level. [ABSTRACT FROM AUTHOR]

In this paper, we are concerned with the finite-time synchronization of a class of inertial neural networks with time delays. Without applying some finite-time stability theorems, which are widely applied to studying the finite-time synchronization for neural networks, by constructing two Lyapunov functions and using integral inequality method, two sufficient conditions on the finite-time synchronization for a class of inertial neural networks with time delays are derived. Considering that the method and research results of the finite-time synchronization are different from some existing works, this paper extends the works on the finite-time synchronization of neural networks. [ABSTRACT FROM AUTHOR]

Manufacturing process variations and transistor’s aging effects are two major concerns for reliable design of nano-scale digital circuits. Correct functionality of flip-flops (FFs), as one of the most important elements in digital circuits, plays a key role in reliability of modern circuit designs. In this paper, a timing reliability improvement technique is proposed for master-slave FFs considering the impacts of process variations and aging effects. In this technique, the internal circuitry of the FF is restructured in order to improve the reliability by reducing the stress time (i.e. the time of being ON) of the transistors which are stacked in the feedback loop. Using Monte-Carlo based HSPICE simulations, the efficacy of the restructuring-based reliability improvement technique is shown considering various experimental conditions (i.e. different process variation ratios and lifetime values). The experimental results show that, the lifetime reliability of Master-Slave FFs improved by 22% in expense of 3% area overhead, 8% propagation delay absolute change, and 6% absolute power change in the presence of 20% variation ratio and 9 years of operation time. [ABSTRACT FROM AUTHOR]

Resampling technology is becoming increasingly critical, as different frequency components are required to be measured in one device. In this paper, a resampling method based on filter designed by window function is proposed to satisfy the requirements of different sampling rates. The frequency responses of the filter in the resampling model based on the Farrow structure are investigated, and the design criterion of the filter in the resampling model is proposed. A fractional delay filter design model based on window function method is established. A fractional delay filter coefficient matrix, which is expressed by a polynomial form, is constructed. Then, the expression related to the subfilter coefficients is obtained and subfilter coefficients are solved by the least-square method. The simulation results show that the filter designed by the proposed method has better performance when used for resampling as compared those designed by existing methods, and can efficiently prevent the occurrence of frequency aliasing and mirroring components in the process of sampling rate conversion. Therefore, the proposed method meets the conditions for application to existing measurement devices. [ABSTRACT FROM AUTHOR]

This paper investigates the issue of global robust ${H_\infty }$ pinning synchronization for a class of complex networks with sampled-data-based event-triggered communication via a pinning control approach. The complex network is subject to network-induced time-varying delays, parametric uncertainties and external disturbances. A directed and weighted communication topology is taken into account, and the phenomenon of uncertainties is reflected in both modelling and inner coupling matrices. In order to save communication resources, a new and practical event-triggered communication mechanism with an asynchronous sampling manner is developed, with which the Zeno behaviour can be absolutely avoided. Then, based on the presented event-triggered strategy, a pinning control protocol is proposed to reduce the frequency of controller updates and the computational burden. The problems on the minimal number and which of the nodes should be chosen are addressed. By Lyapunov stability theory, sufficient conditions are deduced to ensure the underlying network achieves global robust ${H_\infty }$ pinning synchronization. Finally, numerical examples are provided to verify the effectiveness of the new design techniques. [ABSTRACT FROM AUTHOR]

In this paper, we present a new approach to simplify fast Fourier transform (FFT) hardware architectures. The new approach is based on a group of transformations called decimation, reduction, center, move and merge. By combining them it is possible to transform the rotators at different FFT stages, move them to other stages and merge them in such a way that the resulting rotators are simpler than the original ones. The proposed approach can be combined with other existing techniques such coefficient selection and shift-and-add implementation, or rotator allocation in order to obtain low-complexity FFT hardware architectures. To show the effectiveness of the proposed approach, it has been applied to single-path delay feedback (SDF) FFT hardware architectures, where it is observed that the complexity of the rotators is reduced up to 33%. [ABSTRACT FROM AUTHOR]

In this paper, we propose a reduced complexity parallel least mean square structure (RC-pLMS) for adaptive beamforming and its pipelined hardware implementation. RC-pLMS is formed by two least mean square (LMS) stages operating in parallel (pLMS), where the overall error signal is derived as a combination of individual stage errors. The pLMS is further simplified to remove the second independent set of weights resulting in a reduced complexity pLMS (RC-pLMS) design. In order to obtain a pipelined hardware architecture of our proposed RC-pLMS algorithm, we applied the delay and sum relaxation technique (DRC-pLMS). Convergence, stability and quantization effect analysis are performed to determine the upper bound of the step size and assess the behavior of the system. Computer simulations demonstrate the outstanding performance of the proposed RC-pLMS in providing accelerated convergence and reduced error floor while preserving a LMS identical $O(N)$ complexity, for an antenna array of $N$ elements. Synthesis and implementation results show that the proposed design achieves a significant increase in the maximum operating frequency over other variants with minimal resource usage. Additionally, the resulting beam radiation pattern show that the finite precision DRC-pLMS implementation presents similar behavior of the infinite precision theoretical results. [ABSTRACT FROM AUTHOR]

This paper presents a compact and low-power time-domain CMOS temperature sensor intended for Internet of Things. To eliminate the off-chip reference clock that is commonly needed for time-domain CMOS temperature sensors, a precise on-chip reference clock is designed to measure the temperature-dependent delay generated by an inverter chain with even stages. In the reference clock circuit, a relaxation oscillator showing discharging phases with negative temperature coefficient (TC) is designed, which are compensated by 2 identical inverter-chains with positive-TC delay, resulting in a reference clock with nearly temperature-independent pulse width and period. In addition, a $2^{{\text {nd}}}$ -order hybrid time-voltage delta-sigma ($\Delta \Sigma $) modulator with feedforward path is proposed to quantize the temperature-dependent delay of the main inverter chain, achieving 100-mK resolution only in about 25-ms conversion time. Fabricated in 0.18- $\mu \text{m}$ CMOS, measurement results show that the best (worst)-case temperature accuracy of the clock’s reference time is ±0.015% (±0.055%) and the temperature sensor achieves a maximum inaccuracy of +0.66/−0.73 °C from −20 °C to −80 °C. The prototype occupies 0.45-mm2 chip area and consumes 1.99- $\mu \text{W}$ from a 1.8-V supply at room temperature. [ABSTRACT FROM AUTHOR]