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The authors have proposed two methods for iron loss evaluation of the ac filter inductor used in a pulsewidth modulation (PWM) inverter. The first method is a loss map method, which can be used for the iron loss calculation of the ac filter inductor without using a real PWM inverter, and the second method is an iron loss analyzer (ILA), which can measure the iron loss of the ac filter inductor during every switching period on a real PWM inverter. In this paper, the measurement results obtained using the ILA and the results calculated using the loss map method on both the single-phase and three-phase inverters are compared. The calculated iron loss of the ac filter inductor on the three-phase PWM inverter is found to have a relatively large error for certain PWM pulse conditions. In order to reduce the calculation error, the authors propose a modified loss calculation method and demonstrate that the calculation error is reduced to less than 2%. [ABSTRACT FROM PUBLISHER]

In this paper, two new optimized common-mode voltage reduction PWM (CMVRPWM) strategies based on solving the established constrained nonlinear programming models in the time domain are proposed and analyzed. The proposed current ripple losses-optimized CMVRPWM (CRLO-CMVRPWM) minimizes the mean-square values of the three-phase current ripples by calculating the optimized special solutions of the voltage–second balance equations under the designed switching sequences. CRLO-CMVRPWM can achieve better output waveform quality than the existing methods. The proposed switching losses-optimized CMVRPWM (SLO-CMVRPWM) online optimizes the bus-clamping styles according to the phase currents to minimize the switching losses under different load power factors. Compared to the near-state PWM with fixed bus-clamping styles, SLO-CMVRPWM can reduce more switching losses in broader range of the modulation index. Simulation and experimental results verify the superiority of the proposed strategies to the conventional ones. [ABSTRACT FROM PUBLISHER]

Eliminating the leakage current is one of the most important issues for transformerless three-phase photovoltaic (PV) systems. In this paper, the leakage current elimination of a three-phase four-leg PV inverter is investigated. With the common-mode loop model established, the generation mechanism of the leakage current is clearly identified. Different typical carrier-based modulation methods and their corresponding common-mode voltages are discussed. A new modulation strategy with Boolean logic function is proposed to achieve the constant common-mode voltage for the leakage current reduction. Finally, the different modulation methods are implemented and tested on the TMS320F28335 DSP +XC3S400 FPGA digital control platform. The experimental results verify the effectiveness of the proposed solution. [ABSTRACT FROM PUBLISHER]

The purpose of neutral-point voltage balancing algorithms in the three-level neutral-point clamped (3L-NPC) topology is to eliminate the voltage unbalance of top- and bottom-side dc-link voltages (neutral-point voltage). These algorithms are divided into dc unbalance and ac unbalance compensation methods. The dc unbalance causes distortion of output currents; therefore, this problem has to be solved. The ac unbalance implies that there is an ac ripple in the top- and bottom-side dc-link voltages. In applications using 3L-NPC topology, a large dc-link capacitor value is required to mitigate this ac unbalance problem. As a result, the size and the cost of applications become large and expensive. In this paper, a compensation method for mitigating the ac unbalance of the neutral-point voltage is proposed, which causes the dc-link capacitor value to be small, when a carrier-based pulse width modulation method is applied. The proposed method compensates the ac unbalance of the neutral-point voltage by adding an optimal compensation value to the reference duty signals. This compensation value is calculated simply by currents and reference duty signals. The calculation process of the optimal compensation value is discussed, and the effectiveness of the proposed method is verified with simulations and experiments. [ABSTRACT FROM PUBLISHER]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

This paper presents an adaptive-linear-neuron (ADALINE)-based dead-time compensation method for vector-controlled permanent-magnet synchronous motor drives. The proposed strategy is achieved by suppressing the sixth-order current harmonics in the dq-axes synchronous reference frame. Four ADALINEs are employed in the proposed algorithm. Two ADALINEs are used for estimating the sixth-order harmonic components of dq-axes currents and the other two are used for generating the dq-axes compensation voltages. The voltage compensators are self-tuned by minimizing the estimated current distortion by means of the least mean square algorithm. The proposed compensation algorithm does not require any additional hardware or complicated signal processing algorithms. Experimental results validating the proposed compensation method are also presented. [ABSTRACT FROM PUBLISHER]

Commutations existing in a brushless dc motor (BLDCM) drive system not only aggravate the torque ripple and reduce the power factor but also cause the catastrophic failure of a sensorless drive based on the zero-crossing detection of back electromotive force when the commutation duration approaches or exceeds 30 electrical degrees. For a sensorless BLDCM drive system with a long commutation time, it is necessary to shorten the commutation time. In this paper, a technique making the commutation time significantly reduced by means of a novel inverter topology is presented. The proposed topology is based on the idea of supplying higher dc-link voltage for the freewheeling phase. First, the dc link of the backward freewheeling path is decoupled from that of the forward energy flow path. The superiority of dc-link decoupling for commutation control is analyzed. Then, in order to provide adjustable voltage higher than the dc source voltage for the dc link of the freewheeling path, a double-layer C-dump converter is proposed. Compared with the traditional unipolar C-dump converter, it not only upraises the potential of the positive rail but also lowers the potential of the negative rail. Finally, the proposed inverter topology is verified by simulation and experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, three overmodulation techniques for the three-to-five-phase indirect matrix converter (IMC) are proposed. The first technique utilizes only the adjacent large vectors in the sector in which the reference output voltage vector lies. The second technique improves on that by continuously adapting vector elimination in the d_2-q_2 vector space based on the output voltage requirements. The third technique utilizes the ripple in the dc link to further reduce the modulation index of the inverter stage during overmodulation. All three techniques increase the voltage transfer ratio of the three-to-five-phase IMC from 0.788 to 0.923, but with the addition of harmonics generated by a vector in the d_2-q_2 vector space of the inverter stage. Simulation and experimental results from a prototype three-to-five-phase IMC validate the three proposed overmodulation techniques. [ABSTRACT FROM AUTHOR]

In this paper, a modified zero-voltage-switching pulsewidth-modulation inverter with a digital-signal-processor-based proportional–integral–derivative (PID)-like fuzzy controller (PIDFC) is implemented. The switches of the inverter can achieve a soft-switching feature that can largely reduce switching losses and improve the converting efficiency. In order for the online control of the proposed dc–ac inverter to be feasible, a fuzzy control is designed to be a PID-like fuzzy mechanism with the complexity significantly reduced. From the results, it is shown that the PIDFC can not only stabilize the output at 110 V rms but can also improve the performance when the system load has been changed from 600 to 100 $\Omega$. Comparing with a traditional PID controller, the responding speed can be improved by 75% in the simulation, and the speed can still be improved by 35% in the practice experiment. [ABSTRACT FROM AUTHOR]

This paper investigates a dynamic voltage restorer (DVR) composed of two conventional three-phase inverters series cascaded through an open-end winding (OEW) transformer, denominated here DVR-OEW. The DVR-OEW operating with either equal or different dc-link voltages is examined. The proposed topology aims to regulate the voltage at the load side in the case of voltage sags/swells, distortion, or unbalance at the grid voltage. A suitable control strategy is developed, including space-vector analysis, level-shifted PWM and its equivalent optimized single-carrier PWM, as well as the operating principles and characteristics of the DVR. Comparisons among the DVR-OEW and conventional configurations, including a neutral-point clamped converter-based DVR, are furnished. The main advantages of the DVR-OEW compared to the conventional topologies lie on: 1) reduced harmonic distortion, 2) reduced converter losses, and 3) reduced voltage rating of the power switches. Simulated and experimental results are presented to validate the theoretical studies. [ABSTRACT FROM AUTHOR]

In this paper, a multilevel dodecagonal voltage space vector structure with nineteen concentric dodecagons is proposed for the first time. This space vector structure is achieved by cascading two sets of asymmetric three-level inverters with isolated H-bridges on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of dc link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well as the advantages of dodecagonal voltage space vector structure. In addition to that, a generic and simple method for calculation of pulsewidth modulation timings using only sampled reference values ( $v_\alpha$ and $v_\beta$) is proposed. This enables the scheme to be used for any closed-loop application such as vector control. In addition, a new method of switching technique is proposed, which ensures minimum switching while eliminating the fifth- and seventh-order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady-state operation, transient operation, including start-up have been presented and the results of fast Fourier transform analysis is also presented for validating the proposed concept. [ABSTRACT FROM PUBLISHER]

This paper introduces the periodic carrier frequency modulation (PCFM) for permanent magnet synchronous motor (PMSM) drive systems so as to reduce the low-frequency electromagnetic interference (EMI). PMSMs are widely used in many applications and they are usually fed by pulsewidth modulation (PWM) inverters. The EMI of PMSM, which results from the switch of power device, generates undesirable effects on the control system. Therefore, it is of importance to reduce the EMI of PMSM. The common mode (CM) conducted EMI model of the PMSM drive system is constructed to investigate the CM voltage. The simulations and experiments of PMSM fed by the fixed frequency PWM (FFPWM) and PCFM are implemented to analyze the CM conducted EMI. The CM EMI spectra of PMSM fed by the FFPWM and PCFM with different spreading frequency widths are compared to explore the influence of PCFM on the CM conducted EMI. The regular patterns on PCFM in reducing the CM conducted EMI of PMSM drive systems are revealed. [ABSTRACT FROM AUTHOR]

This paper proposes a three-phase isolated bidirectional ac/dc converter. The converter achieves buck–boost ac/dc bidirectional conversion, sinusoidal ac current, and high-frequency electrical isolation with single-stage structure. The traditional SVPWM algorithm should be modified to keep the voltage–second balance of the transformer. The circuit derivation, operation principles, and SVPWM algorithm are presented specifically. The solution for shoot-through problem is proposed, which does not need extra dead time. To verify the theoretical analysis, the proposed converter was simulated by MATLAB/SIMULINK and a 3 kW prototype was built in the lab. The simulation and experimental results show the high power factor and the low harmonic distortion characteristics of the circuit. [ABSTRACT FROM AUTHOR]

In this paper, an analysis and calculation of the dc-link current and voltage ripples are presented for a three-phase inverter with unbalanced load. A comparison of the dc-link average and root-mean-square (rms) currents between considering and ignoring high frequency harmonics of the output current is drawn. It is shown that high frequency harmonic currents have little effect on the dc-link current, and therefore, they can be ignored. Based on the symmetrical components method, the dc-link average and harmonic rms currents are derived, and the dc-link voltage ripple is compared between the balanced and unbalanced loads. It can be found that the dc-link current and voltage ripples consist of not only high frequency harmonics but also the double fundamental frequency harmonic, and the voltage ripple is independent of the positive-sequence component and determined by the negative-sequence component, under the unbalanced load. Experimental results are shown to verify the accuracy of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper introduces a novel pulse width modulation (PWM) technique to eliminate common-mode voltage in odd-multilevel inverters using the three zero common-mode vectors principles. Similarly, as in conventional PWM for multilevel inverters, this PWM can be properly depicted in an active two-level voltage inverter. With the help of two standardized PWM patterns, the characteristics of the PWM process can be fully explored in that active inverter as a switching time diagram and switching state sequence. Due to an unequal number of commutations of three phases in each sampling period, the switching loss is optimized by a proposed current-based mapping algorithm. The switching loss reduction can be up to 25% compared to the same PWM technique with nonoptimized algorithms. The PWM method has been then generalized as an equipotential PWM control, which is valid to both odd- and even-multilevel inverters . The theoretical analysis is verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

Single-phase power conversion such as pulse width modulation rectifier, grid connected PV inverter system, static synchronous compensator all can be implemented by an H-bridge inverter and a large electrolytic dc capacitor to absorb the ripple power pulsating at twice the line frequency (2ω ripple power). This paper proposed a dc capacitor-less inverter for H-bridge with minimum voltage and current stress. By adding another phase leg to control an ac capacitor, the 2ω ripple power can be absorbed by the capacitor and theoretically 2ω ripples to the dc capacitor can be eliminated completely. The H-bridge and the addition phase leg can be analyzed together as an unbalanced three phase system. By adopting space-vector pulse width modulation control and choosing the optimum ac capacitance and the voltage reference, the voltage and current stress of the switches can be minimized to the same as the conventional H-bridge. The size of capacitor is reduced by ten times compared to the conventional H-bridge system. Simulation and experimental results are shown to prove the effectiveness of the proposed dc capacitor-less inverter and active power decoupling method. [ABSTRACT FROM AUTHOR]

In this paper, a novel drive method, which is different from the traditional motor drive techniques, for high-speed brushless DC (BLDC) motor is proposed and verified by a series of experiments. It is well known that the BLDC motor can be driven by either pulse-width modulation (PWM) techniques with a constant dc-link voltage or pulse-amplitude modulation (PAM) techniques with an adjustable dc-link voltage. However, to our best knowledge, there is rare study providing a proper drive method for a high-speed BLDC motor with a large power over a wide speed range. Therefore, the detailed theoretical analysis comparison of the PWM control and the PAM control for high-speed BLDC motor is first given. Then, a conclusion that the PAM control is superior to the PWM control at high speed is obtained because of decreasing the commutation delay and high-frequency harmonic wave. Meanwhile, a new high-speed BLDC motor drive method based on the hybrid approach combining PWM and PAM is proposed. Finally, the feasibility and effectiveness of the performance analysis comparison and the new drive method are verified by several experiments. [ABSTRACT FROM AUTHOR]

Pulse width modulation schemes are aimed at adjusting the fundamental component while reducing the harmonic content of an inverter output voltage or current. This paper addresses the topic of optimal inverter operation in reference to a given objective function. The objective function could embody either a single performance criterion, such as voltage or current total harmonic distortion (THD), or a weighted sum of multiple criteria. The proposed method ensures primacy of the chosen solution while imposing no restriction over its modulation index. In particular, operating the inverter by the chosen solution would result in performances superior to any other modulation scheme commutating in an equal number of switching angles per fundamental cycle. The proposed method allows for the consideration of practical inverter constraints and prevents the possibility of impractical switching sequence. A detailed investigation of the method is given, accompanied by two practical cases minimizing, respectively, phase-voltage THD and line-current THD of a three-level inverter. Selected simulation and experimental results are presented to validate the theoretical part. [ABSTRACT FROM AUTHOR]

This paper describes the implementation of a load voltage observer into the control algorithms of a Rapid Capacitor Charger controlled by a digital signal controller (DSC) with a fast DSP core. A hybrid peak current mode control algorithm with digital control of the PWM signal and high speed analog current sensing is used to control the inverter of the charger. The DSC controller keeps the current loop stable using adaptive slope compensation. In addition to providing fast adaptive digital control of the current loop, the DSC can perform additional functions such as estimation of the voltage level of the load capacitor. This avoids the cost, bandwidth limitations and insulation challenges of a conventional HV-sensor. To evaluate the performance of the load voltage observer, we measured the output voltage with a laboratory grade HV probe to establish a reference to test the results of the digital algorithm. [ABSTRACT FROM PUBLISHER]

Three-phase multilevel (ML) inverters are used in many medium- and high-power applications such as motor drives and grid-connected systems. Despite the fact that numerous pulsewidth modulation (PWM) techniques for ML inverters have been developed, the impact of these modulation schemes on the peak-to-peak output current ripple amplitude has not been addressed yet. In this paper, analysis and comparison of current ripple for two-level (2L) and three-level (3L) voltage source inverters are given. Reference is made to optimal and popular modulation, so-called centered PWM, easily obtained by both carrier-based modulation (phase disposition, with proper common-mode voltage injection) and space vector modulation (nearest three vectors). It is shown that the peak-to-peak current ripple amplitude in 3L inverters can be determined on the basis of the ripple in 2L inverters, obtaining the same results as by directly analyzing the output voltage waveforms of the 3L inverters. This procedure can be readily extended to higher level numbers. The proposed analytical developments are verified by both numerical simulations and experimental tests. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel modulation technique and a new balancing control strategy for a single-phase five-level flying-capacitor (FC)-based active-neutral-point-clamped (ANPC) converter. The proposed modulator can control the FC voltage to follow the requested reference value and simultaneously generate the required ac output voltage regardless of the values of the dc capacitor voltages of the converter. By implementing this method, smaller values of the dc-link capacitor and FC can be used even in applications that could experience ripple or transient in the capacitor voltage. In a single-phase five-level ANPC converter applications, where the capacitors can experience pulsation power and dc-link balancing issues, such as grid-connected photovoltaic system, the selection of the reference voltage value for the FC can play an important role to balance the average values of the dc-link capacitor voltage. The proposed new control strategy uses a new reference voltage for the FC to be applied by the new modulator to have an average balanced dc-link voltages as well as an ac output voltage with good power quality. Simulation studies and experimental results demonstrate the effectiveness of the proposed modulation technique and control strategy even with relatively small dc capacitors to produce high-quality output voltage and current waveforms while maintaining an average balanced dc-link voltages. [ABSTRACT FROM PUBLISHER]

The analysis and assessment of the pulsewidth modulation (PWM) techniques is commonly based on the comparison of the total harmonic distortion (THD) results. THD is usually calculated by application of the Fourier transformation and by taking a limited number of harmonics into the consideration. In this paper, derivation of analytical formulas for the phase voltage THD is presented. The considered system is a symmetrical multiphase star-connected load, supplied from a multilevel pulsewidth-modulated voltage-source inverter (VSI, three-phase case is also covered). The solution is based on the Parseval's theorem, which links frequency spectrum and time domain through the average power (i.e., root-mean-square (rms) squared value) of the signal. The assumption throughout the derivations is that the ratio of the switching to fundamental frequency is high. Derivations are based on the integration of the power of the PWM signal in a single switching period over the fundamental period of the signal. Only ideal sinusoidal reference voltages are analyzed, and no injection of any type is considered. Formulas for phase voltage THD for any number of phases are derived for two- and three-level cases, for the most commonly used carrier-based methods. Comparison of the analytically obtained curves with simulation and experimental results shows a high level of agreement and validates the analysis and derivations. [ABSTRACT FROM AUTHOR]

Buck-converter-based topologies are used to generate high-frequency sinusoidal outputs. Buck-based inversion circuits such as voltage source inverters or class-D amplifiers have inherent control-to-output linearity in large-signal sense. However, in these topologies, the instantaneous output is always smaller than the dc-input during linear modulation. A differential boost inverter (DBI) is a boost-based topology that is used to generate a sinusoidal output. In DBI, the instantaneous output can be higher or lower than the dc-input voltage. DBI exhibits nonlinear control-to-output behavior in large-signal dynamic sense. Therefore, generating a high-frequency sinusoidal output using this topology is a challenge. The issues associated with a DBI for high-frequency sine wave generation are characterized in this paper. Conventional linear and nonlinear control techniques fail to produce a high-quality sine wave output at higher operating frequency. A nonlinear feedback linearization technique is proposed, which forces the output to be linear with respect to the reference even at higher operating frequency. This leads to a high-frequency high-quality sine wave generation using a DBI. The proposed modulator is verified using a laboratory prototype to generate a sine wave up to 2 kHz. A triangular wave of 100-Hz frequency is also generated by the proposed technique. Superior dynamic responses of a dynamic linearizing modulator controlled DBI for a step change in frequency, load current, input voltage, and reference are also experimentally verified. [ABSTRACT FROM AUTHOR]

In a six-switch three-phase inverter, the conventional pulsewidth modulation (PWM) has six switching times in every switching period based on the average concept. The used multidimensional feedback quantized modulation (MDFQM) strategy selects one switching state and keeps it in every sampling period based on the minimization of filtered voltage errors between the desired voltage commands and the output voltages. The widths of the output voltage pulse are integer times the fixed sampling time in MDFQM. In this paper, two high-efficiency current control methods based on MDFQM are proposed. They integrate the MDFQM strategy and the current control function to minimize the filtered current errors between the desired current commands and the inverter current. Due to the main advantages of less switching numbers and more closed fundamental current, a high-efficiency performance is achieved. The proposed methods are applied to the current control of a three-phase permanent-magnet synchronous motor. The simulation results and experimental results verify the effectiveness of the proposed methods. [ABSTRACT FROM PUBLISHER]

In order to improve the performance of sensorless field-oriented controlled motor drives at low speed, the inverter nonlinearity should be compensated for by an accurate voltage error model. This paper proposes a novel method to automatically obtain the total output voltage delay curve, which is a significant part of the inverter voltage error model. Unlike manual measurements of the output delays in earlier literature works, the proposed automatic measurement method achieves low cost in time and labor. Meanwhile, the compensation accuracy based on the automeasured output voltage delay curve is approaching to the performance of compensation by the manual measurement method, far better than the accuracy of compensation by the standard square-wave model at low speed. Moreover, in contrast to other inverter nonlinearity automeasurement methods, the measured results of the proposed method can be applied to compensate for inverter nonlinearities at different switching frequencies. The effectiveness of this method is validated in a voltage source inverter fed induction motor drive system experimentally. [ABSTRACT FROM AUTHOR]

The papers in this special section focus on multilevel inverters and applications for their use. This section will be divided into at least two parts. The first section exploresa a new module for cascaded multilevel inverter is proposed. This module is named as Envelope Type (E-Type) module and can generate 13 levels with reduced components. A section section focuses on a new general multilevel inverter topology based on cascaded connection of sub-multilevel units with reduced switching components, DC voltage sources and blocked voltage by switches is proposed. The proposed topology is optimized to generate any levels with minimum number of components and peak voltage on switches. [ABSTRACT FROM PUBLISHER]

In electric vehicle (EV) energy storage systems, a large number of battery cells are usually connected in series to enhance the output voltage for motor driving. The difference in electrochemical characters will cause state-of-charge (SOC) and terminal voltage imbalance between different cells. In this paper, a hybrid cascaded multilevel converter which involves both battery energy management and motor drives is proposed for EV. In the proposed topology, each battery cell can be controlled to be connected into the circuit or to be bypassed by a half-bridge converter. All half-bridges are cascaded to output a staircase shape dc voltage. Then, an H-bridge converter is used to change the direction of the dc bus voltages to make up ac voltages. The outputs of the converter are multilevel voltages with less harmonics and lower dv/dt, which is helpful to improve the performance of the motor drives. By separate control according to the SOC of each cell, the energy utilization ratio of the batteries can be improved. The imbalance of terminal voltage and SOC can also be avoided, fault-tolerant can be easily realized by modular cascaded circuit, so the life of the battery stack will be extended. Simulation and experiments are implemented to verify the performance of the proposed converter. [ABSTRACT FROM AUTHOR]

The electromagnetic interference (EMI) of the inverter output, which is controlled through a sinusoidal pulse width modulation method, is mainly generated at the carrier frequency and its harmonics. The peaks of the interference can be reduced effectively by using carrier-frequency modulation (CFM). The spectrum of the output differential-mode voltage in a SPWM inverter with periodic CFM is analyzed theoretically in this paper. Through changing the maximum frequency deviation, periodic signal's frequency and waveform of CFM, the suppression effects of interference peaks are discussed. A new scheme, in which the carrier frequency is modulated twice, is presented. In this scheme, the frequencies and waveforms of periodic signals are optimized and selected under the condition of the same maximum frequency deviation, and the synthetic modulation signal which has the best suppression effect of the maximum interference peak is obtained. The feasibility and validity of the scheme are proved by simulation and experiment results in a single-phase inverter. [ABSTRACT FROM AUTHOR]

In this paper, an online method to calculate the optimum dc bus voltage for motors and inverters with variable dc bus voltages is proposed. The required dc bus voltage in the low-speed region is much lower than that for the rated-speed region. As a result, the machine drive system efficiency can be improved with lower dc bus voltage since the switching losses in the inverter are reduced. To achieve both desired machine output torque and minimized losses simultaneously, an optimum dc bus voltage is required. However, machine parameter estimation errors and spatial harmonics in the machine result in calculation errors for the required dc bus voltage. A voltage disturbance state filter (VDSF), which is formed by a Luenburger-style closed-loop stator current vector observer with voltage command feedforward, is used to mitigate the calculation errors. Voltage errors caused by the parameter deviations and machine spatial harmonics will inherently be estimated by the observer's state feedback controller. Therefore, the calculation voltage error can be corrected by the VDSF's disturbance voltage so that the optimum dc bus voltage can be obtained. [ABSTRACT FROM PUBLISHER]

This paper proposed an improved phase disposition pulse width modulation (PDPWM) for a modular multilevel inverter which is used for Photovoltaic grid connection. This new modulation method is based on selective virtual loop mapping, to achieve dynamic capacitor voltage balance without the help of an extra compensation signal. The concept of virtual submodule (VSM) is first established, and by changing the loop mapping relationships between the VSMs and the real submodules, the voltages of the upper/lower arm's capacitors can be well balanced. This method does not requiring sorting voltages from highest to lowest, and just identifies the MIN and MAX capacitor voltage's index which makes it suitable for a modular multilevel converter with a large number of submodules in one arm. Compared to carrier phase-shifted PWM (CPSPWM), this method is more easily to be realized in field-programmable gate array and has much stronger dynamic regulation ability, and is conducive to the control of circulating current. Its feasibility and validity have been verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

Ideally, the inner (the upper or lower arm) current of a modular multilevel converter (MMC) is ideally assumed to be the sum of a dc component and an ac component of the fundamental frequency. However, as ac current flows through the submodule (SM) capacitors, the capacitor voltages fluctuate with time. Consequently, the inner current is usually distorted and the peak/RMS value of it is increased compared with the theoretical value. The increased currents will increase power losses and may threaten the safe operation of the power devices and capacitors. This paper proposes a closed-loop method for suppression of the inner current in an MMC. This method is very simple and is implemented in a stationary frame, and no harmonic extraction algorithm is needed. Hence, it can be applied to single-phase or three-phase MMCs. Besides, this method does not influence the balancing of the SM capacitor voltages. Simulation and experimental results show that the proposed method can suppress the peak and RMS values of the inner currents dramatically. [ABSTRACT FROM AUTHOR]

A common-mode (CM) filter based on the LCL filter topology is proposed in this paper, which provides a parallel path for ground currents and which also restricts the magnitude of the EMI noise injected into the grid. The CM filter makes use of the components of a line to line LCL filter, which is modified to address the CM voltage with minimal additional components. This leads to a compact filtering solution. The CM voltage of an adjustable speed drive using a PWM rectifier is analyzed for this purpose. The filter design is based on the CM equivalent circuit of the drive system. The filter addresses the adverse effects of the PWM rectifier in an adjustable speed drive. Guidelines are provided on the selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the proposed circuit. Experimental results based on EMI measurement on the grid side and the CM current measurement on the motor side are presented. These results validate the effectiveness of the filter. [ABSTRACT FROM AUTHOR]

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n ± 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including overmodulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally. [ABSTRACT FROM AUTHOR]

It is important to improve the overall efficiency of a photovoltaic (PV) inverter when it is connected to the grid. Fundamentally, the conversion efficiency from dc to ac power of an inverter is important. However, in the presence of partial shading, maximum power point tracking (MPPT) on PV modules is more important than the conversion efficiency. In this paper, a new control method for a three-level inverter is proposed. With the proposed method, each dc-link voltage of the three-level inverter can be asymmetrically regulated. When PV modules are split into two and each split module is connected to the respective dc-link capacitors of the inverter, the asymmetric control can be helpful because separate MPPTs are possible. The effectiveness of the proposed method was examined through experiments with a T-type three-level inverter, where each dc-link capacitor was supplied by a PV simulator emulating two separate PV modules under different shading conditions. [ABSTRACT FROM AUTHOR]

In high current applications, paralleling three-phase voltage sourced inverters represents a modular solution for improving the system power conversion quality. Single-phase output reactors are often inserted between the output terminals of the two inverters that supply the same phase output. One function of these inductors is to limit circulating currents between the two inverters. These currents are produced by common-mode voltage differences between the three-phase output terminals of the two inverters. Since standard interleaved pulse width modulation (PWM) techniques naturally produce high-frequency common-mode voltage differences between parallel connected inverters, this paper describes a modified discontinuous PWM scheme that eliminates these voltage differences. As a result, a three-phase parallel inverter system can be operated using a single three-limb coupled inductor, significantly improving the system power conversion density as a result. An experimental 3 kW prototype system is used to compare the operation of the resultant inverter against one using separate single-phase coupled inductors. [ABSTRACT FROM PUBLISHER]

The five-level active neutral-point (NP)-clamped (ANPC) converter is a newly emerging topology which can overcome the drawbacks of traditional NP-clamped and flying-capacitor multilevel converters. This paper presents a comprehensive theoretical analysis of the NP potential balancing issue and demonstrates that the NP potential can be naturally balanced under ideal and steady conditions. An NP potential balancing method based on zero-sequence voltage injection is presented. By calculating the average NP currents of all key zero-sequence voltages, the most appropriate zero-sequence voltage is selected to generate the demanded NP current, which can also limit the switching frequency of the series-connected insulated-gate bipolar transistors to the fundamental frequency. A three-phase five-level ANPC inverter prototype is built up, and both steady and dynamic experimental results are presented to verify the validity of this method. [ABSTRACT FROM PUBLISHER]

The three-phase four-leg inverter is very suitable for the high-power uninterruptible power supply application, and the load neutral point voltage (LNPV) should meet the requirement. In this paper, two factors influencing the LNPV were revealed first, which are the switching states and the ratio of the neutral inductance to the phase inductance (k). Then, the 16 switching states can be classified into four groups, and the ones in the first and the second group come to the minimum amplitude of LNPV with a specific ratio k respectively. Third, three methods to mitigate the LNPV were proposed based on the analysis of LNPV. In the first method, switching states in the first group are just utilized, and the LNPV can be eliminated with the ratio k of unity. In the second method, the switching states in the fourth class are avoided, and the LNPV can be reduced. Common mode filter is used in the third method and the LNPV can be mitigated effectively with the ratio k of unity. Furthermore, the power losses in the first and the second method were estimated and were compared with the original situation. Finally, the proposed methods were verified by simulation and experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, a beatless control that enables unity input power factor for the single-pulse operation in the matrix converter is proposed. The proposed method controls the output voltage to synchronize with the output current in terms of voltage–time product during the high output frequency operation. Following the proposed synchronous control method, the beat current is suppressed by approximately 1% at output frequency 1432 Hz. The experimental results also demonstrate that the input current waveform achieves sinusoidal waveform with unity power factor. In addition, the voltage transfer ratio of the matrix converter is improved from 0.866 to 0.955 in the high output frequency region. The maximum efficiency 96.4% is achieved at a 1.34-kW RL load. [ABSTRACT FROM AUTHOR]

This paper presents a novel modulation strategy for a seven-phase three-level inverter, aimed at variable-speed drive applications. Developed space vector pulsewidth modulation (SVPWM) strategy is based on vector space decomposition (VSD) approach and an analysis of multidimensional space vector projections in mutually orthogonal planes. The algorithm represents an extension of a recently developed five-phase three-level SVPWM algorithm and is considerably more complex, due to the existence of three mutually orthogonal planes in a seven-phase system. The difficulties of generalization of space vector strategies, which stem from the nature of the multiphase systems, are highlighted. Increasing the number of phases from five to seven increases the number of switching states from 3 ^5 = 243 to 3^7 = 2187 and the number of orthogonal planes from two to three. This considerably affects the complexity of the offline calculations. However, the final implementation of the algorithm is simple. Developed SVPWM algorithm is compared to an equivalent carrier-based strategy and it is shown that they yield identical performance. The complexity of the algorithms for real-time implementation is compared. Simulation and experimental results, obtained using neutral-point clamped inverter, verify the theoretical developments. [ABSTRACT FROM AUTHOR]

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n ± 1 (n = odd ) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation. [ABSTRACT FROM AUTHOR]

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three- or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications. [ABSTRACT FROM AUTHOR]

The advancement in power electronics has made the use of any number of phases in ac machines possible since with the inverter, any number of phase voltages can be realized as long as the corresponding inverter exists. To supply multiphase drives requires multiphase voltage source inverters (VSIs) whose output voltages depend very much on the methods of generating the pulses to turn on and turn off the inverter devices appropriately. This paper presents an analytical technique for the determination of the expressions for the modulation signals used in the carrier-based sinusoidal and generalized discontinuous pulse width modulation schemes for two-level, five-phase voltage source converters. These expressions can be used for both balanced and unbalanced phase voltages generated by any two-level multiphase inverter, in generating the required reference signals appropriately. An example of a five-phase VSI is presented to illustrate the strategy. Simulation and experimental results are presented in which a close examination shows that both results are similar for the balanced and unbalanced load voltage cases. [ABSTRACT FROM AUTHOR]

Operating a dual three-level inverter system from a single dc link circuit is an economic solution for generating five-level output voltage waveforms and to double the output power compared to a single three-level inverter. Such an inverter system is used for feeding a drive motor with open stator windings. A mechanism is then required to reduce the common-mode voltage components of the motor voltages. This paper describes an offline optimization method that minimizes both the harmonic distortion of the motor currents and the common-mode voltage components. The optimization permits reduction of the switching frequency to a very low value of 200 Hz without compromising the harmonic distortion. High performance operation of the drive system at low switching frequency is experimentally demonstrated. [ABSTRACT FROM PUBLISHER]

The inherent low switching frequency in medium-voltage alternating-current industrial drives presents power-quality and filter-design challenges. In this paper, four multilevel pulsewidth-modulation methods; phase disposition (PD), switching-loss minimization (SLM), and selective harmonic elimination (SHE) up to the 17th and 29th harmonics, respectively, are considered. The characteristics of long-cable effects on common-mode voltage (CMV) and differential-mode voltage (DMV), inverter losses and efficiency, induction machine voltage, and current harmonics are analyzed. Very little has been published in these quantitative comparisons. It is shown that the SHE method has reduced CMV as compared with the PD and SLM algorithms. Elimination of up to the 29th harmonic achieves the best harmonic performance without needing an output filter, at the expense that the losses are higher with a lower efficiency. Analytical and simulation results using the Piecewise Linear Electrical Circuit Simulation for the power-electronic circuits and MATLAB/Simulink for control systems are experimentally verified with a 1000-hp 4160-V neutral-point-clamped adjustable-speed-drive system that includes a 24-pulse front-end voltage source converter. [ABSTRACT FROM AUTHOR]

Multilevel inverters have been widely accepted for high-power high-voltage applications. Their performance is highly superior to that of conventional two-level inverters due to reduced harmonic distortion, lower electromagnetic interference, and higher dc link voltages. However, it has some disadvantages such as increased number of components, complex pulsewidth modulation control method, and voltage-balancing problem. In this paper, a new topology with a reversing-voltage component is proposed to improve the multilevel performance by compensating the disadvantages mentioned. This topology requires fewer components compared to existing inverters (particularly in higher levels) and requires fewer carrier signals and gate drives. Therefore, the overall cost and complexity are greatly reduced particularly for higher output voltage levels. Finally, a prototype of the seven-level proposed topology is built and tested to show the performance of the inverter by experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, a novel single-phase five-level inverter is proposed using coupled inductors. This inverter can output five-level voltage with only one dc source. No split of the dc voltage capacitor is needed, totally avoiding the voltage balancing problem in conventional multilevel inverters. The level of the output voltage is only half of the dc-link voltage in all conditions, leading to much reduced dv/dt . This inverter is based on the widely used three-arm power module and the voltage stresses on all the power switches are the same, making it very easy to construct. Operation mechanism of this inverter is analyzed and the possible switching patterns are investigated. Based on these analyses, a novel optimized modulation scheme is presented. With this modulation method, no dc components exist in the inductor currents, which is very helpful for minimization of the inductors. Simulation and experimental results show the validity of the proposed inverter together with the optimized modulation scheme. [ABSTRACT FROM AUTHOR]

Sliding mode control (SMC) is recognized as robust controller with a high stability in a wide range of operating conditions, although it suffers from chattering problem. In addition, it cannot be directly applied to multiswitches power converters. In this paper, a high performance and fixed switching frequency sliding mode controller is proposed for a single-phase unipolar inverter. The chattering problem of SMC is eliminated by smoothing the control law in a narrow boundary layer, and a pulsewidth modulator produces the fixed frequency switching law for the inverter. The smoothing procedure is based on limitation of pulsewidth modulator. Although the smoothed control law limits the performance of SMC, regulation and dynamic response of the inverter output voltage are in an acceptable superior range. The performance of the proposed controller is verified by both simulation and experiments on a prototype 6-kVA inverter. The experimental results show that the total harmonic distortion of the output voltage is less than 1.1% and 1.7% at maximum linear and nonlinear load, respectively. Furthermore, the output dynamic performance of the inverter strictly conforms the standard IEC62040-3. Moreover, the measured efficiency of the inverter in the worst condition is better than 95.5%. [ABSTRACT FROM AUTHOR]

This paper presents a new type of three-phase voltage source inverter (VSI), called three-phase dual-buck inverter. The proposed inverter does not need dead time, and thus avoids the shoot-through problems of traditional VSIs, and leads to greatly enhanced system reliability. Though it is still a hard-switching inverter, the topology allows the use of power MOSFETs as the active devices instead of IGBTs typically employed by traditional hard-switching VSIs. As a result, the inverter has the benefit of lower switching loss, and it can be designed at higher switching frequency to reduce current ripple and the size of passive components. A unified pulsewidth modulation (PWM) is introduced to reduce computational burden in real-time implementation. Different PWM methods were applied to a three-phase dual-buck inverter, including sinusoidal PWM (SPWM), space vector PWM (SVPWM) and discontinuous space vector PWM (DSVPWM). A 2.5 kW prototype of a three-phase dual-buck inverter and its control system has been designed and tested under different dc bus voltage and modulation index conditions to verify the feasibility of the circuit, the effectiveness of the controller, and to compare the features of different PWMs. Efficiency measurement of different PWMs has been conducted, and the inverter sees peak efficiency of 98.8% with DSVPWM. [ABSTRACT FROM AUTHOR]

This paper proposes a hybrid selective harmonic elimination pulsewidth modulation (SHEPWM) scheme for common-mode voltage reduction in three-level neutral-point-clamped inverter-based induction motor drives. The scheme uses the conventional SHEPWM (C-SHEPWM) to control the inverter at high frequency (≥ 0.9 motor rated frequency) and uses the modified SHEPWM (M-SHEPWM) to control the inverter at low frequency. It also uses a scheme to ensure the smooth transition between the two SHEPWM schemes. As a result, at high frequency, the C-SHEPWM provides the required high modulation index for the motor, while at low frequency, when a passive filter is less effective for common-mode voltage reduction, the M-SHEPWM is used to suppress the common-mode voltage. Experimental results show that the proposed hybrid SHEPWM scheme could meet the modulation index need of the motor and reduce the common-mode voltage in the drive, and the two SHEPWM schemes could transition smoothly. [ABSTRACT FROM AUTHOR]

This paper describes a hybrid active filter intended for mitigating the line-side harmonic currents of a three-phase 12-pulse diode rectifier used as the front end of a medium-voltage high-power motor drive. This hybrid filter is characterized by series connection of a simple LC filter and a small-rated active filter. This circuit configuration brings low cost, small size, and light weight to the hybrid filter. A three-phase experimental system rated at 400 V and 15 kW is designed, constructed, and tested, which is a downscaled model of the medium-voltage motor drive system. In this experiment, the LC filter is tuned to the 11th-harmonic frequency, and the active filter is based on a three-level neutral-point-clamped pulsewidth modulation converter (NPC PWM) with a dc capacitor voltage as low as 28 V. This hybrid filter is connected on either first or fourth winding of a line-frequency transformer with a first Δ-winding voltage of 400 V in the primary, and a second Δ-winding voltage of 220 V, a third Y-winding voltage of 220 V, and a fourth Δ-winding voltage of 400 V in the secondary. Experimental results show that the hybrid filter performs satisfactory filtering in a range from no-load to full-load conditions. [ABSTRACT FROM AUTHOR]