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Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope ($SS_{avg}$), off current (${I} _{OFF}$), and on current (${I} _{ON}$) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope. [ABSTRACT FROM AUTHOR]

An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659~\mu \textW when the piezoelectric transducer original open-circuit voltage V\mathrm{ oc,org}=5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V\mathrm{ DC} . The harvesting efficiency can still reach 71.3% at V\mathrm{ oc,org}=5 V. The size of the active area is 0.5 mm2 in a 0.18- \mu \textm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things. [ABSTRACT FROM PUBLISHER]

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results. [ABSTRACT FROM AUTHOR]

Accurate modeling of magnetic tunnel junction (MTJ) is critical for design of memories such as spin-transfer-torque magnetoresistive random access memory (STT-MRAM) and spin logic circuits such as spin flip flops. This paper reviews several static and dynamic models for the MTJ and compares them for their capabilities and limitations. Furthermore, a Verilog-A model is developed to predict dynamic characteristics of the MTJ. These models are used in simulating a prototype circuit to illustrate their strengths and weaknesses. [ABSTRACT FROM AUTHOR]

Dynamic average-value models (AVMs) for AC-DC rectifier circuits are generally formulated in state-space form and hence are straightforward to implement in state-variable-based simulation languages. In the nodal analysis-based approach used in electromagnetic transient (EMTP-type) simulation packages, the development of AVMs requires additional effort to reformulate and interface the models with the external ac and dc networks. This paper proposes a new averaged-circuit model for three-phase line-commutated rectifiers which is directly interfaced with the ac and dc networks, thereby achieving a simultaneous solution of the respective variables in EMTP-type solution. The proposed model is verified against conventionally interfaced model, as well as detailed switching model of the original rectifier circuit. A significant improvement of numerical accuracy and stability of the solution is demonstrated even at fairly large time steps. [ABSTRACT FROM AUTHOR]

The harmonic signal rejection capability and the rejection schemes of polyphase downconverters are discussed. An analysis of a simple model of a polyphase downconverter shows that n-phase converter can reject up to (n-2)th harmonic signal, and that (n-1)th harmonic signal aliases into the desired signal. It means that the harmonic rejection is not exclusive ability of downconverters with large number of phases, and conventional downconverters with fewer phases have the ability. An example is a differential amplifier type downconverter (n=2), which has the ability of even harmonic signal rejection as common-mode signal. In this paper, the common-mode concept is extended to polyphase circuits. It is named “partial common mode,” because it does not have to be common for all node but is common for a part of nodes. The partial common-mode rejection is effective for harmonic rejection. There is the other type of harmonic rejection techniques for polyphase downconverters, i.e., signal weighting-and-summing type. Comparison between the harmonic rejection with weighting-and-summing circuit and that with the common-mode rejection circuit is discussed, too. Due to its simple structure, a 6-phase downconverter with partial common-mode rejection is attractive for practical wideband receivers. [ABSTRACT FROM PUBLISHER]

This paper proposes a small-signal model for variable-switching-frequency hysteretic converters operating in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The model is capable of predicting flip-bifurcation phenomena when the hysteretic converter operates below the CCM/DCM boundary. By developing a discrete-time state-space model of the converter, the z-domain model is derived using the advanced z-transform. Such a tool is suitable to transform in the z-domain signals varying within a switching cycle. A comparison with exact simulations is provided to validate the proposed model. The propagation delay of the feedback control circuit is included due to its significant influence on the low-frequency open-loop gain. Experimental results run on a test chip including a 10-MHz TSMC 0.18\ \mu\m-process hysteretic-mode buck converter are also reported along with the model results. [ABSTRACT FROM PUBLISHER]

In this article, first integrated circuit (IC) implementation of parallel synchronized switching harvesting on inductor (p-SSHI) is presented for triboelectric energy harvester targeting 1 Hz to 5 Hz mechanical motions. It is accompanied by on-chip buck and switched capacitor DC-DC converters, all capable of handling 70 V levels. Unlike piezoelectric harvesters, triboelectric nanogenerators (TENGs) can produce very high open-circuit voltages; thus, the proposed system utilizes this property within the technology limits to maximize the extracted power. An in-house manufactured TENG using steel and polytetrafluoroethylene (PTFE) is modeled for sub-5 Hz motions. The energy is extracted and stored in an external capacitance until its voltage reaches 70 V, which is achieved in three press-and-release mechanical cycles. 70-to-2 V down conversion is carried on by 70-to-10 V buck converter followed by a 10-to-2 V switched capacitor DC-DC converter. A chip is manufactured in $0.18~\mu \text{m}$ HV BCD process with an active area of 6.25 mm2. End-to-end peak efficiency is measured as 32.71% for 1 Hz motion with a 722 $\mu \text{W}$ total power delivery to the load for 4 ms. [ABSTRACT FROM AUTHOR]

A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models. [ABSTRACT FROM AUTHOR]