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MOSFET breakdown voltage is strongly affected by the measurement conditions and the device layout. Substrate resistance has only a moderate influence on the breakdown voltage, and its dependence on device layout may be captured using a simple, semi-empirical model.

The studies have confirmed that, for ESD stress conditions; the time-to-breakdown of gate oxides as thin as 2nm can be predicted using the 1/E model. The 1/E model best fits the time-to-breakdown data. The report has stated that ESD protection networks must provide adequate voltage clamping for ultrathin gate oxide and must limit the voltage overshoot.

Research into hot-carrier-induced degradation in MOSFETs from a 0.25-um and a 0.1-um technology is presented. Post-metallization anneal in deuterium can substantially improve the device lifetime.

The heat flow in Silicon-On-Insulator (SOI) devices used for Electrical Overstress/Electrostatic Discharge protection is analyzed. The heat diffusion problem is modeled using a lossy transmission line equivalent model. Multifinger metal oxide semiconductor field-effect transistors are found to be effective in protecting SOI technology in terms of finger spacing. Buried oxide thickness and Silicon film thickness are found to be the major technology parameters affecting the protection level of SOI protection devices.

Single-trap-assisted inelastic tunneling produces stress-induced leakage current (SILC) in thin gate oxide MOS capacitors. The effect of the inelastic tunneling explains the thickness dependence of the SILC at low fields which identifies it as a scaling limitation for nonvolatile memory tunnel oxide. The clarification also explains the thickness dependence at high fields and facilities modeling of the electric field or voltage, and trap density dependencies of the SILC.

A comparison of various accelerated test methods for SiO2 reliability indicates that the ramp-voltage breakdown test is better than the ramp-current breakdown test. The best method for gate oxide defect characterization is the ramp-breakdown testing method. The ramp-voltage breakdown test is better than the ramp-current test for the extraction of the defect distribution.

An efficient circuit-level simulator for the prediction of time-dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools). The new module enhances the capability of the earlier SPICE-based oxide breakdown simulator by enabling practical simulations of large digital circuits. We discuss burn-in simulation for digital circuits and show that a significant reduction in oxide breakdown failure probability is possible.

Studies on N-MOSFET structures reveal that hole detrapping promotes time to breakdown (tBD) of silicon dioxide under bipolar stresses. tBD improves at high bias frequencies and tBD's dependence on frequency occurs due to tunnelling induced hole-detrapping from the anode. Hole detrapping reduces with increasing distance from the interface.

Studies on a bidirectional current reduction model that directly simulates circuit-degradation due to hot carriers reveals that the model yields results that agree well with experimental data for NMOSFET parameter such as stressing time. The model simulates hot-electron damage as a bidirectional voltage controlled current supplier. The model does not require SPICE simulation stress constrains and is compatible to all SPICE device models.