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In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and low offset voltage. The proposed comparator has been verified in a design, a 12-Bit SAR ADC(Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter). The comparator consists of two stage pre-amplifier and a StrongLatch. The pre-amplifier adopts an inverter-based input pair and a pair of capacitances in output stage to reduce noise. It is shown by simulation and analysis that the offset voltage is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 28 nm CMOS technology. The results show that, for the proposed comparator, the speed is 2.37 ns and consumes only 426.6 μ W power, at 1.8 V supply voltage and 330 MHz clock frequency. This article presents two kinds of FoM(Figure of Merit) to prove that the comparator has excellent performance. • Analysis of offset source of differential pairs. • Optimize comparator design. • Validate the comparator design. [ABSTRACT FROM AUTHOR]

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively. • A 16-bit 1 Msps SAR ADC is manufactured in 0.18 μm CMOS process with 170.47 dB FoMs. • A split-ADC digital calibration scheme based on dynamic element matching can improve the SFDR effectively. • A segmented capacitor array of 4 sub-capacitor arrays decreases the total capacitance of the high-resolution SAR ADC. • A dual-mode automatic zero comparator is utilised to reduce power consumption. [ABSTRACT FROM AUTHOR]

We present a highly robust 12-bit, 100 kS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) that excels in mitigating the effects of mismatch, temperature variations and process corners. A modified hybrid switching method is developed in design of the Capacitive Digital-to-Analog Converter (C-DAC) that saves 17 % of the DAC power consumption. Furthermore, we utilize a switched local feedback loop in the pre-amplifier circuit of the comparator that significantly minimizes the offset. Using this technique, the 3-sigma offset is reduced from 11.33 mV to 0.37 mV. Moreover, a high performance latched-based Bit Slice Unit (BSU) is proposed to preserve the successive codes during each conversion. Designed in 65 nm CMOS technology, the ADC operates in −55 °C to +125 °C temperature range, consuming only 1.55 μW with a 0.7V supply voltage and occupying a 0.6 mm2 area. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (V CM ). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038 m m 2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

Abstract A 10-bit 10-KS/s asynchronous successive approximation register (SAR) analogue-to-digital converter (ADC) in 180 nm CMOS process is proposed for low energy wireless senor network chip. Nanowatt power consumption magnitude can be achieved benefiting from the novel switch scheme which can reduce the average switching energy and area of the capacitive digital-to-analog converter (DAC) by 97.66% and 50% without reset energy compared to the conventional approach, respectively. Meanwhile, a cascode current is employed in the subthreshold dynamic comparator to suppress the total offset voltage (mean+3std) variation with the bulk-driven differential pair. As a consequence, the fluctuation of total offset voltage is only 0.28 mV when the input common-mode voltage operates from 200 mV up to 400 mV at 0.4 V supply. Simulation results indicate that a signal-to-noise-plus-distortion ratio (SNDR) of 58.75 dB and a power consumption of 30.4 nW can be achieved at 0.4 V supply voltage and a near Nyquist rate input, resulting in Walden's figure-of-merit (FOM w) of 4.32fJ/conversion-step. [ABSTRACT FROM AUTHOR]

Abstract This paper configures a successive approximation register (SAR) analog-to-digital converter (ADC) based on a new switching algorithm with efficient energy consumption. The proposed switching algorithm applies the same reference voltage to the bottom plates of all capacitors in each capacitor array to drain no energy through capacitors. In addition to a 100% energy saving in the switched-capacitor digital-to-analog converter (DAC) block, configuration of an N -bit SAR ADC shows a 50% capacitor area reduction in comparison with the conventional SAR ADC. [ABSTRACT FROM AUTHOR]

Abstract A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC. [ABSTRACT FROM AUTHOR]

In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power consumption significantly, the method does not affect the dynamic behavior of the comparator such as speed or offset voltage. This method reduces the power consumption by 30% to 58% . Post Layout Simulations as well as analytical derivations and schematic simulations prove the beneficial performance of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with foreground calibration for digital-to-analog converter (DAC) mismatch and comparator static offset errors. The proposed foreground calibration utilizes the redundancy to facilitate the detection of DAC weight errors, and compensates for deviations of offset and DAC weights from the ideal value in the analog domain respectively. Benefit from the choice of 0.3 fF unit capacitance, the calibration achieves a 90% reduction in DAC power overhead over the conventional method. The effectiveness of this method is demonstrated by simulations in which differential non-linearity (DNL) is reduced from −1.28 LSB to −0.53 LSB and integral non-linearity (INL) is reduced from 2.20 LSB to 1.08 LSB. The ADC implemented in 40 nm CMOS consumes 3.66 μW from a 1 V supply, and achieves an improved signal-to-noise and distortion ratio (SNDR) of from 59.68 dB to 66.67 dB and a figure of merit (FoM) of 2.07 fJ/conversion-step at Nyquist rate. [ABSTRACT FROM AUTHOR]

This paper presents a two-channel 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. Multi-bit/cycle SAR ADC with redundancy is proposed. Novel background calibration for multi-bit/cycle SAR ADC is applied in the prototype ADC monitoring and calibrating the offset between DACs. The ADC achieves both high speed and low power by combining several features, namely digital calibration, redundancy, foreground calibrated dynamic comparator and leakage-immune dynamic logic. According to the simulation, the proposed calibration technique significantly improves linearity exhibiting 77.69 dB SFDR and 60.95 dB SNDR with Nyquist-frequency input at 1 GS/s sampling rate. [ABSTRACT FROM AUTHOR]