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In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

This paper discusses the back-flashover (BFO) phenomena in a high-voltage (HV) vertical double-circuit transmission line by means of numerical simulations. The single- and multiphase BFOs are analyzed considering 24 cases of AC-voltage angles and nonlinear characteristic of flashovers, taking advantage of the circuit analysis method in time domain. The models used in circuit analysis are the TEM-delay model, which can take into account the non-TEM characteristics of tower and line, and the conventional models. Prior to the BFO analysis, the characteristics of circuit models are compared and discussed with the numerical electromagnetic analysis results. In BFO analysis, it is clarified that the occurrence probability of the multiphase BFO is heavily depending on the bias AC-voltages. The relation of measured BFO phases and AC-voltages are well explained by the TEM-delay model with the valid lightning current magnitude. The conventional circuit models could have underestimated the occurrence of BFOs in HV transmission lines. The analysis and discussions shown in this paper can be utilized for advanced evaluation of lightning performance of transmission lines that considers the seriousness of lightning accidents. [ABSTRACT FROM AUTHOR]

In this paper, we propose a circuit yield prediction method to improve the efficiency of circuit yield prediction. Both traditional Monte Carlo simulation and the current popular machine learning for yield prediction require a large number of circuit simulation results, which increases production costs. This method finds the data boundary points through high-dimensional kernel density estimation, and performs simulation calculations on these boundary values instead of the overall simulation. Experiments show that, compared with machine learning and Monte Carlo methods, the proposed algorithm can efficiently predict the yield of circuits. [ABSTRACT FROM AUTHOR]

Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumption, and performance. Simulations are computationally expensive making it rather hard to efficiently explore the design space to identify high-quality configurations in an acceptable exploration time when relying solely on a single-core machine to run simulations. To tackle this problem, engineers proposed solutions based on either: 1) the use of approximate analytic performance models to prune the suboptimal regions of the design space by reducing the number of simulations to run or 2) the use of parallel computing resources to run different simulations concurrently. In this paper we demonstrate that, to efficiently speedup the DSE process while fully exploiting the parallel computing infrastructure, we need to combine the two techniques together in a structured manner. In this paper, we investigate this issue and we propose a DSE solution that exploits approximate analytic prediction models to improve the simulation schedule on a parallel computing environment rather than to prune the number of simulations. Experimental results demonstrate that the proposed technique provides a speedup from 1.26\boldsymbol \times to 4\boldsymbol \times with respect to other parallel state-of-the art DSE techniques. [ABSTRACT FROM PUBLISHER]

An enhanced full-wave method based on circuit analysis is presented in this paper, where the whole set of modes TEmnp and TMmnp are taken into account. The modeling of a split cylinder resonator is done with two circuit networks of one and three ports, characterized by their generalized admittance matrix, which is computed making use of the mode matching method. The improved full-wave circuit method has been applied to the accurate determination of dielectric properties of materials. The proposed method has been validated through comparisons with other published models and also with measurements. [ABSTRACT FROM PUBLISHER]

The spin-transfer torque domain wall (DW) magnetic tunnel junction (MTJ) enables spintronic logic circuits that can be directly cascaded without deleterious signal conversion circuitry and is one of the only spintronic devices for which cascading has been demonstrated experimentally. However, experimental progress has been impeded by a cumbersome modeling technique that requires a combination of micromagnetic and SPICE simulations. This paper, therefore, presents a SPICE-only device model that efficiently determines the DW motion resulting from spin accumulation and calculates the corresponding MTJ resistance. This model has been validated through comparison to the authoritative micromagnetic-based model, enabling reliable prediction of circuit behavior as a function of device parameters with a 10 000 $\times $ reduction in the simulation time. This model thus enables deeper device and circuit investigation, advancing the prospects for nonvolatile spintronic computing systems that overcome the von Neumann bottleneck. [ABSTRACT FROM AUTHOR]

We present a physics-based compact model that captures the behavior of phase-transition materials. The model includes a self-heating module that captures the change in temperature with device operation and the resulting phase change. This is the first compact model that captures the temperature-dependent multidomain switching and the hysteresis behavior seen in such devices. The model is implemented in Verilog-A and validated with experimental data for various geometries and temperatures. It is further coupled with industry standard BSIM-BULK, ASM-HEMT, and BSIM-CMG models for SPICE simulation and validated for various phase-transition FETs, illustrating the previously proposed steep switching effect and a subthreshold slope below the Boltzmann limit of 60 mV/decade. [ABSTRACT FROM AUTHOR]

In this paper, we will focus on the problem of modeling global or die-to-die variation in semiconductor devices. We will demonstrate that the process corner-based approach for modeling global variation, which has been the dominant approach for design validation, has fundamental limitations in predicting the circuit performance variation. We will then show how a full statistical model of variation can accurately predict circuit behavior and discuss some of the challenges in moving from a corner-based design to statistical simulations. [ABSTRACT FROM AUTHOR]

In this paper, we propose SVR-NoC, a network-on-chip (NoC) latency model using support vector regression (SVR). More specifically, based on the application communication information and the NoC routing algorithm, the channel and source queue waiting times are first estimated using an analytical queuing model with two equivalent queues. To improve the prediction accuracy, the queuing theory-based delay estimations are included as features in the learning process. We then propose a learning framework that relies on SVR to collect training data and predict the traffic flow latency. The proposed learning methods can be used to analyze various traffic scenarios for the target NoC platform. Experimental results on both synthetic and real-application traffic demonstrate on average less than 12% prediction error in network saturation load, as well as more than $100\times $ speedup compared to cycle-accurate simulations can be achieved. [ABSTRACT FROM PUBLISHER]

Leakage power is becoming significant in new generation IC chips. As leakage power is nonlinearly related to temperature, it is challenging to manage the thermal behavior of today’s multicore systems, since thermal management becomes a nonlinear control problem. In this paper, a new predictive dynamic thermal management (DTM) method with neural network thermal model is proposed to naturally consider the inherent nonlinearity between leakage and temperature. We start with analyzing the problems of using recurrent neural network (RNN) to build the nonlinear thermal model, and point out that there is exploding gradient induced long-term dependencies problem, leading to large model prediction errors. Based on this analysis, we further propose to use echo state network (ESN), which is a special type of RNN, as the leakage-aware nonlinear thermal model. We theoretically and experimentally show that ESN achieves much higher accuracy by completely avoiding the long-term dependencies problem. On top of this nonlinear ESN thermal model, we propose a novel model predictive control (MPC) scheme called ESN MPC, which uses iterative steps to find the optimal future power recommendations for thermal management. Being able to consider the leakage-temperature nonlinear effects and equipped with advanced control technique, the new method achieves an overall high quality temperature management with smooth and accurate temperature tracking. The experimental results show the new method outperforms the state-of-the-art leakage-aware multicore DTM method in both temperature management quality and computing overhead. [ABSTRACT FROM AUTHOR]

In this paper, transmission-line (TL) theory is applied to formulate a worst-case analysis for the assessment of wideband intentional electromagnetic interference radiated onto a cable harness (with terminal units) above ground. Given the bandwidth and the energy density of the high-power electromagnetic pulse impinging on the cable, the pulse spectrum maximizing the peak value of the common-mode voltage waveform induced at a cable end is obtained. Unlike in a full-wave solution to the problem, the proposed TL model allows for, first, deriving closed-form expressions in the special case of a cable terminated in a matched load at the opposite end; second, computationally efficient evaluation of the spectrum for any other loading conditions. The obtained results clearly unveil the impact of the system parameters (cable length, height, terminal loads, and pulse bandwidth) on the statistics of the worst-case voltage peak for the random direction of incidence and polarization. [ABSTRACT FROM AUTHOR]

Generally, battery-fed capacitive loads are charged to high voltages in series of switching cycles with smaller fragments of energy delivered to the load in every cycle to ensure an efficient charging process. In high voltage low power (HVLP) flyback charging circuit, significant portion of input energy drawn from the source in a cycle is utilized by the effective parasitic capacitance of the HV transformer and semiconductor devices and circulated back to the source at the end of the cycle. This reduces the energy delivered to the load per cycle and hence the net energy delivered in the charging process. In this paper, an energy-based analysis and simplified energy-based model for HVLP charging circuits is derived. An energy-based approach is appropriate to describe and define the HVLP converter behavior in terms of load energy component and circulating energy component. The derived energy-based model is extended to obtain analytical closed-form expressions governing the essential parameters of the charging circuit. The proposed energy-based model and analytical formulation of essential parameters are experimentally validated on a 0–2.5 kV programmable high voltage charging circuit prototype fed from 12 V input battery source. [ABSTRACT FROM AUTHOR]

Electro-mechanical-actuator (EMA) is the key component to convert electrical power into mechanical power for flight control in next-generation aircrafts. Multi-domain simulation of EMA can benefit its on-going evolution process. This paper presents the real-time multi-domain modeling and simulation of an EMA as elevator for flight control by utilization of a unified solver. Several key issues concerning the computational efficiency and successful implementation of this solver are provided and its relationship with state-variable model is also elaborated. Analysis shows that this solver could be a competitive candidate for multi-domain simulation because of its high computational efficiency and relatively less modeling effort. Electrical, mechanical, and thermal parts of the EMA are modeled and simulated interactively based on the proposed solver. The multi-domain model is implemented on FPGA board and executes in real time. Simulation results from FPGA board and commercial softwares under several test scenarios coincide with each other in very high degree, which showcases the efficacy of the proposed solver with respect to computational efficiency and ability to accommodate multi-domain models. The proposed model and solver are useful for hardware-in-the-loop design and testing of EMA. [ABSTRACT FROM AUTHOR]

The magnetic potential drop in nonlinear iron can be replaced by equivalent current sheets on linear iron edges. Based on this principle, this paper proposes a nonlinear subdomain and magnet circuit hybrid model (SMCHM) for open-circuit field prediction in surface-mounted permanent-magnet machines. The values of current sheets are calculated from a magnetic circuit and used as boundary conditions in the subdomain model. The finite element (FE) validation is performed, which shows the SMCHM can accurately predict the magnetic field distribution and electromagnetic performance as nonlinear FE method does. The accuracy of SMCHM is significantly higher than the conventional subdomain model neglecting a nonlinearity effect, and the computation speed of SMCHM is dramatically faster than the FE model. [ABSTRACT FROM AUTHOR]

A major issue in the modeling of harmonics dynamics via extended harmonic domain (EHD) has been detected and thoroughly analyzed in a recently published paper. It consists on incurred error of individual harmonic response when a step change in either source or parameter variable is applied to a system modeled in the EHD. This paper demonstrates that the error is due to incorrect initial conditions of the EHD state-space model at the time of step change and proposes an effective solution to achieve zero error. [ABSTRACT FROM PUBLISHER]

Line edge roughness (LER) is a critical variability source in scaled FinFETs. LER produces line width roughness (LWR) that causes threshold voltage ( VT ) variability. Various lithography techniques demonstrate characteristic LER-LWR relationship. For translating LER/LWR to the VT distribution, an analytical model for uncorrelated fin edges (correlation coefficient, \rho =0 ) has been presented in the literature. However, a range of correlation coefficients ( 0\le \rho \le 0.85 ) between two fin edges is experimentally observed for various lithography techniques. In this paper, we present an analytical model to predict \rho dependent \mu ) and standard deviation ( \sigma ) for \rho and nominal fin width {W}_{\text {fin}}) and LER variability (correlation length \Lambda $ and correlation coefficient $\rho $ ) parameters to show excellent match. The model is 1000 times faster compared with TCAD simulations. [ABSTRACT FROM AUTHOR]

In this paper, a new behavioral modeling approach for magneto-static hysteresis is presented. Many accurate models are currently available, but none of them seems to be able to correctly reproduce all the possible $B$ – $H$ paths with low computational cost. By contrast, the approach proposed in this paper is based on simple functions, which do not require calculus to be involved, thus assuring a very good efficiency in the algorithm. In addition, the proposed method enables initial magnetization curves, symmetric loops, minor loops, normal curves, and reversal curves of any order to be reproduced, as demonstrated through the pertinent results provided in this paper. A model example based on the proposed modeling technique is also introduced and used as inductor core, in order to simulate an $LR$ series circuit. Finally, the model ability to emulate hysteretic inductors is proved by the satisfactory agreement achieved when comparing the measured and simulated results. [ABSTRACT FROM AUTHOR]

This paper proposes an optimal design method of modular multilevel converter (MMC) levels to approach the reasonable compromise between accuracy and computational efficiency. The entire procedure is benchmarked by a Thévenin equivalent 451-level MMC model. First, the calculation method of the critical maximum simulation time step is proposed to faithfully represent each voltage level of the staircase waveforms. Second, the previously developed improved analytic hierarchy process is adopted to integrate the relative errors of all the main electrical parameters into one comprehensive relative error at each MMC level. Third, the steady state, ac, and dc transient state relative error results as well as the central-processing unit times of all models are normalized and curve fitted based on the benchmark model. Finally, the optimal MMC level is obtained by the plotted curves and the given subjective weights considering the accuracy and efficiency. And the effectiveness and robustness of the proposed method are validated by various simulation scenarios on PSCAD/EMTDC. [ABSTRACT FROM PUBLISHER]

This paper proposes an efficient method for extracting the coupling capacitance between through-silicon via (TSV) and the adjacent redistribution layer (RDL) interconnections based on the scalar potential integral equation and cylindrical accumulation mode basis functions. As the numerical integration of capacitance is very complicated, we employed an approximation based on the use of double-exponent transformation and the segmentation method to improve the calculation efficiency. The maximum deviation is less than 5%. The scalability of the proposed model is verified by performing parametric studies on different physical design parameters; the results show good agreement between the proposed model and the numerical simulation. Additionally, we studied several different structures of TSVs with and without RDLs to explain the influence of the coupling capacitance between TSVs and RDLs on crosstalk noise. [ABSTRACT FROM AUTHOR]

A 3-D frequency-domain nonlinear model for sheet beam (SB) traveling-wave tubes (TWTs) based on folded waveguides (FWs) is presented in this paper. The SB with finite thickness is a 3-D asymmetric system. To characterize such a system, an accurate description of the radio frequency (RF) fields and the space charge (SC) fields in the interaction gap in all three dimensions is required. An analytical expression for the interaction electric fields is derived. Beside of the interaction electric fields, a modified analytical model for the dispersion and interaction impedance is also imbedded in our code predicting the cold characteristics of the waveguide, which agrees with the results of the 3-D simulation code CST. As a result, the model provides a through predictive capability from the geometrical parameters to the device performance, such as saturation power and gain. Due to the short computing time, our code is very useful for the large-scale optimizations of TWTs. For the calculation of the SC field, a particle-in-cell method is used by solving the 3-D Helmholtz equation and the motion equation. Such analytical technology is much more preferable to interpret the complicated beam–wave interaction than the conventional electron beam models, which attributes to the ever-increasing computing capacity of the computers. These features have been incorporated in the development of our large-signal code SB-FWTWT-3-D. The validation of the model is performed and comprehensive results are presented. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive and modular modeling framework for stochastic signal integrity analysis of complex high-speed links. Such systems are typically composed of passive linear networks and nonlinear, usually active, devices. The key idea of the proposed contribution is to express the signals at the ports of each of such system elements or subnetworks as a polynomial chaos expansion. This allows one to compute, for each block, equivalent deterministic models describing the stochastic variations of the network voltages and currents. Such models are synthesized into SPICE-compatible circuit equivalents, which are readily connected together and simulated in standard circuit simulators. Only a single circuit simulation of such an equivalent network is required to compute the pertinent statistical information of the entire system, without the need of running a large number of time-consuming electromagnetic circuit cosimulations. The accuracy and efficiency of the proposed approach, which is applicable to a large class of complex circuits, are verified by performing signal integrity investigations of two interconnect examples. [ABSTRACT FROM PUBLISHER]

With the growing number of process variation (PV) sources in deeply nano-scaled technologies, parameterized device and circuit modeling is becoming very important for chip design and verification. However, the high dimensionality of parameter space, for PV analysis, is a serious modeling challenge for emerging VLSI technologies. These parameters correspond to various interdie and intradie variations, and considerably increase the difficulties of design validation. Today’s response surface models and most commonly used parameter reduction methods, such as principal component analysis and independent component analysis, limit parameter reduction to linear or quadratic form and they do not address the higher order of nonlinearity among process and performance parameters. In this paper, we propose and validate a feature selection method to reduce the circuit modeling complexity associated with high parameter dimensionality. This method relies on a learning-based nonlinear sparse regression, and performs a parameter selection in the input space rather than creating a new space. This method is capable of dealing with mixed Gaussian and non-Gaussian parameters and results in a more precise parameter selection considering statistical nonlinear dependencies among input and output parameters. The application of this method is demonstrated in digital circuit timing analysis in both FinFET and Silicon Nanowire technologies. The results confirm the efficiency of this method to significantly reduce the number of required simulations while keeping estimation error small. [ABSTRACT FROM PUBLISHER]

Modeling and analysis of low-frequency noise, such as 1/ f and burst noise, with time-varying bias conditions is a long-standing open problem in circuit simulation. In this paper, we offer a solution for this problem and present a computational model for low-frequency noise. The merits of our model are twofold. First, it is fully nonstationary. It can represent noise processes with time-varying statistics that are tightly coupled to the circuit variables in a stochastically correct manner. Second, its mathematical structure allows the utilization of well-established, non-Monte Carlo noise analysis techniques which are orders of magnitude faster than their Monte Carlo counterparts. We first provide an overview of our noise model along with the legacy modeling techniques. We verify that, when used with fast non-Monte Carlo analysis methods, our noise model produces results with the same accuracy as computationally laborious Monte Carlo simulations. We then proceed to contrast our nonstationary noise model with the legacy modulated stationary model. As a typical instance, where the results produced by these two models differ significantly due to intricate nonstationary behavior, we analyze the switched biasing technique that was proposed in order to reduce low-frequency noise. As a case study, we examine the 1/ f noise behavior in the previously proposed coupled sawtooth oscillator circuit and show that, whereas simulations conducted with the legacy modulated stationary model suggest that no noise reduction is obtainable with switched biasing, our nonstationary noise model predicts the correct amount of noise reduction observed in previously published experimental data. [ABSTRACT FROM PUBLISHER]

High-level synthesis (HLS) relies on the use of synthesis directives to generate digital designs meeting a set of specifications. However, the selection of directives depends largely on designer experience and knowledge of the target architecture and digital design. Existing automated methods of directive selection are very limited in scope and capability to analyze complex design descriptions in high-level languages to be synthesized using HLS. This paper proposes a comprehensive model-based analysis (COMBA) framework which is capable of analyzing the effects of a multitude of directives related to functions, loops and arrays in the design description using pluggable analytical models, a recursive data collector and a metric-guided design space exploration (DSE) algorithm. COMBA reports a small average error in estimating performance when compared with HLS tools like Vivado HLS, and finds a high-performance configuration of synthesis directives within minutes. Given different resource constraints, COMBA finds configurations with higher speed-ups, compared with the state-of-the-art. Moreover, COMBA can guide the performance and area trade-off analysis. Experiments show that our DSE algorithm outperforms the conventional genetic algorithm, and COMBA efficiently finds a near-optimal configuration, which proves the efficiency of our tool for optimizing the practical HLS based designs. [ABSTRACT FROM AUTHOR]

Designing of power electronics converters seldom considers multiscale coupling relationship between components and circuits. Although macroscale is computationally efficient, it barely contains the micro implications about aging, deterioration, transient performance, etc. Conversely, the microscale obtains multiple observation scope, however, with computational disaster. In this paper, the multiscale method is applied in the power electronic modeling which provides a qualitative methodology to combine the scales appropriately, and to obtain the dynamic response under the action of multiphysics accurately. Firstly, the concept of multiscale and the scale division of power electronic system are expounded. Considered the dynamic behavior of components and converters with different complexity, the framework of multiscale converters and modeling method is proposed. Afterwards, a scalable coupling separation method is presented, providing interfaces for the multiphysics and dielectric physics. Additionally, a multiscale conversion algorithm considering both efficiency and accuracy is designed. In the end, a DC/DC converter is taken for the verification. The feasibility and advantages of multiscale method and conversion algorithm have been demonstrated in accuracy, consistency and multiple analysis. By filling in the microscale observation, it is plausible to provide theoretical guidance for reducing margin, accurate analysis and reliability estimation of electronic components. [ABSTRACT FROM AUTHOR]

The accuracy of a power-hardware-in-loop (PHIL) simulation is influenced by factors such as dynamics of the power amplifier (PA) and discretization of the real-time simulated part of the system. An open-loop voltage-source inverter (VSI) without an output filter is demonstrated to be a good choice for power amplification in terms of cost, size, design effort, bandwidth, and accuracy when the load on the PA is significantly inductive. An open-loop-VSI-based PA is shown to be accurate in emulating a synchronous generator, including the fast transients in the excitation control system. The discretization effects of the real-time simulator are captured effectively by the discrete-time (DT) modeling approach proposed in this paper. The DT model is shown to replicate fast transients in the PHIL simulation better than the existing continuous-time-based model. Stability of the PHIL simulation of a benchmark circuit is analyzed using the proposed DT modeling approach. The stability analysis is validated through simulations and experiments. The stability limits derived based on the proposed analysis are capable of suggesting maximum and minimum values of certain circuit parameters, as required for stability. [ABSTRACT FROM AUTHOR]

This paper investigates an original multiphysics KB modeling of the electrothermomechanical (ETM) phenomena in a multi-layer printed circuit board (PCB) under heat cycle aggression. The coupled thermal and intrinsic mechanical interactions with the PCB electrical response are analyzed. The via-interconnect line (IL) junction fatigue caused by the mechanical tensions is explained with tensorial equations. The ETM effects transduced between the PCB components are modeled with equivalent graphs. The multiphysics problem general tensorial relation is formulated. To validate the Kron–Branin model, the numerical application of three-layer PCB proof-of-concept under thermal cycle aggression with 0-to-70 °C variation is introduced. The tensile stresses induced by the thermal effect on the vias and ILs are calculated. The via cracking fatigue model is approximated. The PCB voltage transfer function and input impedance in the function of the thermal aggression are discussed. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) has attracted extensive research in recent years. An appropriate model is necessary to analyze stability or to design MMC controllers. Several published MMC models have been derived in single-phase form to simplify the modeling mathematics. However, little attention is given to the zero-sequence voltage, which introduces coupling in the single-phase model and leads to significant error. In this paper, after revealing the mechanism behind the zero-sequence voltage, a more accurate generalized single-phase MMC model is proposed, which eliminates the zero-sequence voltage coupling effect and is linearized based on harmonic state space (HSS) theory to precisely characterize the internal harmonic features of MMC. A systematic HSS modeling process is presented for both open-loop and closed-loop conditions. And the proposed model is generalized as it can incorporate different control strategy by controller transfer function substitution. Hence it is valuable to analyze MMC stability and dynamics. Model effectiveness is verified by simulation results. [ABSTRACT FROM AUTHOR]

This paper presents a coupled electromagnetic and thermal design methodology which addresses the problem of balancing accuracy against computation time. A case study on a short-duty permanent-magnet (PM) linear actuator is used to illustrate the approach. The proposed method employs a two-dimensional electromagnetic finite-element (FE) model coupled with a detailed thermal equivalent circuit (TEC) model which is automatically constructed and parameterized using geometric and material data. A numerical method of estimating the equivalent thermal properties of the winding amalgam is used along with published empirically derived convection and radiation heat transfer correlations. The relatively high number of network nodes and more accurate thermal material properties minimizes model calibration and allows improved temperature prediction, including winding hot spots, while maintaining a low computational cost for both steady-state and transient analyses. A comparison between experimental and theoretical actuator performance shows that the design methodology provides good accuracy electromagnetic and transient thermal performance predictions without the need for direct model calibration and can yield an optimized design within an acceptable time frame. [ABSTRACT FROM PUBLISHER]

Yield optimization is a challenging topic in electronic circuit design. Methods for yield optimization based on Monte Carlo (MC) analysis of a circuit whose behavior is reproduced by simulations usually require too many time expensive simulations to be effective for iterative optimization. In this paper, we propose a method which tackles the yield optimization problem by combining a support vector machine (SVM) surrogate model (SM) of the circuit to perform the MC analysis and evaluate the yield, and an efficient optimization method to maximize the yield evaluated using the SVM SM. We report the numerical results obtained for the design of two real consumer circuits provided by STMicroelectronics, and we compare these results with the ones obtained using the industrial benchmark currently adopted at STMicroelectronics for yield optimization. These preliminary results show that the method is promising to be very efficient and capable of reaching design solutions with high values of the yield. [ABSTRACT FROM PUBLISHER]

Power converters in the system-level real-time simulation are usually emulated by L/C-based associated discrete circuit (L/C-ADC). However, the L/C-ADC approaches may suffer from two issues: How to mitigate the unacceptable virtual power loss especially in high-frequency applications, and how to tune LC parameters setting which is affected by the external circuit. This paper proposes a novel generalized associated discrete circuit (G-ADC) model with parameterized history current sources. By utilizing the stability region of the feasible parameter space, the optimized G-ADC models with the best damping characteristic are developed for both two-level and three-level converters. The analytical results also guarantee that the parameters of the optimized G-ADC model are independent of the external circuit for most power grid applications. Furthermore, an field programmable gate array (FPGA)-based real-time simulation platform is built to verify the feasibility of the proposed scheme. Extensive simulation and hardware-in-loop experiment results demonstrate the effectiveness and superiority of best-damped models as well as the modeling flexibility corresponding to insensitivity to operating conditions and external system parameters. [ABSTRACT FROM AUTHOR]

Due to the repeated switching, the detailed switch-level models of electrical machines coupled with power-electronic converters are computationally expensive and hard to linearize for small-signal frequency-domain analysis. Average-value modeling (AVM) has become an effective tool for small-signal analysis of power electronic systems and time-domain transient studies where the details of switching are not important and can be neglected. Recently, a parametric AVM (PAVM) approach has been developed for machine/diode rectifier systems. This paper extends the parametric approach to the machine/thyristor-controlled-rectifier systems, where the thyristor firing may be referenced to either the line voltages or the rotor position. An analytical average model for this system is also developed based on the recently proposed constant-parameter voltage-behind-reactance synchronous machine model. The new PAVM is compared against the original switching system, as well as the analytical AVM. It is shown that the PAVM can accurately predict both small-signal characteristics and large-signal transients of the original switching system in light and heavy modes, which represents an advantage over the analytical models which are typically implicit. [ABSTRACT FROM AUTHOR]

This paper presents photovoltaic-oriented nodal analysis (PVONA), a general and flexible tool for efficient spatially resolved simulations for photovoltaic (PV) cells and modules. This approach overcomes the major problem of the conventional Simulation Program with Integrated Circuit Emphasis-based approaches for solving circuit network models, which is the limited number of nodes that can be simulated due to memory and computing time requirements. PVONA integrates a specifically designed sparse data structure and a graphics processing unit-based parallel conjugate gradient algorithm into a PV-oriented iterative Newton–Raphson solver. This first avoids the complicated and time-consuming netlist parsing, second saves memory space, and third accelerates the simulation procedure. In the tests, PVONA generated the local current and voltage maps of a model with $316 \times 316$ nodes with a thin-film PV cell in 15 s, i.e., using only 4.6% of the time required by the latest LTSpice package. The 2-D characterization is used as a case study and the potential application of PVONA toward quantitative analysis of electroluminescence are discussed. [ABSTRACT FROM AUTHOR]

A novel data-driven simulation-based diagnostic model is proposed to realize automatic and practical testability analysis (TA) of analog circuits. With this model and the corresponding methods, sufficient faults can be handily injected into the circuit under test and then be simulated to construct the sample data. Using these data, a kernel density estimation on ${K}$ -nearest neighbors classification algorithm and its leave-one-out cross-validation method are studied to evaluate the testability metrics. To handle the possible high false alarm caused by the faults that have similar samples with the fault-free case, two strategies are carried out by ignoring the faults in the ambiguity groups or/and using the posterior weights to determine the final classification results. Furthermore, a sample compression approach is proposed to reduce the computational cost. Experimental results show that more accurate and reasonable TA and verification can be achieved by comparing with the traditional testability models and the state-of-the-art classification methods. And the diagnostic application against a real circuit based on the simulation data can also reach a satisfactory level. [ABSTRACT FROM AUTHOR]

The signal distribution interconnect network modeling plays an important role during the digital/mixed printed circuit board (PCB) design. With the increase of the design complexity, the PCB interconnect modeling becomes a challenging task. This paper proposes an innovative circuit theory of the PCB electrical interconnects modeling based on the tensorial analysis of network (TAN). The model under study, fundamentally built with the Kron–Branin formalism, is applied to the asymmetrical 1:3 Y-Y-tree interconnects. This Kron–Branin method enables to establish quickly the tree interconnects equivalent model for the signal integrity (SI) analysis. An asymmetrical microstrip circuit was designed and fabricated to validate the developed TAN concept. The modeled, simulated, and measured S-parameters are in good agreement in the broad frequency band 0.1 MHz to 8 GHz. The electrical power budget distributed through the Y-Y-tree prototype in dc and in the considered entire frequency band was analyzed. Furthermore, the Kron–Branin model was also validated in the time domain with 1-Gb/s-rate 8-bits serial data and eye diagram analyses. This innovative formalism presents a considerably high computation speed and is beneficial for the SI analyses thanks to its adaptability to the complex system. [ABSTRACT FROM AUTHOR]

Approximate adders are widely being advocated as a means to achieve performance gain in error resilient applications. In this paper, a generic methodology for analytical modeling of probability of occurrence of error and the Probability Mass Function (PMF) of error value in a selected class of approximate adders is presented, which can serve as performance metrics for the comparative analysis of various adders and their configurations. The proposed model is applicable to approximate adders that comprise of sub-adder units of uniform as well as non-uniform lengths. Using a systematic methodology, we derive closed form expressions for the probability of error for a number of state-of-the-art high-performance approximate adders. The probabilistic analysis is carried out for arbitrary input distributions. It can be used to study the dependence of error statistics in an adder’s output on its configuration and input distribution. Moreover, it is shown that by building upon the proposed error model, we can estimate the probability of error in circuits with multiple approximate adders. We also demonstrate that, using the proposed analysis, the comparative performance of different approximate adders can be correctly predicted in practical applications of image processing. [ABSTRACT FROM AUTHOR]

Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods. [ABSTRACT FROM AUTHOR]

Dynamic thermal management (DTM) techniques are being widely used for attenuation of thermal hot spots in many-core systems. Conventionally, DTM techniques are analyzed using simulation and emulation methods, which are in-exhaustive due to their inherent limitations and cannot provide for a comprehensive comparison between DTM techniques owing to the wide range of corresponding design parameters. In order to handle the above discrepancies, we propose to use model checking, a state-space-based formal method, to model, evaluate, and compare DTM techniques across various functional and performance parameters. The suggested framework includes a modeling flow and a set of generic modules that realistically model many-core and DTM parameters like temperature, power, application, intercore communication and task migration, etc. For analysis purpose, the framework provides a common ground for comparing DTM techniques by formalizing DTM principles and performance parameters as a set of logical properties. These properties are verified for different task load configurations, e.g., multithreaded, malleable, and the applications which do not support migration. We analyze state-of-the-art central (c-) and distributed (d-) DTM techniques to demonstrate the generality and efficacy of our approach. Our formal analysis shows that the state-of-the-art cDTM technique performs better than dDTM in terms of achieving thermal stability, task migration, and communication overhead. We believe that conventional analysis methods do not facilitate such an exhaustive comparison among the DTM techniques. [ABSTRACT FROM AUTHOR]

An internal charging (IC) analysis of the active measurement box of electrostatic risk (AMBER) instrument onboard Jason-3 in polar earth orbit (PEO) has been performed with a new dedicated modeling chain. The ExtendeD Gdml Editor (EDGE) application is in charge of the definition of the computer-aided design (CAD) model. The Modelling Of Radiation (MoORa) front end helps to configure, control, and postprocess the ESA/GRAS Monte Carlo simulation based on Geant4 to model the transport of space radiation environment. Finally, using the radiation results, the IC analysis, including internal electric fields and risk of discharge, is performed with the Spacecraft Plasma Interaction Software (SPIS)-IC 3-D time-dependent simulation code. [ABSTRACT FROM AUTHOR]

We present a numerical modeling and simulation paradigm for multidomain, multiphysics systems with components modeled both in a lumped and distributed manner. The lumped components are modeled with a system of differential-algebraic equations (DAEs), whereas the possibly nonlinear distributed components that may belong to different physical domains are modeled using partial differential equations (PDEs) with associated boundary conditions. We address a comprehensive suite of problems for nonlinear coupled DAE–PDE systems including 1) transient simulation; 2) periodic steady-state (PSS) analysis formulated as a mixed boundary value problem that is solved with a hierarchical spectral collocation technique based on a joint Fourier–Chebyshev representation, for both forced and autonomous systems; 3) Floquet theory and analysis for coupled linear periodically time-varying DAE–PDE systems; 4) phase noise analysis for multidomain oscillators; and 5) efficient parameter sweeps for PSS and noise analyses based on first-order and pseudo-arclength continuation schemes. All of these techniques, implemented in a prototype simulator, are applied to a substantial case study: a multidomain feedback oscillator composed of distributed and lumped components in two physical domains, namely, a nano-mechanical beam resonator operating in the nonlinear regime, an electrical delay line, an electronic amplifier and a sensor-actuator for the transduction between the two physical domains. [ABSTRACT FROM AUTHOR]

On-chip communication system design starting from a high-level model can facilitate formal verification of system properties, such as safety and deadlock freedom. Yet, analyzing its quality-of-service (QoS) property, in our context, per-flow delay bound, is an open challenge. Based on executable micro-architectural specification (xMAS) which is a formal framework modeling communication fabrics, we first present how to model a classic input-queuing virtual channel router using the xMAS primitives and then a QoS analysis methodology using network calculus (NC). Thanks to the precise semantics of the xMAS primitives, the router can be modeled in different variants, which cannot be otherwise captured by normal ad hoc box diagrams. The analysis methodology consists of three steps: 1) given network and flow knowledge, we first create a well-defined precise xMAS model for a specific application on a concrete on-chip network; 2) the specific xMAS model is then mapped to an NC graph (NCG) following a set of mapping rules; and 3) finally, existing QoS analysis techniques can be applied to analyze the NCG to obtain end-to-end delay bound per flow. We also show how to apply the technique to a typical all-to-one communication pattern on a binary-tree network and conduct an SoC case study, exemplifying the step-by-step analysis procedure and discussing the tightness of the results. [ABSTRACT FROM AUTHOR]

Parametric yield estimation is a critical task for design and validation of analog and mixed-signal (AMS) circuits. However, the computational cost for yield estimation based on Monte Carlo (MC) analysis is often prohibitively high, especially when multiple circuit performances and/or environmental corners (e.g., voltage and temperature corners) are considered. In this paper, a novel statistical method named correlation-aided yield estimation (C-YES) is proposed to reduce the computational cost for parametric yield estimation. Our proposed approach exploits the fact that multiple circuit performances over different environmental corners are often correlated. Hence, we can accurately predict the performance value at one corner from the simulation results for other performances and/or corners. Based upon this observation, instead of running a large number of MC simulations to cover all performances and corners, an efficient algorithm is developed to select a small set of the most “informative” simulations that should be performed for yield estimation. Our numerical experiments show that for parametric yield estimation with multiple circuit performances and environmental corners, C-YES achieves 6.5– 9.3 \boldsymbol \times runtime speedups over other conventional methods. [ABSTRACT FROM PUBLISHER]

Fully formal verification of perception models is likely to remain challenging in the foreseeable future, and yet these models are being integrated into safety-critical control systems. We present a practical method for reasoning about the safety of such systems. Our method is based on systematically constructing approximations of perception models from system-level safety requirements, data, and program analysis of the modules that are downstream from perception. These approximations have some desirable properties like being low-dimensional, intelligible, and tractable. The closed-loop system, with the approximation substituting the actual perception model, is verified to be safe. Establishing the formal relationship between the actual and the approximate perception models remains well beyond available verification techniques. However, we do provide a useful empirical measure of their closeness called precision. Overall, our method can tradeoff the size of the approximation against precision. We apply the method to two significant case studies: 1) a vision-based lane tracking controller for an autonomous vehicle and 2) a controller for an agricultural robot. We show how the generated approximations for each system can be composed with the downstream modules and be verified using program analysis tools like CBMC. Detailed evaluations of the impacts of size, and the environmental parameters (e.g., lighting, road surface, and plant type) on the precision of the generated approximations suggest that the approach can be useful for realistic control systems. [ABSTRACT FROM AUTHOR]