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In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

A 650-V/84-mΩ normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally-off gate control, and a 650-V normally-on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QG×RON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs. [ABSTRACT FROM AUTHOR]

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this article, we demonstrate a GaN-based gate driver with an overcurrent (OC) protection circuit and an undervoltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, the OC protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power devices. The OC protection is implemented with a separated sensing branch and blanking time controller, and the response time to an OC event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V, and its threshold voltage is especially tailored for the GaN integrated circuits. [ABSTRACT FROM AUTHOR]

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad. [ABSTRACT FROM AUTHOR]

In this article, the impacts of the off-state gate bias (VGS,OFF) on dynamic on-resistance (RON) are systematically investigated in commercial Schottky-type p-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed I–V system are adopted to evaluate the dynamic RON with various off-state gate and drain bias (VDS,OFF) under hard- and soft-switching conditions. More negative VGS,OFF can aggravate the dynamic RON degradation under both soft- and hard-switching, especially when switching with a high VDS,OFF. The impacts of VGS,OFF on switching transients and off-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The off-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

Recently, a GaN reverse-conducting high-electron-mobility transistor (RC-HEMT) has been demonstrated. The RC-HEMT features built-in distributive Schottky contacts, which provide a low-loss freewheeling path. The RC-HEMT offers the same functionality as an HEMT/Schottky barrier diode (SBD) pair, but consumes much less chip area, thus its ${R}_{ \mathrm{\scriptscriptstyle ON}}$ (ON-resistance $\times $ total device width) is significantly reduced. Theoretically, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT can approach that of an HEMT. In practice, due to certain geometry limitations, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of an RC-HEMT lies between an HEMT/SBD pair and a single HEMT. This work investigates the factors that influence ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT using both experimental measurements and numerical simulations. It is found that ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is strongly affected by the geometry of the source and channel regions, where HEMT sections and SBD sections are interdigitally distributed. With coarse patterning of these regions, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is close to the HEMT/SBD pair. Through proper geometry scaling, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of RC-HEMT is reduced and approaches that of HEMT. [ABSTRACT FROM AUTHOR]

The short circuit (SC) behavior of a newly developed GaN-HEMT/SiC-JFET cascode device is investigated in this work. The reverse leakage current through the drain-side PN junction (IR) of the SiC JFET under SC conditions is measured simultaneously during the SC event. IR of the SiC JFET increases to 6.4 A at the end of a 5-μs nondestructive SC pulse. The increase of IR during the SC pulse induces a turning point in the SC current waveform and a dramatic negative threshold voltage shift (>30 V) in the SiC JEFT, resulting in high transient drain-to-source voltage in the GaN HEMT. The underlying mechanism is associated with the increase of local potential in the P-type layer of the SiC JFET with inevitable spread resistance (RSPD). It is suggested that reducing RSPD can improve SC capability and high IR should be considered in SC failure mechanism analysis and the design of external gate resistance of the SiC JFET. [ABSTRACT FROM AUTHOR]

Short circuit (SC) capability of 650-V Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under single and repetitive tests is characterized in this article. The investigated devices exhibit strong capability under a single SC test, but weak capability under repetitive SC tests with a bus voltage of 400 V and a gate drive voltage of 6 V. The failure mechanism under repetitive SC tests is revealed through electrothermal simulation and microscale failure spot analysis. Thermal fatigue cracks are formed due to the high temperature spike and local temperature fluctuations in the narrow GaN channel and buffer layers, leading to weak repetitive SC capability. The unique heat confinement effect in the GaN layer plays an important role in the formation of high temperature spike and fatigue cracks. The withstand time in a single SC test is several hundred microseconds due to fast drain current drop that results from high temperature and, to a lesser degree, the dynamic threshold voltage shift during the SC transient. The device failure in a single-event SC test is related to heat diffusion to a wider region. Some guidelines are proposed for handling and improving the repetitive SC capability. [ABSTRACT FROM AUTHOR]

The threshold voltage (VTH) of an enhancement-mode Schottky-type p-GaN gate high-electron-mobility transistor (HEMT) is found to have a special dependence on the drain bias. The device commonly requires higher gate voltage to switch on the transistor from a high-drain-voltage off-state than what is expected from the static device characteristics. The reason behind the dynamic VTH has been proved to be the floating p-GaN layer, where charges could be stored and further influence VTH under different drain bias. In this article, a SPICE-compatible equivalent circuit model is presented according to the structure of Schottky-type p-GaN gate HEMTs. It features a floating node to imitate the charge storage process within the gate stack. Compared to conventional models, the proposed model could accurately predict the dynamic VTH characteristics and switching behaviors of power electronics circuits, where Schottky-type p-GaN gate HEMTs are deployed as power transistors. The phenomena related to the dynamic VTH, including the disappearance of Miller plateau, the overestimated false-turn-on problem, and the higher reverse conduction loss are evaluated with a half-bridge circuit and the merits of the proposed model are verified. [ABSTRACT FROM AUTHOR]

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p-GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on-resistance (RON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage (VTH), and no dynamic RON degradation. To identify its safe operation in the off-state with a high drain bias, the off-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. A relatively low off-state VM is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic VTH shift; and 2) suppress the increased dynamic off-state leakage current (IOFF) induced by on-state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn-on and 121 V/ns during turn-off is achieved. [ABSTRACT FROM AUTHOR]

A 1200-V/100-mΩ silicon carbide (SiC) junction field-effect-transistor (JFET)/ gallium nitride (GaN) high-electron-mobility-transistor (HEMT) hybrid power switch is demonstrated, which features a flip-chip copackaged cascode configuration incorporating a vertical SiC JFET and a lateral GaN-HEMT. The high-voltage SiC-JFET provides the high-voltage blocking capability while the low-voltage GaN-HEMT enables the normally-off gate control with superior switching characteristics. Compared to conventional SiC-JFET/Si-mosfet cascode devices, the SiC-JFET/GaN-HEMT cascode device exhibits fast switching speed, which has been validated by systematic characterizations including static/dynamic device-level measurements and board-level hard-switching tests. Meanwhile, the device is free from several notorious issues of high-voltage GaN power transistors such as dynamic on-state resistance degradation and threshold voltage shift. Such a wide-bandgap semiconductor-based hybrid switch is suitable to be deployed in high-power and high-efficiency power conversion systems. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage (I–V) characteristics and threshold voltage (${V}_{\text {TH}}$) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier. [ABSTRACT FROM AUTHOR]

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations. [ABSTRACT FROM AUTHOR]

(Al)GaN recess-free normally OFF technology is developed for fabrication of high-yield lateral GaN-based power devices. The recess-free process is achieved by an ultrathin-barrier (UTB) AlGaN/GaN heterostructure that features a natural pinched-off 2-D electron gas channel. The top–down manufacturing technique overcomes the challenges in etching of AlGaN barrier with well-controlled depth and uniformity, which is especially attractive for fabrication of normally OFF GaN-based high-electron-mobility transistors (HEMTs) and metal–insulator–semiconductor HEMTs (MIS-HEMTs) on large-size Si substrate. With SiNx passivation grown by low-pressure chemical-vapor deposition, on-resistance of the UTB-AlGaN/GaN-based power devices can be significantly reduced. High-uniformity low-hysteresis normally OFF HEMTs and Al2O3/AlGaN/GaN MIS-HEMTs are successfully demonstrated on the UTB AlGaN/GaN-on-Si platform. It is also a compelling technology platform for manufacturing high-performance GaN-based lateral power diodes, and normally OFF p-(Al)GaN heterojunction field-effect transistors. [ABSTRACT FROM PUBLISHER]

Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance (RON) of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been investigated by using ramped and transient back-gating characterizations as well as TCAD simulations. High voltage applied to the conductive Si substrate can modulate 2DEG conductivity through the back-gate effect, whereby the dynamics of both acceptor and donor buffer traps are identified. Distinct buffer trapping and asymmetric vertical leakage under opposite top-to-substratebias polarities have been observed, which are attributed to the fundamentally different carrier injection/transport mechanisms. It is suggested that the energy barrier at the nucleation-layer/Si interface can limit the electron injection from Si substrate into the buffer stack and consequently influence the bufferrelated current collapse. [ABSTRACT FROM AUTHOR]

The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance $R_{{\rm{ON}}}$ and threshold voltage $V_{{\rm{TH}}}$ are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic RON is found to exhibit different dependence on the gate drive voltage $V_{{\rm{GS}}}$ from the static $R_{{\rm{ON}}}$. While reasonably suppressed at higher $V_{{\rm{GS}}}$ of 5 and 6 V, the degradation in dynamic RON is significantly larger at lower $V_{{\rm{GS}}}$ of 3–4 V, which is attributed to the positive shift in $V_{{\rm{TH}}}$ under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the $V_{{\rm{TH}}}$ shift on the dynamic $R_{{\rm{ON}}}$; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices. [ABSTRACT FROM AUTHOR]

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level $E1$ with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while $E2$ with an activation energy of 0.22 eV is located in the buffer layer. [ABSTRACT FROM AUTHOR]

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth. [ABSTRACT FROM AUTHOR]

We report the first gallium nitride (GaN)-based pulse width modulation (PWM) integrated circuit (IC) featuring monolithically integrated enhancement- and depletion-mode high electron mobility transistors and lateral field-effect rectifiers on the GaN smart power technology platform. The PWM IC is able to generate 1-MHz PWM signal with its duty cycle modulated effectively by a reference voltage ( Vc) over a wide range with good linearity. It features a 5 V supply voltage and is composed of a sawtooth generator and a comparator, both of which can be operated at 1 MHz and exhibit proper functionality over a wide temperature range (from 25 °C to 250 °C). This circuit demonstration further proves the feasibility of an all-GaN solution that features monolithically integrated peripheral gate control circuits and power switches for GaN power converters. An all-GaN solution would lead to a compact system with improved efficiency and enhanced reliability. [ABSTRACT FROM AUTHOR]

Al2O3–AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) featuring indium tin oxide transparent gate electrode are fabricated for the purpose of evaluating the gate reliability. The transparent gate electrode allows electroluminescence (EL) observation in the region directly under the gate, which cannot be performed in conventional MIS-HEMTs with opaque gate electrode. Normally OFF transparent-gate MIS-HEMTs were realized by implanting fluorine ions into the AlGaN barrier prior to the deposition of Al2O3. The dependence of EL on bias condition was investigated with the color of EL resolved by filters. Gate dielectric degradation in MIS-HEMTs was induced by OFF state drain-bias stress, as detected by the increased gate leakage current. Location of the gate degradation could be clearly identified by EL imaging through the transparent gate. From the EL image, the passivation layer under the overhang of T-shaped gate is found to be vulnerable to OFF-state stress, which is confirmed by simulation. [ABSTRACT FROM AUTHOR]

We investigate in detail the influence of AlN passivation on dynamic ON-resistance ( \(R_{\mathrm{{\scriptstyle ON}}}\) ) and electric field ( \(E\) -field) distribution in high-voltage AlGaN/GaN high electron mobility transistors (HEMTs) on a Si substrate based on pulsed \(I\) – \(V\) measurements, electroluminescence (EL) microscopy, and 2-D physics-based numerical device simulations. It is found that the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) increase has been significantly suppressed to below 10% at various temperatures ranging from −50 to 200 °C owing to the effective and robust compensation of deep acceptor-like trap states at the AlN/GaN (passivation/cap) interface by the additional positive polarization charges induced in the epitaxial AlN thin passivation layer grown in a plasma-enhanced atomic layer deposition system. To the best of our knowledge, this is the first time that highly suppressed current collapse in an AlGaN/GaN HEMT on a Si substrate within a wide temperature range is ever reported. By monitoring the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) for 100 consecutive 133-kHz switching cycles, its variation is observed to be less than 2.5%, indicating excellent stability of the passivation effectiveness. The electric field in an AlN-passivated device is found to be well confined at the drain-side gate edge, as shown in EL measurement and numerical simulation results. This phenomenon directly suggests that the virtual gate effect arising from surface trap charging has been effectively alleviated by the AlN passivation technique. [ABSTRACT FROM AUTHOR]