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A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

A 650-V/84-mΩ normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally-off gate control, and a 650-V normally-on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QG×RON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs. [ABSTRACT FROM AUTHOR]

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad. [ABSTRACT FROM AUTHOR]

GaN ${p}$ -channel field-effect transistors (${p}$ -FETs) are essential components for implementing the energy-efficient complementary logic circuitry for monolithic GaN power integration. This letter reports the threshold voltage (${V}_{\mathrm {TH}}$) instability of ${p}$ -channel GaN MOSFETs with Al2O3 as the gate dielectric. When the gate-to-source bias sweeps toward the negative direction, the ${V}_{\mathrm {TH}}$ exhibits a shift toward more negative values. The impacts of such ${V}_{\mathrm {TH}}$ instability on GaN complementary logic circuits are characterized using logic inverters and ring oscillators. It is shown that impacts on circuit functions are limited with an operating voltage swing below 5 V. However, the propagation delay could be gradually prolonged, as a result of the drifting ${V}_{\mathrm {TH}}$. [ABSTRACT FROM AUTHOR]

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p-GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on-resistance (RON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage (VTH), and no dynamic RON degradation. To identify its safe operation in the off-state with a high drain bias, the off-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. A relatively low off-state VM is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic VTH shift; and 2) suppress the increased dynamic off-state leakage current (IOFF) induced by on-state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn-on and 121 V/ns during turn-off is achieved. [ABSTRACT FROM AUTHOR]

A dual-gate superjunction insulated gate bipolar transistor (IGBT) (DG-SJ-IGBT) is proposed and studied with numerical TCAD simulations. The new structure utilizes the superjunction structure as a controlling port for the strength of conductivity modulation inside the IGBT, so that a low VON is obtained by a strong conductivity modulation during ON-state and a near-unipolar turn-off is achieved by removing the minority carriers before the turn-off event. For this purpose, the p-pillar in the DG-SJ-IGBT is connected to the p-body using a built-in p-channel MOSFET. The primary gate and the auxiliary gate (i.e., gate of p-MOSFET) are controlled by two separate driving signals. In the IGBT’s ON-state, the p-MOSFET disconnects the p-pillar, enabling full conductivity-modulated bipolar conduction and a consequent low VON. As a well-known issue, conductivity modulation is accompanied by significant additional turn-off loss (EOFF). To overcome this issue, the DG-SJ-IGBT takes advantage of the p-pillar which extends through the entire drift region. Before the IGBT’s turn-off event, the p-MOSFET electrically grounds the p-pillar to the p-body. The grounded p-pillar serves as a hole extractor, suppresses the minority carrier density throughout the depth of the drift region, and brings the device into a near-unipolar conduction mode. Thus, a near-unipolar turn-off can be obtained, resulting in a low EOFF. [ABSTRACT FROM AUTHOR]

A new superjunction MOSFET (SJ-MOSFET) architecture with dual built-in Schottky diodes is proposed and studied with the numerical TCAD simulations. This letter is based on silicon. One Schottky contact is formed at the top of the n-pillar, while the other is formed at the bottom of the p-pillar. During the reverse conduction period, the Schottky junctions turn on at a lower voltage than the PN junction. The current flows through n-pillar and p-pillar in parallel, so the potential difference across the PN junction is kept below its turn-on voltage. Thus, minority carrier injection through the PN junction is completely suppressed, leading to a superior reverse recovery performance. Integration of a single Schottky contact to either the n-pillar or the p-pillar cannot completely suppress the turn-on of the PN junction in the SJ-MOSFET due to the potential drop created by the current through only one type of the pillars. Furthermore, the proposed dual-Schottky SJ-MOSFET reduces the gate charge (${Q} _{\mathrm {G}}$) and the gate-to-drain charge (${Q} _{\mathrm {GD}}$), compared with the conventional SJ-MOSFET, leading to better figures of merit. [ABSTRACT FROM AUTHOR]

A new silicon power MOSFET architecture is proposed by introducing a built-in channel diode through a dummy MOS gate electrically coupled to the source. The oxide thickness of the channel diode is reduced to obtain a desired turn-ON voltage and attenuate the minority carrier injection from the PN junction body diode. Consequently, the proposed MOSFET is able to deliver superior reverse recovery characteristics, including reductions in reverse recovery charge ($Q_{\sf RR}$) and peak reverse recovery current ($I_{\mathrm{ RRM}}$) by a factor of ~4.2 and ~2.6, respectively. The breakdown voltage (232 V) of the proposed MOSFET is the same as the conventional MOSFET. The on-resistance of the proposed MOSFET (8.5 $\text{m}\Omega \cdot \text {cm}^{{2}}$) is only slightly increased compared with conventional MOSFET (8.0 $\text{m}\Omega \cdot \text {cm}^{{2}}$). The gate-to-drain charge ($Q_{\sf GD}$) and gate charge (${Q} _{\mathsf {G}}$) are reduced by a factor of ~7.2 and ~3.9, respectively. Significantly improved figures of merit (${R} _{ON} \times {Q}_{\mathsf {G}}$ and ${R} _{ON} \times {Q}_{\mathsf {GD}}$ reduced by a factor of ~3.7 and ~6.8, respectively) are obtained in the proposed MOSFET. The device concept and characteristics are systematically analyzed with numerical TCAD simulations. [ABSTRACT FROM AUTHOR]

The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance $R_{{\rm{ON}}}$ and threshold voltage $V_{{\rm{TH}}}$ are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic RON is found to exhibit different dependence on the gate drive voltage $V_{{\rm{GS}}}$ from the static $R_{{\rm{ON}}}$. While reasonably suppressed at higher $V_{{\rm{GS}}}$ of 5 and 6 V, the degradation in dynamic RON is significantly larger at lower $V_{{\rm{GS}}}$ of 3–4 V, which is attributed to the positive shift in $V_{{\rm{TH}}}$ under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the $V_{{\rm{TH}}}$ shift on the dynamic $R_{{\rm{ON}}}$; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices. [ABSTRACT FROM AUTHOR]

The high OFF-state oxide field in the SiC trench MOSFET is a threat for its long term reliability, and thus hinders the wide acceptance of the SiC trench MOSFETs. In this paper, an SiC trench MOSFET with protruded p-bases (PB-MOS) is proposed, which features protruded p-bases to shield the gate oxide at the trench bottom against the high OFF-state drain voltage. Numerical device simulations based on Sentaurus TCAD verify the benefits of the structure. The OFF-state oxide field ( E\text {ox-m} ) in the PB-MOS is 1.7 MV/cm, which is dramatically lower compared to the high E\text {ox-m} of 8.6 MV/cm in the conventional trench MOSFET (C-MOS). The above benefit is achieved without sacrificing device performances. The reverse transfer capacitance ( C\text{rss} ) of the PB-MOS is around ten times lower than that in the C-MOS. Both the gate charge ( Q\text{G} ) and the gate-to-drain charge ( Q\text{GD} ) of the PB-MOS are significantly improved compared to the C-MOS. A low specific ON-resistance ( R\text{ON} ) is maintained in the PB-MOS by using additional JFET doping to compensate the JFET effect. As a result, the PB-MOS presents much better figures of merit Q\text{G} \cdot { {R}}\text{ON} and Q\text{GD} \cdot { {R}}\text{ON} than those of the C-MOS. The PB-MOS achieves a much faster switching speed than the C-MOS, and consequently exhibits an appreciable reduction in the switching energy loss. [ABSTRACT FROM PUBLISHER]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

We propose a SiC trench/planar MOSFET (TP-MOS) which features a trench channel and a planar channel in one half-cell. Numerical simulations with Sentaurus TCAD have been carried out to study the proposed device architecture. Compared with traditional planar MOSFET (P-MOS), the TP-MOS has a much lower R \mathrm {ON} owing to the increased channel density. Unlike traditional trench MOSFET (T-MOS) which enables a higher channel density at the price of a high bottom-oxide field in the high-voltage OFF-state, the TP-MOS features bottom p-bases as in the P-MOS that protect the gate oxide from high electric field. The OFF-state oxide field in the TP-MOS is found to be even lower than the P-MOS. In addition, the TP-MOS boasts a low feedback capacitance ( C \mathrm {rss}) and gate-to-drain charge ( Q \mathrm {GD}) , since the coupling between the gate and the drain is suppressed by the collective effects of the top p-bases and the bottom p-bases. The Q \mathrm {G} of the TP-MOS is nearly the same as the P-MOS, and is much smaller than the T-MOS. Superior figures of merit ( Q \mathrm {G}\times {R} \mathrm {ON} and Q \mathrm {GD}\times {R} \mathrm {ON}) are achieved in the TP-MOS. [ABSTRACT FROM AUTHOR]

A GaN/SiC hybrid field-effect transistor (HyFET) is proposed as a high-voltage power device that provides a high-mobility lateral AlGaN/GaN channel to reduce the channel resistance and a vertical SiC drift region to sustain the high OFF-state voltage. The performance of the HyFET is evaluated by numerical device simulations. Compared with the conventional SiC MOSFET, the HyFET exhibits a greatly reduced R\mathrm{\scriptscriptstyle ON} together with a low C\mathrm{ GD} and low gate charges. The figures of merit Q\mathrm{ G}\times R\mathrm{\scriptscriptstyle ON} and Q\mathrm{ GD}\times R\mathrm{\scriptscriptstyle ON} of the HyFET are dramatically improved. [ABSTRACT FROM AUTHOR]