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We have proposed "PN-Body Tied SOI FET (PNBT-FET)" as a candidate of steep subthreshold slope (SS) devices, such as tunnel FETs and negative capacitance FETs, which will be a key device for expanding ultralow power IoT applications. We have already reported that PNBT-FET has SS below 1mV/dec over several orders of the drain current even with ultralow drain voltage of 0.1V [1] – [2] . We also reported the drain current (Id) enhancement effect on PNBT-FET, at previous IEEE SNW [3] .

We report for the first time the measured transfer characteristics of CMOS inverter using the steep subthreshold slope (SS) PN-Body Tied (PNBT) SOI-FET. When the position of SS of both NMOS and PMOS are overlapped, it shows a surprisingly very steep, ideally right angle, transfer characteristic, compared with the case of the conventional SOI-CMOS. It is an interesting finding when using the real ideally steep SS device, such as PNBT SOI-FET.

We investigated the mechanism of the PN-body tied (PNBT) silicon on insulator (SOI) field effect transistor (FET) with a 65 nm thin buried oxide (Box) FD-SOI technology. We clarified the mechanism by which the 65 nm PNBT-SOI-FET shows steep subthreshold slope (SS) only with negative or positive substrate bias (V sub ). We compared this behavior with a 200nm SOI-FET technology, which needs no V sub to exhibit steep SS. It coincides with our first measured confirmation of the steep SS on the 65 nm SOI technology. The hole accumulation in channel by the V sub and also the gate voltage is a key for the 65 nm PNBT SOI-FET because the 65 nm SOI-FET is a more fully depleted SOI. The specific shift of the steep SS voltage was also analyzed.

In this paper, the diode characteristics of our newly proposed super-steep subthreshold slope “PN-body tied (PNBT) silicon-on-insulator field-effect transistor” are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.

Characteristics of the super-steep subthreshold slope (SS) PN-body tied (PNBT) SOI-FET was confirmed with the 65 nm thin buried oxide (Box) fully depleted (FD)-SOI process, for the first time. The substrate bias (Vsub) was necessary for inducing the super-steep SS on 65 nm PNBT SOI-FETs. It is noted that the super-steep SS is observed with the negative and also the positive Vsub. The body current was below one tenth of the drain current. The trade-off between Ion/Ioff ratio and the hysteresis window was also shown. The confirmation of the super-steep SS PNBT SOI-FET on 65 nm technology is adding to confirmation on 200 nm SOI technology, so far, and is also valuable for ultralow power applications.

We report the effect of the substrate bias (V sub ) and the positive charge (Q ox ) in the buried oxide (BOX) on P-channel / N-channel super steep subthreshold slope (SS) “PN Body-Tied (PNBT) SOI-FET”. The Q ox in the BOX was evaluated with the specific test device. Removing the effect of the Q ox and realizing the super steep SS, the necessity of V sub, especially on P-channel, was systematically confirmed with measurements and simulations. It was founded out that the positive feedback by PNBT contributes to making the barrier height for reducing the leakage current and realizing the super steep SS, although the difference of the static barrier height is small only with V sub and the Q ox . We also propose modification on PNBT structure for realizing CMOS without V sub bias.

Numerous numbers of IoT sensors could be distributed to environments to persistently monitor the environments and send the acquired data by wireless manner in the era of Trillion Sensor Universe. Therefore, the IoT sensors need to have battery less power supply systems. This paper is focusing on device characteristics of RF energy harvesting systems. RF characteristics of the devices of 65nm SOTB and Super-Steep Transistor, which are suitable for efficiently rectifying the RF signal, are shown. The experiments for RF energy harvesting from ambient RF signals using the 65nm SOTB device and cross couple rectifier exhibits more than 1uW power generations.

In this study, the precise transient mechanism of the super-steep subthreshold slope PN-body-tied (PNBT) silicon on insulator field-effect transistor (SOI-FET) is clarified by using technology computer-aided design. We found out that the operation mechanism differs between the turn-on and turn-off. Additionally, a new PNBT SOI-FET structure with a second gate for the high-speed operation is proposed and we showed that the new structure can reduce the leakage current upon the turn-off.

In this paper, simulational and experimental investigations on the 1 MHz band rectenna in nW operation are described for energy harvesting from AM radio waves. For the objective, a commercial based SBD, a Cross couple CMOS Pair (CCP) IC and a super-steep subthreshold slope PN-body tied SOI-MOSFET (PNBT) diode are investigated as rectifier devices in nW region. In experiments with the CCP IC, efficiency of 9.4 % at -41 dBm can be obtained. In simulation with the PNBT diode, efficiency of 30.3 % at -40 dBm can be estimated for our future step. These results clarify superior possibility for energy harvesting in wider service area with AM radio waves.

In this paper, the high sensitive 2.4 GHz band rectenna with direct matching topology is described. The rectenna is consisting of the inductive planar 3-strip folded dipole antenna with 10 $\mathrm{k}\Omega$ impedance and the SOI-CMOS rectifier IC. The rectifier IC is fabricated on Global Foundries 40 nm SOI-CMOS for improvement of the rectification efficiency in $\mu \mathrm{W}$ region. Furthermore, the inductive planar 3-strip folded dipole antenna is proposed to be combined with the rectifier IC with capacitive admittance for direct impedance matching. The developed rectenna achieves the rectification efficiency of 14.7 % at the input power of -30 dBm.

In this paper, transient effects of the super-steep subthreshold slope (SS) “PN-body tied (PNBT) silicon-on-insulator field-effect transistor (SOI-FET)” were investigated by using technology computer-aided design simulation. It was founded that the PNBT SOI-FET has switching delay time due to the carrier charging and discharging affected by the Shockley-Read-Hall (SRH) recombination on the $W_{\mathrm{b}}$ region (Base of Bipolar). It is a specific mechanism of the PNBT SOI-FET, which results in the delay time from OFF to ON state and the long time of the leakage current from ON to OFF state.

The transient effect and the carrier charging effect were observed on the super steep SS “PN-Body Tied SOI FET”, for the first time, using pulse measurements. It was also founded that the delay time of the turn-on decreases to be near zero when the gate overdrive voltage is set to be 0.1~0.15V and the interval time between pulses is set to be below 10ms. Those are good news for low speed concerns of this device.

We have proposed the super steep subthreshold slope (SS) “PN-Body-Tied SOI-FET (PNBTFET)”. It shows the perfect DC characteristics as a steep SS device, which is one of hot topics on the current research of Si devices. It shows SS < mV/Dec over 5 decades of the drain current with an ultralow drain voltage down to 0.1V. The steep SS on N-channel and also on the P-channel PNBT-FET have already been demonstrated. The CMOS with PNBT-FETs will open LSI with the ultralow power supply voltage around 0.1V, which is promising for the ultralow power IoT edge systems. The ultralow voltage rectification of the 10mV amplitude has also been confirmed with the MOS diode of the PNBT-FET. It is also promising for high efficiency rectification on RF energy harvesting. The research status on the PNBT-FET is reviewed as well.

In this study, integrate and fire neuron by using a dual-gate (DG) PN-body tied (PNBT) silicon on insulator field-effect transistor (SOI-FET) was investigated. We found out that the DG PNBT SOI-FET has the integrate and fire function in a single device. The floating body and the positive feedback effect can perform the functions of the capacitor and comparator, respectively. The device can generate a continuous spike and also a single spike signal with the additional reset scheme. The reset action requires a recovery time, which can be controlled by voltage conditions. It has a chance of making a refractory period function. These characteristics mean that it is possible to realize the capacitor-less small footprint neuron circuit with the DG PNBT SOI-FET.

Rectification of the ultralow voltage signal, up to 10mV, was experimentally confirmed, for the first time, by our new device of the super steep subthreshold slope “PN-body Tied SOI-FET” (PNBT-FET). It comes from the surprisingly sharp turn-on characteristics of PNBT-FET, even with measuring on the ultra small voltage range. It is impossible with the conventional diodes, due to becoming the tangential line. Rectification up to 30 MHz was also confirmed with PNBT-FET. It is a good news for PNBT-FET because its conduction mechanism has the low speed concern. Those rectification demonstrations will be promising for small voltage rectification on RF energy harvesting and ultralow voltage sensing applications.

High-impedance folded dipole antennas (FDAs) consisting of three conductors are designed in order to improve rectification efficiency of energy harvesters. FDAs with $\mathbf{10k}\Omega$ -impedance designed for three terrestrial systems of DTV, cellular and Wi-Fi.

The surface state density (Qss) of SOI back Si/SiO 2 interfcae was evaluated by newly desiged Charge Pumping (CP) method-TEG. The CP method was also re-examied to apply to the thick oxide MOS. It was noted that the high volatge aplitude and attention on the slope on the gate pulse are nesessary to evaluate the Qss of SOI back interface made of the thick oxide. It was founded out that the Qss of SOI back interface (bonded wafer interface) is comparabe to that of the thermal oxidation interface and also that the Qss of Floating Zone (FZ) wafer is larger than that of Czochralski (CZ) wafer, and the Qss of FZ wafer varies from lot to lot.

We demonstrated a P-channel super steep Subthreshold Slope (SS) PN-Body Tied (PNBT) SOI FET, for the first time. We found out that the substrate bias is necessary for the appearance of the super steep SS on the P-channel PNBT. The device shows a super steep SS (

We have proposed a super steep Subthreshold Slope (SS) “PN-Body Tied SOI-FET”. It shows the super steep SS (∼ 35 μ V/dec) over 3 to 5 decades of the drain current with an ultra-low drain voltage down to 0.1V. We have also improved it to reduce the operating body voltage below 1V and have clarified that the floating body effect of the SOI is a key mechanism for appearance of a super steep SS. The research status on the device was reviewed, here.

We have studied a high impedance antenna in order to improve the rectifier efficiency for energy harvesting applications. Folded dipole antenna (FDA) with high impedance of over 10 kΩ is proposed. To obtain higher impedance stepup ratio compared with the conventional FDA, an FDA consisting with three strip conductors is investigated. Impedance stepup ratio is calculated and the results in theory, simulation and measurement are compared.

Gate controlled diode (GCD) characteristics with our newly proposed super steep subthreshold slope (SS) “PN-Body Tied SOI-FET” was shown, for the first time, compared with the conventional diodes. It shows the super steep characteristics, the low leakage current and the sharp On-characteristics even on the ultralow voltage range of 50mV. The simple circuit simulations also indicated that the GCD with “PN-Body Tied SOI-FET” will achieve the high efficiency rectification on the ultralow input power of the RF energy harvesting. Additionally, the slight shift of the voltage of the zero current was confirmed as a specific characteristics on this GCD.

The SOI floating body effect and to keep floating on both the N layer and the body are important for appearance of the super steep SS on the PN-Body tied SOI FET. It was confirmed for the first time with measuring the new test devices.

It was demonstrated that the body bias appearing the super steep Subthreshold Slope (SS) reduces from over 5V to below 1V on the PN-body tied SOIFET's which show the super steep SS with the ultralow drain voltage of 0.1V, when the impurity concentration of the N region on the body tied area is redesigned from the high concentration of the N+ to the low N−. The 3D device simulations also confirmed it and indicated that the optimum length of the N region exits on the different impurity concentration of it for appearing the super steep SS with the low body bias.

We demonstrated the high efficiency on the rectenna which is composed of the high impedance antenna and the optimized gate controlled diode (GCD), for RF energy harvesting. It was clearly shown that the high impedance and the cancelation of the parasitic capacitance (Cj) of the diode improve the rectification efficiency, by using the fabricated transmission line module. The rectification efficiency of 15% at input power of −15dBm around 500MHz was obtained with the first demonstration of the fabricated rectenna which is composed of the 1.6k Ω folded dipole antenna, the Cj canceler, and the optimized GCD.

We checked the minimum subthreshold slope (SS) on the SOI based super steep FET's. It was 35µV/dec over 3 decades of the drain current on the PN-body tied SOI FET. It is the minimum value, ever reported. We also obtained the phenomena by the hole accumulation effect in the body with the pulsed measurement, which is a key for the appearance of the super steep SS on the SOI based FET. If it is true, the device needs improvement.

In this paper, the 500MHz band low power rectenna with high sensitivity characteristic is described. The rectenna is consisting of the folded dipole antenna with a 1.6kΩ impedance and the Cockcroft-Walton type rectifier for improvement of the rectification efficiency and the output dc voltage. Furthermore an L-Type LPF is added to reduce the negative influence due to the junction capacitance of the SBD. The developed rectennas (stage number: 1, 2) achieve the rectification efficiency of 48.9 % (stage number: 1) and 43.1 % (stage number: 2) at −15dBm of the input power. In addition to above, the top level efficiency of 8.7 % (stage number:1) at the input power of −30dBm can be achieved. In the Tokyo are, the output dc voltage of 0.22 V can be measured at the 25 km point from the antenna tower.

We propose and demonstrate a super steep Subthreshold Slope (SS) new type SOI FET with a PN-body tied structure. It has a symmetry source and drain (S/D) structure. The device shows a super steep SS (

Autonomous systems are important for realization of the sensor network. The RF energy harvesting is one candidate of the power source for the systems. It extracts the electric power from the electromagnetic waves which exist environmentally [1]. We have chosen the wave of the Digital Terrestrial Television (DTTV) which frequency is around 500MHz, because the covered area and the expected power will become large, compared with others, e.g. the Wi-Fi and the cellular phone [2]. Although the DTTV is chosen, the expected received power is around or below the micro watts when the covered area is intended to be enlarged. Therefore, the most important issue of the RF energy harvesting is the high efficiency rectification on such ultralow input power level [1].

A card-type folded dipole antenna with high impedance and wideband characteristics was investigated for energy-harvesting applications. An impedance of more than 2000 O was realized by the high-impedance step-up ratio of the folded structure. A prototype of the antenna was designed with an EM simulator, and the simulated and measured results were compared. The measured results agreed with the simulated results, and the measured bandwidth was 4.5% of that corresponding to the four channels of digital TV broadcasting waves.

High-impedance wideband folded dipole antennas (FDAs) are proposed for energy harvesting applications in order to obtain high rectification efficiency. Design method of the FDA is discussed based on an equivalent circuit, and condition of high-impedance wideband characteristics is expressed with equations. As design examples, straight-type and card-type FDAs are described for the digital TV broadcasting waves in Japan.