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${p}$ -channel GaN field-effect transistors (FETs) with a SiNx/GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack are investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the ${p}$ -channel through the SiNx via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, $\sqrt {{\mathrm {E}}} $ model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. [ABSTRACT FROM AUTHOR]

In this article, the impacts of the off-state gate bias (VGS,OFF) on dynamic on-resistance (RON) are systematically investigated in commercial Schottky-type p-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed I–V system are adopted to evaluate the dynamic RON with various off-state gate and drain bias (VDS,OFF) under hard- and soft-switching conditions. More negative VGS,OFF can aggravate the dynamic RON degradation under both soft- and hard-switching, especially when switching with a high VDS,OFF. The impacts of VGS,OFF on switching transients and off-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The off-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

In a ${p}$ -channel field-effect-transistor (${p}$ -FET) bridge HEMT device recently realized on a commercial ${p}$ -GaN/AlGaN/GaN-on-Si power HEMT epi-wafer, it is revealed that the device’s reverse-conduction turn-on voltage (${V}_{\text {RT}}$) can be effectively decoupled from the forward threshold voltage (${V}_{\text {TH}}$) of Schottky-type ${p}$ -GaN gate HEMTs. Unlike the conventional Schottky-type ${p}$ -GaN gate HEMTs, of which ${V}_{\text {RT}}$ is closely linked to ${V}_{\text {TH}}$ , the ${p}$ -FET-bridge HEMT enables separate designs of ${V}_{\text {RT}}$ and $V_{\text {TH}}$ so that low-loss reverse conduction and high threshold voltage can be simultaneously realized. In addition, ${V}_{\text {RT}}$ can be further reduced by engineering the AlGaN barrier layer, which will also benefit a lower channel sheet resistance without lowering ${V}_{\text {TH}}$. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a GaN-based $\textit {p-n}$ junction gate (PNJ) HEMT featuring an ${n}$ -GaN/ ${p}$ -GaN/AlGaN/GaN gate stack. Compared to the more conventional ${p}$ -GaN gate HEMT with a Schottky junction between the gate metal and ${p}$ -GaN layer, the $\textit {p-n}$ junction can withstand higher reverse bias at the same peak electric-field as the depletion region extends to both the ${n}$ -side and ${p}$ -side, while exhibiting lower leakage current. The PNJ-HEMT shows a positive threshold voltage (${V}_{\text {TH}}$) of 1.78 V, a small gate leakage $(\sim 10^{-3}$ mA/mm @ ${V}_{\text {GS}} = {10}\,\, \text {V}$). In particular, a large forward gate breakdown voltage of 19.35 V at 25 °C and 19.70 V at 200 °C was achieved with the PNJ-gate HEMT. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

The drain induced dynamic threshold voltage (${V}_{\textrm {th}}$) shift of a ${p}$ -GaN gate HEMT with a Schottky gate contact is investigated, and the underlying mechanisms are explained with a charge storage model. When the device experiences a high drain bias ${V}_{\textrm {DSQ}}$ , the gate-to-drain capacitance (${C}_{\textrm {GD}}$) is charged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$). As the drain voltage drops to ${V}_{\textrm {DSM}}$ where ${V}_{\textrm {th}}$ is measured, ${C}_{\textrm {GD}}$ is expected to be discharged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). However, the metal/ ${p}$ -GaN Schottky junction could block the discharging current, resulting in storage of negative charges in the ${p}$ -GaN layer. For the device to turn on, additional gate voltage is required to counteract the stored negative charges, resulting in a positive shift of ${V}_{\textrm {th}}$. The dynamic ${V}_{\textrm {th}}$ shift is an intrinsic and predictable characteristic of the ${p}$ -GaN gate HEMT which is linearly correlated with $\Delta \!{Q}_{\textrm {GD}}={Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$) $- {Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). The ${V}_{\textrm {th}}$ shift is dependent on ${V}_{\textrm {DSQ}}$ as well as ${V}_{\textrm {DSM}}$ , indicating that the ${V}_{\textrm {th}}$ shift is varying along the load line during a switching operation. [ABSTRACT FROM AUTHOR]

The OFF-state drain leakage characteristics in 600-V p-GaN HEMTs with an ohmic gate contact are investigated under dynamic switching conditions instead of commonly used quasi-static measurement setup. It is found that fast dynamic OFF-state leakage current (dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$) is substantially higher than the slow-ramping quasi-static ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ due to the weaker trapping effect in the buffer layer. With sufficiently large positive ON-state gate bias, further increase in dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ is observed and is attributed to ON-state hole injection that leads to energy band lowering in the buffer. The underlying physical processes are explained by the dynamic behavior of the traps in the buffer layer. This letter indicates that the ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under practical switching operations is much higher than the static measurement results and should be used to evaluate dynamic OFF-state power consumption in the p-GaN HEMTs with an ohmic gate contact. [ABSTRACT FROM AUTHOR]

A low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with V\mathrm {th} of +0.5 V at I\mathrm {DS}= 10 ~\mu \text{A} /mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/( \textV\cdot \texts ). The on-resistance is as small as 6.9 \Omega \cdot \text mm for a DC-MOS-HEMT with LG/L\mathrm {GS}/L\mathrm {GD} = 1.5/2/15~\mu \text{m} , and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. [ABSTRACT FROM AUTHOR]