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Abstract In this study, we demonstrate binary and ternary logic-in-memory (LIM) operations of inverters and NAND and NOR gates comprising nanosheet (NS) feedback field-effect transistors (FBFETs) with a triple-gated structure. The NS FBFETs are reconfigured in p- or n-channel modes depending on the polarity of the gate bias voltage and exhibit steep switching characteristics with an extremely low subthreshold swing of 1.08 mV dec–1 and a high ON/OFF current ratio of approximately 107. Logic circuits consisting of NS FBFETs perform binary and ternary logic operations of the inverters and NAND and NOR gates in each circuit and store their outputs under zero-bias conditions. Therefore, NS FBFETs are promising components for next-generation LIM.

Abstract In this study, a binarized neural network (BNN) of silicon diode arrays achieved vector–matrix multiplication (VMM) between the binarized weights and inputs in these arrays. The diodes that operate in a positive-feedback loop in their p+-n-p-n+ device structure possess steep switching and bistable characteristics with an extremely low subthreshold swing (below 1 mV) and a high current ratio (approximately 108). Moreover, the arrays show a self-rectifying functionality and an outstanding linearity by an R-squared value of 0.99986, which allows to compose a synaptic cell with a single diode. A 2 × 2 diode array can perform matrix multiply-accumulate operations for various binarized weight matrix cases with some input vectors, which is in high concordance with the VMM, owing to the high reliability and uniformity of the diodes. Moreover, the disturbance-free, nondestructive readout, and semi-permanent holding characteristics of the diode arrays support the feasibility of implementing the BNN.

Abstract In‐memory computing significantly reduces workload and energy cost of data access in the traditional von Neumann computing architecture. Using various memristors, stateful logic is developed to realize in‐memory computing. However, memristors have encountered critical issues in terms of device variation and reliability, and therefore, fundamental device solutions are required to realize practical stateful logic. In this study, NAND, NOR, and half‐adder stateful logic operations of gated silicon diodes with a p+–n–p–n+ structure are demonstrated to achieve in‐memory computing. Gated diodes have bistable, steep switching, and quasi‐nonvolatile memory characteristics, enabling reliable stateful logic operation. The uniformity of their device characteristics overcomes the inherent stochastic characteristics of memristors that are widely researched for stateful logic. The sequential multiread logic operation simplifies the complex state logic scheme. In particular, a nondestructive half‐adder operation can be executed in five sequential steps using six parallel diodes. Thus, the stateful logic of gated diodes can be a potential building block for in‐memory computing.

Here, we investigate the effects of interface defects on the electrical characteristics of amorphous indium-tin-gallium-zinc oxide (a-ITGZO) thin-film transistors (TFTs) utilizing bottom, top, and dual gatings. The field-effect mobility (27.3 cm2/V∙s) and subthreshold swing (222 mV/decade) under a dual gating is substantially better than those under top (12.6 cm2/V∙s, 301 mV/decade) and bottom (11.1 cm2/V∙s, 487 mV/decade) gatings. For an a-ITGZO TFT, oxygen deficiencies are more prevalent in the bottom-gate dielectric interface than in the top-gate dielectric interface, and they are less prevalent inside the channel layer than at the interfaces, indicating that the presence of oxygen deficiencies significantly affects the field-effect mobility and subthreshold swing. Moreover, the variation in the electrical characteristics due to the positive bias stress is discussed here.

Abstract In this study, a triple‐gated transistor with a p+‐i‐n+ silicon nanosheet (NS) is proposed as a single synaptic device, and bidirectional synaptic functions are realized using reconfigurable memory characteristics. The triple‐gated NS transistor features steep switching and bistable characteristics with a subthreshold swing below 5 mV dec−1 and an ON/OFF current ratio of ≈5 × 106 for both the n‐ and p‐channel modes. This transistor exhibits electrically symmetric reconfigurable memory characteristics with an ON current ratio of 1.02 for the n‐ and p‐channel modes. Moreover, the bidirectional synaptic weight updates of binarized spike‐timing‐dependent plasticity learning are successfully performed in a single transistor. This study demonstrates the potential of a triple‐gated NS transistor for achieving compact synaptic arrays in large‐scale silicon‐based neuromorphic computing systems.

Abstract A reconfigurable logic‐in‐memory (R‐LIM) cell performs logic‐in‐memory functions as well as reconfigurable logic gates. The R‐LIM cell is constructed with triple‐gated (TG) feedback field‐effect transistors (FBFETs) that are reconfigured in n‐channel or p‐channel modes via electrostatic doping. Each TG FBFET has one control gate electrode and two program‐gate electrodes that determine the channel mode. Their reconfigurability enables the symmetrical operation of the n‐channel and p‐channel modes through an on‐current ratio of 1:04. Furthermore, the R‐LIM cell performs eight Boolean logic operations, storing the logic outputs for ≈100 s under zero‐bias conditions. The R‐LIM cell is useful for developing in‐memory computing systems with high energy efficiency and functional logic.

In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator exhibited uniform probability distributions of 51.6% for logic 0 and 48.4% for logic 1. The generation of analog voltages provides binary random variables that are stored for over 5000 s. This demonstrates the potential of the ring oscillator in advanced physical functions and true random number generator technologies.

In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of −200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from −1.01 V (1.34 V) to −11.01 V (10.45 V) in the n-channel (p-channel) mode. In contrast, with decreasing temperature from 25 °C to −200 °C, the thermally generated charge carriers decrease, causing a shift in the latch-up voltage in the opposite direction to that of the increasing temperature case. Despite the shift in the latch-up voltage, the TG FBFETs exhibit ideal switching characteristics, with subthreshold swings of 6.6 mV/dec and 7.2 mV/dec for the n-channel and p-channel modes, respectively. Moreover, the memory window widens with increasing temperature. Specifically, at temperatures above 85 °C, the memory windows are wider than 3.05 V and 1.42 V for the n-channel and p-channel modes, respectively.

In this study, we examine the effect of interface trap states on the electrical characteristics of single-gated feedback field-effect transistors (FBFETs) using a commercially available computer-aided design simulation package. Interface trap states exist between the channels and the oxide layers, and these trap states act as acceptor-like trap states in regions of higher energy than the intrinsic Fermi energy ( $E_{\mathrm {i}}$ ) and as donor-like trap states in regions of lower energy than $E_{\mathrm {i}}$ in the energy band. The density distribution peaks at $E_{\mathrm {i}}$ + 0.28 eV for the acceptor-like trap states and at $E_{\mathrm {i}}$ – 0.28 eV for the donor-like trap states. The occupation mechanism of these trap states is analyzed by the density of the interface states and trapped charges, the energy band diagram, and the current-voltage curves. In n-channel (p-channel) FBFETs, the latch-up voltage varies by approximately 0.01 V as the acceptor-like (donor-like) trap states increase, whereas the effect of the donor-like (acceptor-like) trap states is negligible. Moreover, the FBFETs exhibit an operating speed of 4 ns and retention time of 900 s during a memory operation, despite the existence of the interface states.

In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, generating the memory state “State 1 (State 0)”. Read pulses of 40 ns read these states with a retention time of 3 s, and the potential barrier formation and carrier accumulation were influenced by these read pulses. The potential barriers were analyzed, using junction voltage and current density to explore the memory states. Moreover, FBFETs exhibited nondestructive readout characteristics during the read operation, which depended on the read voltage and pulse width.

Abstract The reconfigurable feedback field‐effect transistors (R‐FBFETs) with a double‐gated structure are designed and the logic and memory operations of a logic‐in‐memory (LIM) inverter comprising two R‐FBFETs are investigated. The R‐FBFETs exhibit an extremely low subthreshold swing of ≈1 mV dec−1, a high on/off current ratio of ≈107, and a long retention time of 10 s, owing to a positive feedback loop mechanism. The on‐current ratio of the p‐ to n‐channel modes is 1.03, which indicates a high degree of reconfigurability. The LIM inverter retains the output logic “1” and “0” states for over 50 s under zero‐bias conditions. The symmetric reconfigurable switching and memory operations of the R‐FBFETs enable the LIM inverter to perform logic and memory operations for a long retention time without a power supply.

Abstract Among the promising approaches for implementing high-performance computing, reconfigurable logic gates and logic-in-memory (LIM) approaches have been drawing increased research attention. These allow for improved functional scaling of a chip, owing to the improved functionality per unit area. Although numerous studies have been conducted independently for either reconfigurable logic or LIM units, attempts to construct a hybrid structure based on reconfigurable logic and LIM units remain relatively rare. In this study, we merge reconfigurable logic gates and LIM units to achieve a universal logic-in-memory (ULIM) cell for enabling all basic Boolean logic operations and data storage in a single cell. A ULIM cell consisting of silicon memory devices with reconfigurable n- and p-program modes can reconfigure logic operations within the complete set of Boolean logic operations. Moreover, the ULIM cell exhibits memory behaviors for storing output logic values without supply voltages for a certain period, resulting in zero static power consumption. Hence, this study provides a way to realize high-performance electronics by utilizing the silicon devices with a hybrid function of reconfigurable logic and LIM.

Abstract In this study, we propose an inverter consisting of reconfigurable double-gated (DG) feedback field-effect transistors (FBFETs) and examine its logic and memory operations through a mixed-mode technology computer-aided design simulation. The DG FBFETs can be reconfigured to n- or p-channel modes, and these modes exhibit an on/off current ratio of ~ 1012 and a subthreshold swing (SS) of ~ 0.4 mV/dec. Our study suggests the solution to the output voltage loss, a common problem in FBFET-based inverters; the proposed inverter exhibits the same output logic voltage as the supply voltage in gigahertz frequencies by applying a reset operation between the logic operations. The inverter retains the output logic ‘1’ and ‘0’ states for ~ 21 s without the supply voltage. The proposed inverter demonstrates the promising potential for logic-in-memory application.

Abstract In this study, we present a fully complementary metal–oxide–semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a positive feedback loop by carrier accumulation in their channels, which allows to achieve excellent memory characteristics with extremely low subthreshold swings. This hybrid operation of the switching and memory functions enables FBFETs to implement memory operation in a conventional CMOS logic scheme. The inverter comprising p- and n-channel FBFETs in series can be in ternary logic states and retain these states during the hold operation owing to the switching and memory functions of FBFETs. It exhibits a high voltage gain of approximately 73 V/V, logic holding time of 150 s, and reliable endurance of approximately 105. This ternary inverter with memory function demonstrates possibilities for a new computing paradigm in multivalued logic applications.

Abstract In this study, the logic‐in‐memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double‐gated feedback field‐effect transistors. The component transistors reconfigure their operation modes into n‐ or p‐channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on‐current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero‐bias condition. This study demonstrates that the ternary logic gates are promising candidates for next‐generation low‐power computing systems.

Abstract In this study, we perform simulations to demonstrate neural oscillations in a single silicon nanowire neuron device comprising a gated p–n–p–n diode structure with no external bias lines. The neuron device emulates a biological neuron using interlinked positive and negative feedback loops, enabling neural oscillations with a high firing frequency of ~ 8 MHz and a low energy consumption of ~ 4.5 × 10−15 J. The neuron device provides a high integration density and low energy consumption for neuromorphic hardware. The periodic and aperiodic patterns of the neural oscillations depend on the amplitudes of the analog and digital input signals. Furthermore, the device characteristics, energy band diagram, and leaky integrate-and-fire operation of the neuron device are discussed.

Abstract The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowire feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

In this study, the temperature-dependent electrical characteristics of p-channel mode feedback field-effect transistors (FBFETs) were examined at temperatures ranging from 250 to 425 K. Their steep subthreshold swings of less than 1 mV/dec were maintained even at temperatures up to 400 K. As the temperature increased to 400 K, the latch-up voltage shifted from −0.951 to −0.613 V, which was caused by a reduction in the potential barriers in the channels of the FBFETs. High $I_{\mathrm {on}}/I_{\mathrm {off}}$ ratios above 108 were maintained in the temperature range of 250 to 400 K. However, at temperatures over 400 K, the FBFETs were turned on regardless of the gate voltages owing to the generation of a thermally induced positive feedback loop.

Abstract In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

Abstract In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.

Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+–n–p–n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10−15 J/bit for the write ‘1’ operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.

In this study, we examined electrical stability of the p-channel feedback field-effect transistors (FBFETs) under negative bias stress (NBS) and positive bias stress (PBS). The intact FBFETs have a subthreshold swing (SS) of 0.12 mV/dec, an on-current of $\sim 10^{-4}$ A, and a threshold voltage ( $V_{\mathrm {TH}}$ ) of −0.76 V. There is a negligible change in the on-current and SS when the FBFETs are stressed by a gate-bias voltage corresponding to an electric field of 5.4 MV/cm across the gate oxide. On the other hand, as the duration of the stress increases to 1000 s, the $V_{\mathrm {TH}}$ shifts to −0.89 V and −0.67 V for NBS and PBS, respectively. The $V_{\mathrm {TH}}$ was recovered to over 83% at a recovery bias voltage of ±5 V. The electrical stabilities of FBFETs under NBS and PBS are discussed in this study.

In this study, the device characteristics of silicon nanowire feedback field-effect transistors were predicted using technology computer-aided design (TCAD)-augmented machine learning (TCAD-ML). The full current–voltage (I-V) curves in forward and reverse voltage sweeps were predicted well, with high R-squared values of 0.9938 and 0.9953, respectively, by using random forest regression. Moreover, the TCAD-ML model provided high prediction accuracy not only for the full I-V curves but also for the important device features, such as the latch-up and latch-down voltages, saturation drain current, and memory window. Therefore, this study demonstrated that the TCAD-ML model can substantially reduce the computational time for device development compared with conventional simulation methods.

In this study, we investigate the performance of a hybrid energy device (HED) composed of a photovoltaic cell (PVC) and a thermoelectric generator (TEG) through an analysis of the voltage difference (net voltage) between voltage drop and thermoelectric voltage. The efficiency of the HED is compared with that of an isolated PVC at irradiances in the range of 200∼1000 W/m2. At an irradiance of 200 W/m2, the maximum power of the HED is 6.7% higher than that of the isolated PVC because the thermoelectric voltage is greater than the voltage drop in the TEG. Our study reveals that the net voltage between the voltage drop and the thermoelectric voltage determines whether the output power of the HED is higher than that of the isolated PVC. In addition, the relationship between the net voltage and the increase in maximum power of the HED reveals that the net voltage becomes a predictor of the performance of HED.

In this study, we demonstrated the enhancement of the output power of a hybrid energy device (HED) using a cooling patch that does not consume any external electric power. The HED consisted of a photovoltaic cell (PVC) and a thermoelectric generator (TEG); the cooling patch was attached to the TEG. When the PVC was exposed to solar irradiance, the cooling patch lowered the temperature of the PVC and increased the thermal gradient across the TEG, thereby increasing the output power. For an HED with a cooling patch at an irradiance of 1000 W/m2, the output power increased to 24.2 mW, as compared to the output power of 19.9 mW for an HED without any cooling patch.

In this study, we propose an integrate-and-fire (I&F) neuron circuit using a p-n-p-n diode that utilizes a latch-up phenomenon and investigate the I&F operation without external bias voltages using mixed-mode technology computer-aided design (TCAD) simulations. The neuron circuit composed of one p-n-p-n diode, three MOSFETs, and a capacitor operates with no external bias lines, and its I&F operation has an energy consumption of 0.59 fJ with an energy efficiency of 96.3% per spike. The presented neuron circuit is superior in terms of structural simplicity, number of external bias lines, and energy efficiency in comparison with that constructed with only MOSFETs. Moreover, the neuron circuit exhibits the features of controlling the firing frequency through the amplitude and time width of the synaptic pulse despite of the reduced number of the components and no external bias lines.

Abstract The change of electrical performance of amorphous SiZnSnO thin film transistors (a-SZTO TFTs) has been investigated depending on various metal capping layers on the channel layer by causing different contact property. It was confirmed that the change of electrical characteristics was sensitively dependent on the change of the capping layer materials on the same channel layer between the source/drain electrodes. This sensitive change in the electrical characteristics is mainly due to different work function of metal capping layer on the channel layer. The work function of each capping layer material has been analyzed and derived by using Kelvin probe force microscopy and compared with the energy bandgap of the SZTO layer. When the work function of the capping layer is larger than that of the channel layer, electrons are depleted from the channel layer to the capping layer. On the contrary, in the case of using a material having a work function smaller than that of the channel layer, the electrical characteristics were improved because electrons were injected into the channel layer. Based on depletion and injection mechanism caused by different contact barrier between metal capping layer and channel layer, NOT, NAND, and NOR logic circuits have been implemented simply by changing metal capping layer on the channel layer.

In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). The hybrid logic and memory operations of the LIM inverter were investigated by mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.8 (V/V) when transitioning from logic ‘1’ to ‘0’ and 7.9 (V/V) when transitioning from logic ‘0’ to ‘1’, while holding calculated logic at zero input voltage. The energy band diagrams of the n-FBFET structure demonstrated that the holding operation of the inverter was implemented by controlling the positive feedback loop. Moreover, the output logic can remain constant without any supply voltage, resulting in zero static power consumption.

Abstract The switchable‐memory operation of a feedback silicon nanowire transistor with a dual‐gate structure is demonstrated. The single transistor exhibits volatile memory characteristics with a retention time longer than 3600 s, as well as a switching capability with a subthreshold swing lower than 7 mV dec−1. A gate‐controlled memory window forms around a gate voltage of 0 V owing to the positive feedback loop in the channel region, allowing a program/erase endurance of more than 1000 cycles. The memory transistor, with switching capability, opens up the possibility of overcoming not only the scaling limit faced by conventional volatile memory but also the inherent drawback of the separation of the building blocks for memory and logic.

A solution-processable Ag2Se nanoparticle thin film (NPTF) is a prospective thermoelectric material for plastic-based thermoelectric generators, but its low electrical conductivity hinders the fabrication of high performance plastic-based thermoelectric generators. In this study, we design Ag2Se NPTFs embedded with silicon nanowires (SiNWs) to improve their thermoelectric characteristics. The Seebeck coefficients are −233 and −240 µV/K, respectively, for a Ag2Se NPTF alone and a Ag2Se NPTF embedded with SiNWs. For the Ag2Se NPTF embedded with SiNWs, the electrical conductivity is improved from 0.15 to 18.5 S/m with the embedment of SiNWs. The thermal conductivities are determined by a lateral thermal conductivity measurement for nanomaterials and the thermal conductivities are 0.62 and 0.84 W/(m·K) for a Ag2Se NPTF alone and a Ag2Se NPTF embedded with SiNWs, respectively. Due to the significant increase in the electrical conductivity and the insignificant increase in its thermal conductivity, the output power of the Ag2Se NPTF embedded with SiNWs is 120 times greater than that of the Ag2Se NPTF alone. Our results demonstrate that the Ag2Se NPTF embedded with SiNWs is a prospective thermoelectric material for high performance plastic-based thermoelectric generators.

In this study, a laterally coupled device composed of a photodiode and a Si nanowires-field-effect transistor (NWs-FET) is constructed on a plastic substrate and the coupled device is characterized. The photodiode is made of p-type Si NWs and an n-type ZnO film. The Si NWs-FET is connected electrically to the photodiode in order to enhance the latter’s photocurrent efficiency by adjusting the gate voltage of the FET. When the FET is switched on by biasing a gate voltage of −9 V, the photocurrent efficiency of the photodiode is three times higher than that when the FET is switched off by biasing a gate voltage of 0 V.