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In this work, we manifest that the epitaxial structure for p-GaN gate high-electron-mobility transistor is a versatile platform to develop electronics for operating in an extremely wide temperature range (X-WTR) from 2 to 675 K, with comprehensive X-WTR studies on device operation and circuit behaviors. The key enabler for the high-temperature operation is the wide bandgap that substantially suppresses the thermal excitation of the intrinsic carrier. However, for the low-temperature side, the two-dimensional electron and hole gas (2DEG and 2DHG) channels at the heterojunctions are formed by the temperature-insensitive polarization fields, which free the carriers from freezing out. The monolithically integrated GaN n-FET, p-FET, and the resultant complementary circuits are, therefore, shown to operate in X-WTR. [ABSTRACT FROM AUTHOR]

Enhancement-mode (E-mode) p-channel gallium nitride (GaN) field-effect transistors (p-FETs) are essential components for GaN-based complementary logic circuits. For the ease of integration with n-FETs, they could be fabricated on the commercial p-GaN gate high-electron-mobility-transistor (HEMT) platform, on which the two-dimensional electron gas at the AlGaN/GaN hetero-interface is completely depleted in as-grown epi-structures. However, under the gated region where p-GaN is recessed and depleted at thermal equilibrium, a parasitic electron channel (PEC) could appear at the AlGaN/GaN interface. This Letter reports experimental investigations on the PEC with specifically designed structures, confirming that the PEC does exist but imposes limited impacts on electrical characteristics of p-FETs. When connected with an external contact, the PEC could act as a back gate to modulate the overlaying p-channel. If isolated from external contacts, which is the case of p-FETs under normal operations, electrons in the PEC would redistribute under the active region of p-FETs in the horizontal direction (i.e., parallel to the surface) under different biases but are mostly confined near the AlGaN/GaN interface in the vertical direction (i.e., perpendicular to the surface). [ABSTRACT FROM AUTHOR]

We report GaN high-electron-mobility transistors (HEMTs) with a thick (7.7 µm) GaN buffer on a Czochralski low resistivity Si (LRS) substrate. The GaN HEMTs exhibit high performance for both radio-frequency (RF) amplification and power conversion. The thick GaN buffer was grown by means of vacancy engineering, delivering a low dislocation density of ∼1.6 × 108 cm−2, contributing to suppressed RF signal coupling to the lossy Si substrate and a high vertical voltage blocking capability. For RF performance, GaN HEMTs with a 650 nm gate exhibit an fT/fMAX value of 25.1/32.3 GHz and a maximum output power POUT of 2.2 W/mm at 4 GHz with a drain voltage VDS of 20 V, which is comparable with the performance of RF GaN HEMTs on a high-resistivity silicon substrate without the existence of the field plate. For power performance, the vertical breakdown voltage of the wafer is 1160 V, and the three-terminal lateral breakdown voltage is 885 V in a GaN HEMT with a gate-to-drain distance of 8 µm. The thick GaN layer on the LRS substrate scheme thus provides a compelling platform for monolithic integration of high-performance RF devices and high-voltage power devices. [ABSTRACT FROM AUTHOR]

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoHLED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The detrapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance Ron and/or threshold voltage Vth of the HEMT. The results show that the recovery processes of both dynamic Ron and threshold voltage Vth of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs. [ABSTRACT FROM AUTHOR]

We report the interface characterization of Al2O3/AlN/GaN MOS (metal-oxide-semiconductor) structures with an AlN interfacial layer. A thin monocrystal-like interfacial layer (AlN) is formed at the Al2O3/GaN to effectively block oxygen from the GaN surface and prevent the formation of detrimental Ga-O bonds. The suppression of Ga-O bonds is validated by X-ray photoelectron spectroscopy of the critical interface. Frequency-dispersion in C-V characteristics has been significantly reduced, owing to improved interface quality. Furthermore, using the conventional conductance method suitable for extracting the interface trap density Dit in MOS structures, Dit in the device with AlN was determined to be in the range of 1011-1012eV-1cm-2, showing one order of magnitude lower than that without AlN. Border traps near the gate-dielectric/GaN interface were identified and shown to be suppressed by the AlN interfacial layer as well. [ABSTRACT FROM AUTHOR]

High quality Al2O3 film grown by atomic layer deposition (ALD), with ozone (O3) as oxygen source, is demonstrated for fabrication of normally-off AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Significant suppression of Al-O-H and Al-Al bonds in ALD-Al2O3 has been realized by substituting conventional H2O source with O3. A high dielectric breakdown E-field of 8.5 MV/cm and good TDDB behavior are achieved in a gate dielectric stack consisting of 13-nm O3-Al2O3 and 2-nm H2O-Al2O3 interfacial layer on recessed GaN. By using this 15-nm gate dielectric and a high-temperature gate-recess technique, the density of positive bulk/interface charges in normally-off AlGaN/GaN MIS-HEMTs is remarkably suppressed to as low as 0.9 x 1012cm-2, contributing to the realization of normally-off operation with a high threshold voltage of +1.6 V and a low specific ON-resistance RON,sp of 0.49 mΩ cm². [ABSTRACT FROM AUTHOR]

In this work, we attempt to reveal the underlying mechanisms of divergent V TH-thermal-stabilities in III-nitride metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) and MOS-Channel-HEMT (MOSC-HEMT). In marked contrast to MOSC-HEMT featuring temperature-independent VTH, MIS-HEMT with the same high-quality gate-dielectric/III-nitride interface and similar interface trap distribution exhibits manifest thermally induced VTH shift. The temperature-dependent VTH of MIS-HEMT is attributed to the polarized III-nitride barrier layer, which spatially separates the critical gate-dielectric/III-nitride interface from the channel and allows "deeper" interface trap levels emerging above the Fermi level at pinch-off. This model is further experimentally validated by distinct VG-driven Fermi level movements at the critical interfaces in MIS-HEMT and MOSC-HEMT. The mechanisms of polarized III-nitride barrier layer in influencing VTH-thermal-stability provide guidelines for the optimization of insulated-gate III-nitride power switching devices. [ABSTRACT FROM AUTHOR]