Search

• Multi-energy level agnostic approach describes defects generation during time-dependent dielectric breakdown. • Defect generation is both fluence and energy-carrier-driven. • Considering the bond strength distribution, the accepted power-law trend for defect generation is naturally obtained by Monte Carlo simulations. • Low-frequency AC time to-breakdown increased compared to DC. A multi-energy level agnostic model is used to examine defect generation during time-dependent dielectric breakdown stress. When considering distributed bond strengths, Monte Carlo simulations show that the distinctive power-law increase of the generated defects with stress time is attained. The rate is strongly influenced by the width of the distribution. The time to breakdown in DC and AC unipolar simulations is proportional to the fluence and energy of the injected carriers. These findings are in line with thin oxide breakdown measurements, which demonstrate a fluence and energy-driven process. [ABSTRACT FROM AUTHOR]

• Multi-energy level agnostic approach describes defects generation during time-dependent dielectric breakdown. • Defect generation is both fluence and energy-carrier-driven. • Considering the bond strength distribution, the accepted power-law trend for defect generation is naturally obtained by Monte Carlo simulations. • Low-frequency AC time to-breakdown increased compared to DC. Defect generation during time-dependent dielectric breakdown stress is investigated by a multi-energy level agnostic model. Monte Carlo simulations show that the characteristic power-law increase of the generated defects with stress time is readily obtained when considering distributed bond strengths. DC and AC unipolar simulations show the proportionality between the time-to-breakdown and the fluence and energy of the injected carriers. These results are consistent with the experimental observations of a fluence and energy-driven process in thin oxides. [ABSTRACT FROM AUTHOR]

Dielectric defects play a crucial role in the reliability of MOSFETs. In this study, we aim to gain a deeper understanding of dielectrics' degradation by correlating the effective interface (N 2 D) and bulk (N B T) trap densities extracted by different characterization techniques (I-V, charge pumping, and 1/f noise) under different electrical stress conditions. Additionally, we establish an empirical relation between the increase of N B T (estimated via 1/f noise measurements) and N 2 D , e f f (estimated through the monitoring of threshold voltage shift) after stress. This relation is useful to calculate the expected increase in 1/f noise from the V T degradation models typically made available by the foundries to circuit designers. • Comparison of electrical techniques to extract trap densities under diverse stress conditions. • 1/f noise increases with stress only in the carrier number fluctuation regime (i.e., at low gate voltage overdrives). • We derive an empirical relationship between the stress-induced increase of 1/f noise and threshold voltage shift. [ABSTRACT FROM AUTHOR]

Charge trapping plays an important role for the reliability of electronic devices and manifests itself in various phenomena like bias temperature instability (BTI), random telegraph noise (RTN), hysteresis or trap-assisted tunneling (TAT). In this work we present Comphy v3.0 , an open source physical framework for modeling these effects in a unified fashion using nonradiative multiphonon theory on a one-dimensional device geometry. Here we give an overview about the underlying theory, discuss newly introduced features compared to the original Comphy framework and also review recent advances in reliability physics enabled by these new features. The usefulness of Comphy v3.0 for the reliability community is highlighted by several practical examples including automatic extraction of defect distributions, modeling of TAT in high- κ capacitors and BTI/RTN modeling at cryogenic temperatures. • User-friendly Python package providing a compact model for device reliability. • Automatic defect parameter extraction and reliability model creation from measure-stress-measure experiments. • Unified framework for modeling bias temperature instability, random telegraph noise and trap-assisted tunneling. • Quantum mechanical models to consider nuclear tunneling relevant for charge trapping at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

Abstract: Identifying the trap configuration is essential for understanding non-volatile memory device performance and reliability. In this paper, an accurate approach to determine the trap distribution in the charged layer is presented. The analysis is done by Trap Spectroscopy by Charge Injection and Sensing (TSCIS) technique varying charge injection time and gate voltage independently. Varying time determines the physical charge injection distance. The conversion of time into distance is done based on theoretical modeling simplified to only electron capturing from Shockley–Read–Hall (SRH) statistics. Direct tunneling of the electrons from quantized energy levels in inverted Si channels to the oxide traps is considered with a WKB approximation. This approach gives the electron scanning rate in SiO2 as 0.19nm/decade, which is consistent with previous noise/direct tunneling analyses. The effect of the residual charge on the potential energy barrier for the electron tunneling is also accounted for in the electron scanning distance calculation by including Gauss’ law. Considering the charge voltage determines the trap energy level, and we can finally obtain the trap distribution ‘map’ inside the oxide. This TSCIS technique is applied to profile the oxide trap density in oxide stacks for flash memory application successfully. Traps located spatially as far as 3nm from the Si/SiO2 interface can be probed with 1000s of charge injection time in case of a 0.87nm SiO2/10nm Al2O3 stack. [ABSTRACT FROM AUTHOR]

Abstract: The post-breakdown conduction properties of ultrathin SiON layers were investigated, to determine the impact of various parameters on the growth of a breakdown path after its formation. Post-breakdown conduction is seen to be dependent on stress voltage used to break the oxide, the stress temperature, and the time-to-breakdown. With this knowledge, the performance of transistors of various channel lengths and widths was studied both before and after breakdown occurred to determine whether the devices still function as a digital switches after breakdown. That is, the drain to source current (I ds) in the on–state (V g ≫ V th) is much larger than I ds in the off–state (V g < V th), allowing the device to continue to function as a switch, after breakdown occurs. [Copyright &y& Elsevier]

Gate-stack reliability has been a major roadblock in the realization of InGaAs-channel based logic technology. Excessive charge trapping in the gate-oxide causes time-dependent drift in transistor threshold voltage (V th). The extent to which V th drifts under certain stress conditions depends on (i) the defect ground-state energy distributions in the oxide bandgap, and (ii) the specific activation energy distributions for charge capture/emission process. In this work, semi-empirical modelling of ground-state defect energy distributions is revisited to determine the Total Operating Voltage Range of InGaAs-based MOSFETs for a DC-BTI lifetime of 10 years under DC operating conditions. Non-radiative Multiphonon (NMP) theory is subsequently used to describe the microscopic physics of charge (de-)trapping kinetics in terms of activation energy barriers for charge capture (E Ac) and emission (E Ae) into/from gate-stack defects. These activation energy barriers are visualized using Capture/Emission Time (CET) maps, which are efficient and powerful tools to predict the BTI degradation under different AC operating conditions as well. We demonstrate that the enhanced BTI reliability of a gate-stack with a novel ASM interfacial layer (ASM-IL), as compared to the bilayer gate-stack of Al 2 O 3 /HfO 2 , results from the favorable reconfiguration of the defect energy distribution in the oxide bandgap, as well as their activation energies for capture and emission process. • Reviews the modelling of ground-state defect energy distributions in the bandgap of high-k based gate-stacks. • Provides the physical insight into improved reliability performance of the gate-stack (1nmASM-IL/1nmLaSiOx/3nmHfO 2). • Uses CET map methodology to provide these insights, by invoking the atomistic defect model based on NMP theory. • Provides a direct comparison of the (de-)trapping kinetics of defects in the ASM-IL gate-stack using calibrated CET maps. • Validates the AC-BTI results for the Al 2 O 3 gate-stack. [ABSTRACT FROM AUTHOR]

In nMOS transistors the impact of positive bias temperature instability (PBTI) on the device performance is typically considered negligible and has thus been barely studied in the past. However, an accurate description of this phenomena requires and in depth understanding of the physical origin being responsible for the change of the device characteristics over time. For the assessment of PBTI in nanoscale SiON nMOS transistors we make use of the time-dependent defect spectroscopy (TDDS) and examine the device performance degradation at the single-defect level. Contrary to what is visible in large-area devices, our investigations clearly reveal that charge trapping at both electron and hole traps contributes to the overall drift of the threshold voltage in these devices. Furthermore we observe that hole traps account for around 20% of the total threshold voltage drift. To evaluate the impact of single-defects on the device performance we characterize the charge trapping kinetics of a number of defects, which can be explained by employing a two-state defect model. In our approach we observe charge trapping due to defect/channel interaction for electron traps and defect/gate interaction for hole traps. The extracted trap levels and trap depths clearly reveal that the electrically active electron traps reside closer to the SiON/Si interface while the hole traps are located closer to the poly-Si/SiON interface. Finally, the extracted trap parameters are fully consistent with defect candidates for electron and hole trapping from DFT calculations. [ABSTRACT FROM AUTHOR]

Abstract: The reliability of 0.69nm EOT GdHfO dielectric with metal gate is investigated. The threshold voltage shift at identical PBTI stress conditions is only 20% of the shift of a 0.78nm EOT HfO2 +La2O3 (or HfLaO) device. The resulting reliable gate over-drive at 10years of this GdHfO device is 0.85V. Analysis of the stress induced leakage current (SILC) shows that the improved PBTI in the GdHfO device is related to the reduced trap generation under low bias stress, which already exists in the HfLaO device. [Copyright &y& Elsevier]