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This paper presents a methodology for designing balanced VLIW architectures. Since we are interested in the architectural aspects of those processors we have developed a framework to evaluate the relationship among the main components of a VLIW machine. Our framework includes the simulator of an actual processor, software tools both to detect the instruction level parallelism of application programs and to generate the parallel object code for each specific machine configuration derived from our basic model of VLIW architecture, and an interpreter which reproduces the behavior of each member of the VLIW family. By interpreting the optimized code derived from a suite of benchmark programs, we have determined the best VLIW configuration for each test program. From these experiments we have discovered which relationship among the machine components should be observed during the specification of a VLIW machine in order to obtain a balanced processor.

This paper presents a study of the impact of conditional branch instructions on the performance of Superscalar processors. By interpreting non-optimised code of a real processor on various configurations derived from a Superscalar architecture model, we have evaluated the execution time percentages in which the associative dispatch algorithm remains idle, waiting for the completion of conditional branch instructions. In addition, we have assessed the volume of instruction level parallelism that can be extracted from application programs if the target machine is equipped with an omniscient branch predictor.

The development of a recent technological product, referred to as Array of Configurable Logic Cells, promotes many opportunities for research and implementation of digital circuits. These arrays include logic cells whose functions can be dynamically specified by the user. The paper describes the main characteristics of configurable cells, and indicates the potential use of these arrays for research and teaching. The paper also shows our experiments in this area, including the design of an alternative array of configurable cells.

The development of Computer Architectures capable of executing several different instructions per clock cycle is a recent trend in processor design. These machines are called Super-Scalar architectures, and they represent an important member of parallel processors: machines incorporating several independent functional devices that can be programmed to operate in parallel. The main problem regarding this class of architectures is how the machine code should be generated in order to exploit their potential parallelism. This work describes some experiments leading to the generation of parallel code for Super-Scalar machines. The experiments have been carried out with traditional concurrency extraction techniques that have been modified in order to satisfy the requirements of some target machines with low level concurrency. The paper outlines the main details of the project, and shows that speed-up ratios ranging from 1.91 up to 2.91 have been obtained by some versions of our algorithm.

Conventional processor can be characterized by the sequential nature in which machine instructions are dispatched: only one instruction is issued each time, and the next one will be started after the conclusion of the current one. However, the machine performance can be significantly improved if the hardware is able to issue several instructions to be executed simultaneously. In this work we describe some experiments that have been carried out to assess the effect of alternative instruction dispatching algorithms on the overall performance of machines comprising several independent functional units. The paper presents the main aspects of the project, and shows that reduction ratios up to 78% in the processing time required by some benchmark programs can be obtained by issuing multiple instructions.

This paper deals with the subject of placing a set of μ-instructions into the control store in such a way that each μ-instruction can reach its successors. A survey of classical techniques for the generation of the address of the next μ-instruction which are employed by existing μ-architectures, together with the restrictions imposed by their designs and implementations, is presented. Next, we formally describe the placement problem, presenting an algorithm that has been developed to place the μ-instructions into the control memory. The algorithm takes into account the capabilities of the hardware mechanism responsible for the generation of the address of the next μ-instruction. Finally, we present the use of the algorithm in performing the placement of a typical μ-program of an existing μ-machine.

This paper presents the specification and implementation of a kernel supporting an environment oriented towards the development and execution of parallel programs written in PASCAL. The host machine is a multiprocessor system with a common bus interconnecting the processing boards, the global memory segment, I/O boards, and other system modules. The processing board structure of the host is similar to the IBM-PC mother board. The environment is based on the TURBO PASCAL which was extended with constructs providing facilities to express and synchronise the parallel execution of processes. The paper describes the main issues regarding the specification and implementation of the kernel, and outlines the use of the environment in the development of parallel programs.

This paper describes the design and implementation of a virtual machine oriented towards the execution of concurrent programs written in the high level language EDISON defined by P. Brinch Hansen in [1] and [2]. The target machine specification includes primitives reflecting typical constructs of source programs. For instance, there are primitives realizing directly those source operations involving array type and set type variables; instructions to create, synchronize, and to kill processes etc. As required by the source language, the virtual machine implements the concept of Conditional Critical Regions [3]. EDISON programs are translated to target code before their actual interpretation. Some virtual machine interpreters were implemented: first we developed two interpreters in high level language; next an interpreter in ASSEMBLY language; and finally we implemented a μ-programmed version of the virtual machine. Some performance figures of the interpretation are included in the appendix.

In an earlier work we have introduced an Architecture Description Language (ADL for short) and its support system implemented in a machine-independent fashion [5]. This system provides facilities for teaching and research in computer architecture: target machines described in ADL are fed into the support system, and the corresponding interpreter programs are automatically generated. These programs reproduced the run-time environment of the target, as specified by the ADL description, including the interpretation of the target code. This paper presents a brief review of the language and the implementation of its support system. Next, the new constructs that have been incorporated into ADL to give an extended version (ADL-X) are described. Through these mechanisms, designers can specify and synchronize target machine activities occuring in parallel. Finally, we show how the new support system is being implemented, and give a description of a pipeline machine, using the new language features.

This paper presents the specification and implementation of a kernel supporting an environment oriented towards the development and execution of concurrent programs written in an extension of PASCAL. The environment is based on the TURBO PASCAL which was extended with constructs providing mechanisms to express and synchronize the concurrent execution of processes. In addition to the specification and implementation details of the kernel, the paper also outlines the use of the environment in the development of parallel programs, and describes the current stage of the work which should lead to the migration of the environment to a parallel host machine.

The specification and implementation of a machine oriented to the execution of programs written in applicative languages is presented. Source programs are translated into a intermediate form which is interpreted by the target architecture: a normal graph reduction machine based on combinators. Some interpreters for this reduction machine were implemented. In this way, we developed interpreters in the C language, in ASSEMBLY language, and finally a microprogrammed version of the target architecture. The paper shows the relevant aspects of the reduction machine design and the current stage of the project.

This paper describes the design and realization of MPH, a Hybrid Parallel Machine, which is intended to be used as a tool for research in parallel computing. MPH is a multiprocessor system whose processors are arranged according to a hypercubic topology but with interprocessor communication being realized through memory segments which are shared by each pair of processors. The resulting machine incorporates the characteristics of both loosely and tightly coupled architectures, hence its hybrid nature. In addition to the design and implementation issues, the paper also describes the research potential of MPH, and the current stage of the work.