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Phase transition materials are promising for realization of switchable optics. In this work, we show reflectance resonances in the near-infrared and long-wave infrared wavelengths in highly subwavelength partially oxidized Vanadium thin films. These partially oxidized films consist of a multilayer of Vanadium dioxide and Vanadium as shown using Raman spectroscopy and four-probe measurements. As Vanadium dioxide is a phase transition material that shows insulator to metal phase transition at 68 C, the observed infra-red resonances can be switched with temperature into a high-reflectance state. The wavelength of these resonances are passively tunable as a function of the oxidation duration. The obtained reflectance resonance at near-infrared wavelength red shifts from 1.78 um to 2.68 um with increasing oxidation duration while the long-wavelength infrared resonance blue shifts from 12.68 um to 9.96 um. To find the origin of the reflectance resonances, we model the reflectance spectra as a function of the oxidation duration using the transfer matrix method. The presented model captures the dual reflectance resonances reasonably well. These passive wavelength-tunable and switchable resonances with easy to fabricate lithography-free multilayer structure will be useful for multispectral applications such as camouflage, spectral selective microbolometer, and thermal management., Comment: 10 pages, 3 figures

The impact of negative capacitance (NC) of the ferroelectric materials in controlling the direct source to drain tunneling (DSDT) in ultra-short channel FETs is presented in this paper. Besides, an analytical model is developed by solving 2-D Poisson’s equation incorporating the degeneracy of source/drain (S/D) regions. We demonstrate that in NC gate stack based Si channel FETs (NC-FETs), the scaling limit can be pushed down to 7 nm gate length, without using effective mass engineering and alternate channel materials. However, under severe subthreshold tunneling circumstances, we find that as the % content of tunneling current rises above the value of 50% in the net current, the subthreshold slope (SS) ceases to improve with the higher ferroelectric thickness. The rigorous analysis of DSDT-Negative drain induced barrier lowering (NDIBL) and impact of the S/D doping over DSDT is also incorporated in the paper. It is found that DSDT decreases drastically in the NCFET compared to baseline FETs due to the NC effect. Hence, using NC effect, transistor can be scaled down to 7 nm physical gate length with SS 80 mV/dec and I OFF 70 nA / μ m compared to 173 mV/dec and 1.5 × 10 6 nA / μ m, respectively for the baseline FET at the same gate length.

β-Ga2O3 has drawn significant attention for power electronics and deep ultraviolet (UV) photodetector applications owing to its wide bandgap of ~4.4–4.9 eV and high electric breakdown strength of ~7–8 MV/cm. Growth of β-Ga2O3 epitaxial thin films with high growth rate has been recently reported using low pressure chemical vapor deposition (LPCVD) technique. In this work, we have investigated the effect of growth temperature on β-Ga2O3 films grown on c-plane sapphire substrates using LPCVD. We performed growths by varying temperatures from 800 °C to 950 °C while keeping all other growth parameters (Ar/O2 gas flow rates, growth pressure, and Gallium precursor to substrate distance) constant. Optical, structural, and surface characterizations are performed to determine the thickness, bandgap, phase purity, crystal orientation, and crystalline quality of the grown thin films. Amorphous islands of Ga2O3 are observed at growth temperature of 800 °C while continuous and crystalline (−201) oriented β-Ga2O3 thin films are achieved for growth temperatures of 850–950 °C. Crystallinity of the films is found to improve with increase in growth temperature with a minimum rocking full width at half maximum of 1.52o in sample grown at 925 °C. For all the samples grown at and above 875 °C, transmittance measurements revealed an optical bandgap of ~4.77–4.80 eV with high growth rate of ~6 µm/h.

In this paper, we study the multi-domain switching dynamics for a metal–ferroelectric–insulator–semiconductor (MFIS) type negative capacitance Fin Field Effect Transistor (NC-FinFET) for a 10 nm technology node. To study its characteristics, we develop a SPICE model for multi-domain NC-FinFET. Our proposed model is based on Feynman’s pedagogical model of microscopic origin of ferroelectricity. We develop this model using the positive feedback mechanism for dipole–dipole interactions in the ferroelectric material in conjugation with the BSIM-CMG model for the underneath FinFETs. This study reveals that the drain current achieved in a multi-domain case is lower than the mono-domain case. The negative differential resistance (NDR) effect in transistor characteristics is more pronounced in multi-domain NC-FinFET compared to the mono-domain case. Increasing variation in individual domain parameters of the ferroelectric material i.e., coercive voltage ( V C ) and remnant polarization ( P R ), further lowers the drain current with a hysteresis in the drain current characteristics in the multi-domain NC-FinFET.

Halo implanted MOSFETs exhibit anomalous behavior in drain current power spectral density ( S ID ) of flicker noise (1/f) with the variation in drain voltage, but this behavior cannot be captured by existing 1/f models. To identify the reasons for this abnormal behavior of 1/f noise, we have performed experimentally calibrated technology computer-aided design (TCAD) simulations. We find that this anomalous behavior comes from the drain-side halo region, and it has complex dependence on the bias and geometry. We propose a sub-circuit model for 1 / f noise that successfully captures the anomalous behavior of S ID with the drain bias. This model calculates the individual contributions and the impact of different device regions, such as the source side halo, channel, and drain side halo, on the overall noise of the device. The proposed model is in good agreement with the experimentally calibrated TCAD simulations for different geometries, biases, and temperatures. The proposed model is also validated with the measurement data.

BSIM-CMG can fit low frequency noise spectrum in the linear region of operation, but deviates in the saturation region of operation, because the noise model used in BSIM-CMG (and also in other MOSFET models) does not include the impact of velocity saturation. In this work, we formulate a unified noise model including the velocity saturation effect and show that the new model accurately captures the experimental data. Additionally, the developed model can be easily implemented in a circuit simulator, with slight modification in the present low frequency noise model. Although this model is developed for BSIM-CMG, it is a generic model and can be used in any industry-standard model like BSIM-BULK, BSIM-IMG, etc. This model is validated with experimental data of 14 nm FinFET technology.

We present a surface potential based analytical model for double gate tunnel field effect transistor (DGTFET) for the current, terminal charges, and terminal capacitances. The model accounts for the effect of the mobile charge in the channel and captures the device physics in depletion as well as in the strong inversion regime. The narrowing of the tunnel barrier in the presence of mobile charges in the channel is incorporated via modeling of the inverse decay length, which is constant under channel depletion condition and bias dependent under inversion condition. To capture the ambipolar current behavior in the model, tunneling at the drain junction is also included. The proposed model is validated against TCAD simulation data and it shows close match with the simulation data.

The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors. Graphical abstractThe channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. We also validate the radio-frequency (RF) model with measured high frequency data. The proposed model is implemented in the independent multigate model (BSIM-IMG) for FDSOI transistors.Display Omitted HighlightsGeometrical scaling of thermal resistance in FDSOI transistor has been analyzed.A new behavioral model for thermal resistance scaling has been proposed.The model is validated against experimental and Technology Computer Aided Design (TCAD) data.The BSIM-IMG model is validated on the measured RF characteristics for wide bias and frequency ranges.

A novel method for associative processing, using negative capacitance FDSOI (NC-FDSOI) transistors, is presented in this work. Distance computing cell (DCC), that is the basic building block of the associative processing system, is designed using only five transistors. For processing an input pattern, this NC-FDSOI DCC based associative processing system requires fewer transistors and consumes 150 to 500 times lower energy, in comparison with the conventional CMOS Boolean system. The functionality of the DCC is achieved in this small five transistor circuit because of the sharp switching of the ferroelectric polarization.

In this paper, flicker noise behavior of lateral non-uniformly doped MOSFET is studied using impedance field method. Our study shows that Klaassen Prins (KP) method, which forms the basis of noise model in MOSFETs, underestimates flicker noise in such devices. The same KP method overestimates thermal noise by 2–3 orders of magnitude in similar devices as demonstrated in Roy et al. (2007). This apparent discrepancy between thermal and flicker noise behavior lies in origin of these noises, which leads to opposite trend of local noise power spectral density vs doping. We have modeled the physics behind such behavior, which also explain the trends observed in the measurements (Agarwal et al., 2015).

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C–V and I–V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.

We investigate magnetism and band structure engineering in Moire superlattice of blue phosphorus ( β -P) and grey arsenene ( β -As) bilayers, using ab initio calculations. The electronic states near the valence and conduction band edges have significant p z character in both the bilayers. Thus, twisting the layers significantly reduce the interlayer orbital overlap, leading to a decrease in the binding energy (up to ∼ 33 % ) and an increase in interlayer distance (up to ∼ 10 % ), compared to the most stable AA-stacking. This interlayer decoupling also results in a notable increase (up to ∼ 25–50%) of the bandgap of twisted bilayers, with the valance band edge becoming relatively flat with van-Hove singularities in the density of states. Thus, hole doping induces a Stoner instability, leading to ferromagnetic ground state, which is more robust in Moire superlattices, than that of AA-stacked β -P and β -As.

This paper proposes, the investigation of the Suspended Gate Field-Effect Transistor (SG-FET) small-slope switch based on a hybrid numerical simulation approach combining ANSYSTM Multiphysics and ISE-DESSISTM in a self-consistent system. The proposed numerical simulations uniquely enable the investigation of the behavior and the physics of complex micro-electro-mechanical/solid-state devices, such as the SG-FET. Abrupt switching as well as the effect of trapped charges in the gate dielectric are demonstrated. The numerical data serve to calibrate an analytical EKV-based SG-FET model, which is then used to design and originally simulate a sub-micron (90 nm) scaled SG-FET complementary inverter. It is shown that, due to abrupt switching in the subthreshold region and electro-mechanical hysteresis, the SG-FET inverter could deliver a significant power saving (1-2 decades reduction of inverter peak current and practically no leakage power) compared to traditional CMOS inverter.