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This paper presents a new approach for compact modeling of aging and radiation effects for MOS transistors including process variation and environmental influences. This approach can be used in common design flows for analog integrated circuits. Moreover, the aging behavior of whole circuits can be analyzed without the need for abstractions or extrapolation. Only one common physically motivated transistor parameter is used in order to model radiation and degradation mechanisms. [ABSTRACT FROM AUTHOR]

This paper presents a unique methodology to calculate the filtering capacitances of the OpAmp already reported in the literature. The methodology aims to show that there is an optimal solution that can be used to increase the electromagnetic interference (EMI) immunity of any OpAmp for a wide range of frequencies. By using this proposed methodology, an OpAmp structure that reduces the EMI effect is designed in standard 0.18\ \mu \textm mixed-mode CMOS technology. Detailed mathematical analyses and simulation results are presented and discussed. Simulation results show that the maximum EMI-induced offset voltage in the frequency range from 1 MHz to 1 GHz for the OpAmp is 4.4 mV. In contrast, the standard Miller OpAmp exhibits a maximum EMI-induced offset voltage of 92.4 mV under the same operating conditions. [ABSTRACT FROM PUBLISHER]

This paper presents a high-voltage emission driver chiplet for inorganic micro-pixelated light-emitting-diode ($\mu $ LED) displays in a standard 0.18- $\mu \text{m}$ CMOS technology. Different from the conventional driving scheme of the active-matrix organic light-emitting-diode display, which places the scan drivers and emission drivers at the panel bezels, the CMOS driver chiplets are proposed to sit on the glass substrate among $\mu $ LEDs. The high-voltage swing buffers in the CMOS chiplet are used to drive the low-temperature poly-silicon thin-film transistors on glass backplane to enable the emission control of 300 $\mu $ LEDs. A single CMOS chiplet has 20 output channels, each offering 16M-color depth with 256 grey levels realized by an 8-bit digital-to-analog converter. The maximum channel current is 247 $\mu \text{A}$ and the TFT-gate-driving voltage is 15 V. [ABSTRACT FROM AUTHOR]

This paper investigates the fin-width ($\text{W}_{\textsf {Fin}}$) sensitivity of threshold voltage ($\text{V}_{\textsf {T}}$) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ for NC-FinFETs. Our study may provide insights for future scaling of FinFETs. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays. [ABSTRACT FROM AUTHOR]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

Based on time-variant behavior of metal-oxide–semiconductor field-effect transistors in large-signal operations, harmonic translations and their mutual effects are analyzed. Large amplitudes at terminal voltages of these transistors push them into different regions of operation. In this paper, harmonic translations are derived as a result of such changes in operation region of transistors. Operation in triode region for a portion of oscillation cycle results in iterative harmonic translations between fundamental frequency and second harmonic. They boost each other constructively for significantly stronger oscillation, more second harmonic output power, and enhanced dc-to-RF efficiency. Based on this analysis, a 215-GHz signal source, implemented in a TSMC 65-nm CMOS LP is presented. The proposed oscillator achieves a maximum output power of 5.6 dBm and a dc-to-RF efficiency of 4.6%. The measured phase noise is −94.6 dBc/Hz at 1-MHz offset. The proposed oscillator occupies only 0.08 mm2 of chip area. [ABSTRACT FROM PUBLISHER]

This paper presents a tunable active bandpass filter (BPF) with adjustable transmission zeros (TZs) close to the passband for software-defined radio (SDR) applications. The RF front-end frequency selectivity is enhanced by the creation of TZs that also improve the out-of-band (OOB) input-referred third-order intercept point (IIP3). The filter is based on two-path signal cancellation and consists of a tunable BPF in parallel with two tunable bandstop filters. This combination ensures the correct amplitude and phase relationships across a wide tuning range to create adjustable TZs without sacrificing the gain of the passband. This paper presents in detail the design considerations and guidelines, as well as analysis of the filter performance in the presence of nonidealities such as parasitics and imperfect clock signal shape. The proposed filter is implemented with high- $Q~N$ -path filter blocks in a 65-nm CMOS process. The passband of the filter is tunable from 0.1 to 1.4 GHz with a 3-dB bandwidth of 9.8–10.2 MHz, a gain of 21.5–24 dB, a noise figure of 3–4.2 dB, and a total power consumption of 50–73 mW. TZs are created on both sides of the passband with a minimal offset of 25 MHz and are tunable across a 20-MHz range with up to a 60-dB rejection. The measured blocker 1-dB compression point is 8 dBm and the OOB IIP3 is 23 dBm. The reported filter provides a promising on-chip filtering solution for multistandard multifrequency SDR applications with improved interference mitigation capabilities. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to present the main results of an electrostatic discharge (ESD) protection for advanced CMOS technology with electromagnetic (EM) field effect and Lorentz Force (LF) contributions during fast transient and high-current surge. To address this goal, the first step is building a tool to simulate fast transient conditions with all participating physical mechanisms included. The relevant equations describing these mechanisms are: 1) the charge transport equations and 2) the Maxwell equations to describe the EM fields. The LF is also included using an extended formulation of the current-continuity equations. An integrated approach is followed to simulate the full structure (metal connections $+$ silicon device) during the ESD surge and to compare the results between ElectroMagnetic Lorentz Force simulations and transmission line pulse measurements. Obviously, in general, this paper and tool can be used to address electromagnetic compatibility topics and more. [ABSTRACT FROM AUTHOR]

Integrated antennas have become the attractive solution as the electromagnetic (EM) interface for mm-Wave and terahertz ICs. However, on-chip antennas lying at the interface between two different dielectrics (such as air and substrate) can channel most of its power into multiple nonradiative surface-wave modes, reducing efficiency drastically. In this paper, we consider the following problem: given a dielectric substrate, what is the theoretical optimal 2-D surface-current configuration that collectively suppresses surface waves and maximizes radiation efficiency with the desirable radiation pattern? This paper also discusses demonstrative examples of a circuit-EM codesign approach to realize the approximation of such current configurations. Measurement results of radiating arrays in CMOS at mm-Wave frequencies (250–300 GHz) are presented and compared with theoretical predictions. [ABSTRACT FROM PUBLISHER]

In this paper, a new circuit model is proposed to simulate plasma-induced damage (PID). It includes the two sheaths of the plasma, the blocking capacitor, and the RF power source coupled with the victim device. As a result, this model accounts for both the ac behavior of the plasma and the local voltage imbalance induced by differences in shading factors. The advantage of this approach, compared with the previous works, is that it can yield the waveform impinged by the plasma on the transistor gate, which is known to influence the amount of reliability degradation experienced by the device. Finally, this model is also utilized to elucidate the impact of a parasitic capacitance connected to the transistor gate on the extent of the PID inflicted on the victim device. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of efficient and wideband stacked distributed power amplifiers (SDPAs) in 0.13- \mu \textm CMOS technology. To obtain high output swing along with reasonable gain, a four-transistor stack is utilized. Voltage alignment at the drain of each device in the stack is obtained by allowing a small ac swing at the gate due to voltage division between the gate-source capacitance, C\mathrm{ gs} , and the external gate capacitance. Interstage matching is performed by peaking inductors. Further, the four-transistor stack has been replicated in four sections in a distributed topology to obtain wideband operation. A uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines. Based on the said approach, two topologies, the SDPA and the stacked-cascode distributed power amplifier (SCDPA), are designed, implemented, and compared in terms of their performance. For SDPA, measured results show at least 10±0.3 dB of small-signal gain from 2 to 16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with a peak efficiency of 17% and an OIP3 of 22 dBm. The SCDPA shows a measured small-signal gain of more than 10 dB at low frequencies and drops to 10 dB at 10 GHz. Also, the SCDPA demonstrates a saturated output power of 19.8 dBm with a peak efficiency of 19% and an OIP3 of 23 dBm. Both power amplifiers occupy an area of 0.83mm2. [ABSTRACT FROM PUBLISHER]

In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and $5\times $ improvement in the electrostatic discharge robustness are reported experimentally. [ABSTRACT FROM PUBLISHER]

In this paper, for the first time, we study the impact of self-heating on the statistical variability of bulk and Silicon-on-insulator FinFETs designed to meet the requirements of the 14/16-nm technology node. The simulations are performed using the Gold Standard Simulations atomistic simulator GARAND using an enhanced electrothermal model that considers the impact of the fin geometry on the thermal conductivity. In the simulations, we have compared the statistical variability obtained from full-scale electrothermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electrothermal simulations. The combined effects of line edge roughness and metal gate granularity are considered. The distributions and the correlations between key figures of merit, including the threshold voltage, ON-current, subthreshold slope, and leakage current are presented and analyzed. [ABSTRACT FROM PUBLISHER]

In this paper, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realized with a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- Q interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32-\mu\m silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access adjacent channel leakage ratios are better than -\33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS. [ABSTRACT FROM AUTHOR]

This paper presents a power amplifier (PA) topology to improve the back-off efficiency and the linearity of millimeter-wave (mm-wave) PAs without area overhead. In this paper, an asymmetrical series power combiner with LC tuning circuits is proposed to mimic the Doherty operation. Due to high back-off efficiency and high linearity behavior, the proposed Doherty topology well suits for E-band communication applications. Two transformer-based E-band PAs are designed and measured to demonstrate the proposed mm-wave Doherty concept. The first implementation achieves 16.2-dBm output power with a P1dB of 15.2 dBm using a 0.9-V supply. The second implementation demonstrates 21-dBm output power with a power-added efficiency (PAE) of 13.6% at a 1.5-V supply. The PAE at 6-dB power back-off is still as high as 7%. [ABSTRACT FROM AUTHOR]

The metal–semiconductor interface is fundamental to any semiconductor device and the success of advanced technology nodes critically depends upon the minimization of the contact resistance at the interface. In this paper, we calculate the electronic structure of a metal–semiconductor interface (TiGe/Ge contact) within the framework of first-principles density functional theory simulations. We report the modulation of the Schottky barrier height with respect to the different phases of TiGe metal and different crystallographic orientations of Ge substrate. We further compute the I – V characteristics of the TiGe/Ge contact with nonequilibrium Green’s function formalism, using a two-terminal device configuration. The calculated transmission spectrum allows us to extract the contact resistance at the metal–semiconductor interface. Furthermore, the onset of Ohmic contact for p-doped TiGe/Ge interface is identified by studying the I – V characteristics as a function of increasing active carrier concentration. We find that a doping concentration of 1e21 is sufficient to transform the Schottky contact into Ohmic and thereby achieve a least possible contact resistance at the interfaces. Our paper thus provides useful physical insights into the nanoscale details of the TiGe/Ge interfaces and can guide further process development to minimize the contact resistance. [ABSTRACT FROM PUBLISHER]

This paper presents a CMOS transceiver IC for a single-antenna frequency-modulated continuous wave (FMCW) radar. Since transmitter (Tx) leakage is critical in a single antenna radar with CMOS technology, a comprehensive leakage canceling technique is proposed. It is able to cancel all the leakages caused by antenna reflection, asymmetry of a balanced structure, and lossy substrate without additional power or area. Even-order harmonic leakages from the power amplifier (PA) are also reduced by an even-harmonic filter, which is implemented simply by removing the real ground from the symmetrical point of the PA output transformer. Matching networks are simplified by using a modified coupler structure. A low-noise combining amplifier is used to make the combining circuit compact. As a result, the transceiver achieves the output power of −1.6 dBm, the phase noise of −105.44 dBc/Hz at 1MHz offset, the receiver (Rx) gain of 15.3 dB, and the noise figure of 11.6 dB. Tx leakages are canceled so that the isolation between Tx and Rx is 47.3 dB. The chip consumes 74.1 mA from a 1.5-V power supply. Despite the high integration level, the chip area including pads is 1.7 mm $\times $ 0.9 mm. A {K} -band FMCW radar module with a single antenna is implemented with this chip. [ABSTRACT FROM PUBLISHER]

Design and analysis of low-phase-noise low-jitter subharmonically injection-locked voltage-controlled oscillator (VCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90-nm CMOS process. The issue of the narrow locking range for the subharmonically injection-locked VCO (SILVCO) can be resolved over the variations, especially for high subharmonic number and millimeter-wave band, since the control voltage is adaptively adjusted using the proposed innovative method to refer to the subharmonic input frequency. A theoretical model of the SILVCO with FLL self-alignment technique is addressed for the design consideration and phase noise evaluation. With a subharmonic number of 16, the operation frequency of the proposed $K$ -band circuit is from 24 to 26.1 GHz. The measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are −114.3 dBc/Hz and 56.6 fs, respectively. As the temperature is from 20 °C to 70 °C, the measured deviations of output power, phase noise, and jitter are within 2 dB, 3 dB, and 67 fs, respectively. This paper demonstrates excellent performance and good robustness, and it can be compared with the previously reported state-of-the-art clock generators in silicon-based technologies. [ABSTRACT FROM PUBLISHER]

This paper presents a monolithic pH measurement system with a power conditioning system for supply power derived from harvested energy. The proposed system includes a low-power highly linear pH readout circuits with wide pH values (0–14) and a power conditioning unit based on low dropout (LDO) regulator. The readout circuit provides a square-wave output with the frequency being highly linear corresponding to the input pH values. To achieve that, a simple operational transconductance amplifier is employed to linearly convert the pH sensor output voltage to a current. To overcome the process variations, a simple calibration method is employed in the design which makes the output frequency stay constant over the process, supply voltage, and temperature variations. The prototype circuit is designed and fabricated in a standard 0.13- $\mu \text{m}$ CMOS process and demonstrates a good linearity to cover the entire pH value range from 0 to 14, while the voltage regulator provides a stable supply voltage 1.25 V for the system. The proposed sensor consumes $12.8~\mu \text{W}$ of power for a typical pH value of 7 while occupying a die area of 0.017 mm2. The total die area including the readout circuit and the LDO is 160 $\mu \text{m}\,\,\times 110\,\,\mu \text{m}$ , which makes this system a suitable candidate for low-power miniaturized sensor systems. Both electrical test and in vitro measurement are performed, and a commercial pH meter is employed to make a performance comparison with this paper. The test results of the prototype circuit closely match the measurement results obtained by its commercial counterpart. [ABSTRACT FROM AUTHOR]

This paper presents a 10.56-GHz transceiver with ultracompact transformer-based transmit/receive (T/R) switching via matching network reuse. The reused transformer can operate as T/R switch and impedance matching networks for a power amplifier (PA) and a low-noise amplifier (LNA) simultaneously. The T/R switch, PA, and LNA are fully codesigned, and the interstage matching networks of the PA and LNA are comatched with the T/R switch to improve the performance of the front end (FE). A three-coil transformer is introduced in the PA to improve the linearity and bandwidth of the FE in the transmit (TX) mode. A mode selection unit (MSU) is also utilized in LNA to improve the TX/RX isolation and the linearity of the FE in the TX mode. Utilizing the fully codesign technique in the FE, the bandwidth of the FE is extended to over 4.2 GHz in both the TX and RX modes. A novel “gm-cell-based” broadband programmable gain amplifier (PGA) and a third-order transconductance-capacitor (gm-c) low-pass filter (LPF) are used in analog baseband to provide over 24-dB gain and 1.8-GHz bandwidth adjustment range with ultralow dc power consumption. To prove the concept, the new architecture is implemented in 28-nm CMOS technology. Measurement results prove that the insertion loss of the proposed T/R switch introduced in both the TX and RX modes is ~0.5 dB, and benefiting from this, the RX obtained a 4.2-dB noise figure, and TX obtained 9.9- and 14.1-dBm OP1dB and Psat. The measured single sideband bandwidth of the transceiver is wider than 2.1 GHz in both the TX and RX modes. [ABSTRACT FROM AUTHOR]

In this paper, we present a memristor emulator based on voltage difference transconductance amplifier (VDTA). The proposed memristor emulator circuit contains only one VDTA as an active element and single grounded capacitor which benefits from the integrated circuit. Furthermore, it can be utilized MOS-capacitance instead of the external capacitor in the circuit. The complete memristor emulator is laid by using Cadence Environment using TSMC $0.18\ {\boldsymbol \mu }\text{m}$ process parameters. It occupies an area of $35.7\ {\boldsymbol \mu }\text{m}\,\,\times 29\ {\boldsymbol \mu }\text{m}$. Its simulation results are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner, and radical temperature changes. Moreover, prototype circuit is implemented to confirm the theoretical analysis by employing the single LM13700 commercial device as an active element. Experimental results of the designed memristor emulator are given to investigate its ability for different operating frequencies, the capacitance value and resistor value and DC supply voltage. The experimental results are in accordance with theoretical analyses and simulation results. [ABSTRACT FROM AUTHOR]

In this paper, an extremely low-power and low-complexity CMOS sourceless millimeter-wave (mmW) receiver for the next-generation wireless communication and sensing systems including fifth-generation (5G) is proposed and demonstrated. It makes the use of injection-locked self-oscillating mixers (SOMs) in order to enable a direct conversion to baseband without resorting to any external local oscillator (LO) nor an IF processing block, therefore, greatly reducing power consumption, as well as the receiver’s complexity. This architecture is created through multi-input and multi-output (MIMO) arrays in connection with slicing frequency spectrum or frequency band of interest. In this way, the proposed receiver supports a high data transmission throughput based on the frequency-diversified MIMO, which presents a unique feature in the architectural implementation of a low-power and high bit-rate communication and sensing systems. Transmission and demodulation of a digital modulated signal M-quadratic-amplitude modulation (M-QAM) at 40 GHz, is successfully demonstrated with simulated and measured results. [ABSTRACT FROM AUTHOR]

Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation. [ABSTRACT FROM AUTHOR]

This paper introduces an oversampling, noise-shaping differential successive-approximation-register capacitance-to-digital converter (CDC) architecture for interfacing capacitive sensors. The proposed energy-efficient CDC achieves high-precision capacitive resolution by employing oversampling and noise shaping. The switched-capacitor (SC) integrator is inserted between the comparator and the charge-redistribution digital-to-analog converter to implement noise shaping and to make the interface circuit insensitive to parasitic capacitances. An inverter-based operational transconductance amplifier with a common-mode feedback circuit is employed to implement the SC integrator with subthreshold biasing for low voltage and low power. The ring-oscillator-based comparator is implemented to achieve high energy efficiency. The test chip is fabricated in a 0.18- $\mu \text{m}$ CMOS technology. The proposed CDC experimentally achieves 150 aF absolute resolution and 12.74-ENOB with an oversampling ratio of 15 and a sampling clock of 18.51 kHz. The fabricated prototype dissipates 1.2 and 0.39 $\mu \text{W}$ from analog and digital supplies, respectively, with an energy efficiency figure-of-merit of 187 fJ/conversion step. [ABSTRACT FROM AUTHOR]

This paper presents the design and measurement of an interpolation-based low noise and variable gain cell (IBA-cell) in the 60-GHz band, using a 40-nm CMOS technology. The interpolation-based gain cell is designed for an innovative analog beamforming front end, where the array pattern is not only controlled in the phase domain, but also wins the flexibility in the magnitude domain. The circuit specifications are first derived for the application at 60 GHz. Techniques to combine low noise figure (NF) with variable gain tuning are presented focusing on the NF and linearity (IIP3) on the example of a 60-GHz low noise amplifier and variable gain amplifier. Subsequently, the design and measurement of the whole gain cell (IBA-cell) integrated into a single chip are reported with the technique of a cross-coupled feedback loop to reduce the phase variations over the gain tuning states and enhance the variations of IIP3. The IBA-cell achieves 15.8-dB maximum gain and 6.5-dB NF at 57 GHz with the gain tuning range from −2 to 15.8 dB and IIP3 varying from −11.3 to −16 dBm over the gain control range. The IBA-cell consumes a dc power of maximum 54 mA from 1.1 V. [ABSTRACT FROM AUTHOR]