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This paper studies simultaneous scheduling of production and material transfer that arises in the semiconductor photolithography area. In particular, the right reticle and right job both need to be present to process the job. Jobs are transferred by a material handling system that employees a fleet of vehicles. Reticles serving as an auxiliary resource are also transferred from one place to another by a different set of vehicles. This intricate scheduling challenge, encompassing jobs, reticles, machines, and two distinct sets of vehicles, is explored here for the first time. The paper introduces a multi-stage methodology that involves relaxation, a constructive heuristic, constraint programming, and a warm-start approach to address this complex problem. [ABSTRACT FROM AUTHOR]

Lithography simulation is one of the key steps in physical verification, enabled by the substantial optical and resist models. A resist model bridges the aerial image simulation to printed patterns. While the effectiveness of learning-based solutions for resist modeling has been demonstrated, they are considerably data-demanding. Meanwhile, a set of manufactured data for a specific lithography configuration is only valid for the training of one single model, indicating low data efficiency. Due to the complexity of the manufacturing process, obtaining enough data for acceptable accuracy becomes very expensive in terms of both time and cost, especially during the evolution of technology generations when the design space is intensively explored. In this paper, we propose a new resist modeling framework for contact layers, utilizing existing data from old technology nodes and active selection of data in a target technology node, to reduce the amount of data required from the target lithography configuration. Our framework based on transfer learning and active learning techniques is effective within a competitive range of accuracy, i.e., $3 \times -10 \times $ reduction on the amount of training data with comparable accuracy to the state-of-the-art learning approach. [ABSTRACT FROM AUTHOR]

This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study proposes a Global Attention Generative Adversarial Networks (GAGAN) model to precisely predict the overlay error for the feed-forward data of the front layer, which is used as the important information and process parameters for the advanced process control of the current layer. Experiment results on a semiconductor shop-floor confirms that our proposed method achieves high predictive performance while maintaining extensibility and visual quality. [ABSTRACT FROM AUTHOR]

This paper studies the problem of scheduling machines in the photolithography area of a semiconductor manufacturing facility. The scheduling problem is characterized as an unrelated parallel machine scheduling problem with machine eligibilities, sequence- and machine-dependent setup times, auxiliary resources and transfer times for the auxiliary resources. Each job requires two auxiliary resources: a reticle and a pod. Reticles are handled in pods and a pod contains multiple reticles. Both reticles and pods are used on multiple machines and a transfer time is required if transferred from one machine to another. A novel constraint programming (CP) approach is proposed and is benchmarked against a mixed-integer programming (MIP) method. The results of the study, consisting of a real-world case study at a global semiconductor manufacturer, demonstrate that the CP approach significantly outperforms the MIP method and produces high-quality solutions for multiple real-world instances, although optimality cannot be guaranteed. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays. [ABSTRACT FROM AUTHOR]

Generation of particle defects in semiconductor manufacturing is inevitable, but it has to be minimized to enhance IC yield. There are various causes for the generation of particle defects in different semiconductor manufacturing processes, such as diffusion, thin-film deposition, lithography, etch, and clean. In this paper, primary defect generation mechanisms in thin-film deposition processes, such as atomic layer deposition TiN, radio frequency physical vapor deposition Ti, and physical vapor deposition TiN, are discussed. Various strategies, such as periodic clean optimization, on-load clean, idle pasting, periodic pasting optimization, kit life optimization, target burning optimization, and kit hardware selection that reduce the generation of defects in the thin-film deposition processes are presented. This paper also discusses hardware-induced surface defect and solutions to reduce them. [ABSTRACT FROM AUTHOR]

In deep submicron nodes, the final design patterning quality depends profoundly on the optical proximity correction (OPC) quality. The required pattern fidelity and CD uniformity can never be achieved without good OPC. However, OPC runtime-resource factor has been exponentially increasing every technology node reaching alarming levels, where the OPC cost in terms of resources and turn-around-time is becoming very expensive. In this paper, we present a novel approach for speeding up the OPC convergence process using our model-based initial bias methodology. Our proposed methodology is based on building generic compact bias-models that can predict the final OPC shapes with a good accuracy using the optical simulation parameters. As a result, the OPC initial condition is much closer to the final solution and more than half of the OPC iterations can be saved as a result. In this paper, we present the details of our methodology and our compact initial-bias model we are proposing. We also present our testing results on a 10 nm metal level, where almost 50% of the OPC iterations could be saved when we apply our methodology. [ABSTRACT FROM AUTHOR]

Self-aligned double patterning (SADP) is one of the most promising techniques for sub-20 nm technology. Spacer-is-dielectric SADP using a cut process is getting popular because of its higher design flexibility; for example, it can decompose odd cycles without the need of inserting any stitch. This paper presents the first work that applies the cut process for decomposing odd cycles during routing. For SADP, further, overlay control is a critical issue for yield improvement; while published routers can handle only partial overlay scenarios, this paper identifies all the scenarios that induce overlays and proposes a novel constraint graph to model all overlays. With the developed techniques, our router can achieve high-quality routing results with significantly fewer overlays (and thus better yields). Compared with three state-of-the-art studies, our algorithm can achieve the best quality and efficiency, with zero cut conflicts, smallest overlay length, highest routability, and fastest running time. [ABSTRACT FROM PUBLISHER]

Control of overlay errors in lithography process in semiconductor manufacturing uses in-process measurements of overlay errors from markers distributed across a wafer to adapt controllable process parameters on the relevant lithography tools in order to minimize future errors. Intuitively speaking, the use of a larger number of measurement markers should lead to improvements in one’s ability to control the overlay errors. However, those gains come with simultaneous increases in the metrology times, which negatively impacts throughput. Therefore, one should carefully and strategically select markers which most efficiently enable suppression of overlay errors. This paper proposes a novel optimization framework that couples a recently introduced approach for robust control of overlay errors in photolithography processes with a strategic selection of overlay measurement markers to enable improved control of overlay errors using a reduced number of measurements. Application of the newly proposed method to the data and models from an industrial-scale semiconductor lithography process shows that the newly proposed combination of the robust overlay control paradigm and optimized marker selection enables improved overlay control, even with a significantly reduced number of markers. Thus, the new methodology enables reduction of measurement times and subsequent overall cycle times, without deteriorating the outgoing product quality. [ABSTRACT FROM AUTHOR]

Anisotropic wetting is important in industrial, medical and agricultural applications. In this paper, a novel microstructure performing prominent ultra-anisotropic wetting properties is proposed, with MEMS fabrication process. This microstructure possesses both sharp edge and sharp corner (SESC) in topography. The sharp edge can hinder liquid spreading significantly, whereas the sharp corner enhance spreading. By lithography technology on polymer film, Parylene-C, the microstructure can be tailored into different shapes to achieve various liquid spreading properties, two of which are demonstrated here. 2-D SESC microstructure illustrates ultra-high contact angle difference in parallel and perpendicular directions as high as 93.8°, as well as bidirectional wetting properties. Another microstructure, namely 3-D SESC microstructure, demonstrates specific unidirectional wetting properties. The unique microstructure proposed in this paper provide new ideas for application of controlling liquid spreading on surface. [2019-0077] [ABSTRACT FROM AUTHOR]

In contrast to the conventional planar p-i-n photodiode and a metal-semiconductor-metal photodetector, the 3-D dual-gate photosensitive thin-film transistor (TFT) architectures presented here attain excellent photoresponse characteristics. Operating the device in the subthreshold regime further boosts the photoconductive gain as a result of light-induced decrease in the threshold voltage. This paper presents design considerations along with a performance comparison between 3-D photosensitive TFTs that have π- and FIN-shaped channels and conventional TFT with a planar channel. Our paper shows that the π-shaped structure tends to have a higher sensitivity while the FIN-shaped counterpart is more responsive with wider dynamic range. For both structures, a measured photoconductive gain of 104~106% is obtained with spectral responsivity ranging from near UV to near IR, and the photoresponse time in the range of tens of milliseconds. The 3-D dual-gate photosensitive TFT architecture appears to be very promising for large-area, low-level UV, visible, and IR detection applications. [ABSTRACT FROM AUTHOR]

The thicker photoresists are usually used in the manufacture processes of micro electro mechanical systems (MEMS), bipolar CMOS DMOS (BCD), and insulated gate bipolar transistor (IGBT), due to the thicker film need to be etched, high-dose implant process or other extreme processes have been widely used. This paper deal with the double coating process using the single commercial photoresist, this is an effective and simple approach to achieve the thicker photoresist thickness for the lithography process. We focus on the prediction of the thickness of the double-layer photoresist, which has seldom been reported in past studies. Although the final photoresist cross-section looks like one layer, we divide it theoretically into two layers, refer to as the first layer photoresist and the second layer one. Combined this model, first, an original equation for predicting the final thickness is deduced from the model developed by Emslie et al. Second, we conduct the experiment with different photoresists, soft bake temperatures, and soft bake times, and compare the theoretical predicted thickness to the actual one obtained from the experiment, moreover, a modified equation with satisfied accuracy is proposed, we can prepare the required photoresist thickness quickly and accurately by using this equation, not only can development cost be saved, but also can development cycle be shortened. [ABSTRACT FROM AUTHOR]

This paper studies an unrelated parallel machine photolithography scheduling problem with dual resource constraints (DRC). This is an emerging problem in the semiconductor industry, where the masks can be transferred from one working station to another, increasing the flexibility of production through sharing the auxiliary resource. It gives rise to a complex DRC scheduling problem involving jobs, machines, and masks, restricted by sequence-dependent setup time and station-dependent mask transfer time. This study proposes two mixed-integer programming (MIP) models (Model 1 and Model 2) and an improved naked mole-rat algorithm that hybrids with a genetic algorithm (GA) and variable neighborhood search algorithm (VNS). Numerical experiments show that Model 2 performs better compared with Model 1, and the improved naked mole-rat algorithm brings a significant improvement over GA and VNS. [ABSTRACT FROM AUTHOR]

Detecting layout hotspots is a key step in the physical verification flow. Although machine learning solutions show benefits over lithography simulation and pattern matching-based methods, it is still hard to select a proper model for large scale problems and inevitably, performance degradation occurs. To overcome these issues, in this paper, we develop a deep learning framework for high performance and large scale hotspot detection. First, we use feature tensor generation to extract representative layout features that fit well with convolutional neural networks while keeping the spatial relationship of the original layout pattern with minimal information loss. Second, we propose a biased learning (BL) algorithm to train the convolutional neural network to further improve detection accuracy with small false alarm penalties. In addition, to simplify the training procedure and seek a better tradeoff between accuracy and false alarms, we extend the original BL to a batch BL algorithm. Experimental results show that our framework outperforms previous machine learning-based hotspot detectors in both ICCAD 2012 Contest benchmarks and large scale industrial benchmarks. Source code and trained models are available at https://github.com/phdyang007/dlhsd. [ABSTRACT FROM AUTHOR]

2-D directed self-assembly (DSA) is an emerging lithography for the 5-nm process node and beyond that can substantially increase design flexibility in critical routing layers and reduce the number of cuts for better yield. The state-of-the-art 2-D DSA process manipulates the orientation of double posts inside guiding templates to guide block copolymers (BCPs) to form 2-D patterns. However, a key challenge arises on how to correctly assign double post orientations and place cut patterns to make desired net connections for a given routing instance. In this paper, we propose a novel 2-D DSA-compliant routing (2-D-DCR) framework to systematically derive feasible orientation assignments for double posts to maximize routability. Specifically, 2-D-DCR features a complete set of new routing rules which transform the underlying physical BCP growth principles for large-scale routing, adopts a network-flow-based double-post assignment routing algorithm, and leverages a 2-D DSA line-end creation property to maximally reduce line-end cuts. Experimental results show that our 2-D-DCR can effectively generate a 2-D-DCR solution with zero double post conflicts, maximized routability, and minimized the number of cuts. [ABSTRACT FROM AUTHOR]

Digital circuit physical unclonable function (PUF) has been attracting attentions for the merits of resilience to the environmental and operational variations that analog PUFs suffer from. Existing state-of-the-art digital circuit PUFs, however, are either hybrid of analog-digital circuits which are still under the shadow of vulnerability, or impractical for real-world applications. In this paper, we propose a novel highly nonlinear and secure digital PUF (D-PUF) and the spliced version SD-PUF. The fingerprints are extracted from intentionally induced very large-scale integration interconnect randomness during lithography process, as well as a post-silicon shuffling process. Strongly skewed CMOS latches are used to ensure the immunity against environmental and operational variations. Crucially, a highly nonlinear logic network is proposed to effectively spread and augment any subtle interconnect randomness, which also enables strong resilience against machine learning attacks. On top of it, the expandable architecture of the proposed logic network empowers a novel post-silicon shuffle-splice mechanism, where multiple randomly selected D-PUFs are spliced to be one SD-PUF, pushing the statistical security to a much higher level, while significantly reducing the mask cost per PUF device. It also decouples the trustworthy demands enforced to the foundries or other third party manufacturers. Our proposed PUFs demonstrate close to ideal performance in terms of statistical metrics, including 0 intra-Hamming distance. Various state-of-the-art machine learning models show prediction accuracies almost no better than random guesses when attacking to the proposed PUFs. We also mathematically prove the probability of existence of identical SD-PUF pair is significantly lower than that of D-PUF pair, e.g., such probability of an SD-PUF spliced by 30 D-PUFs is 2.3\times 10^-22 , which is 19 order magnitude lower than that of D-PUF. Benefited from the proposed shuffle-splice mechanism, the mask cost per SD-PUF is also reduced by 300\times than that of D-PUF. [ABSTRACT FROM PUBLISHER]

Multiple patterning lithography has been recognized as one of the most promising solutions, in addition to extreme ultraviolet lithography, directed self-assembly, nanoimprint lithography, and electron beam lithography, for advancing the resolution limit of conventional optical lithography. Multiple patterning layout decomposition (MPLD) becomes more challenging as advanced technology introduces complex coloring rules. Existing works model MPLD as a graph coloring problem; nevertheless, when complex coloring rules are considered, layout decomposition can no longer be modeled accurately by graph coloring. Therefore, in this paper, for capturing the essence of layout decomposition with complex coloring rules, we model the MPLD problem as an exact cover problem. We then propose a fast and exact MPLD framework based on augmented dancing links. Our method is flexible and general: it can consider the basic and complex coloring rules simultaneously, can maintain density balancing, and can handle quadruple patterning and beyond. Experimental results show that our approach outperforms state-of-the-art works on reported conflicts and stitches and is promising for handling complex coloring rules and density balancing as well. [ABSTRACT FROM PUBLISHER]

Multiple e-beam lithography (MEBL) is one of the most promising next generation lithography technologies for high volume manufacturing, which improves the most critical issue of conventional single e-beam lithography, throughput, by simultaneously using thousands or millions of e-beams. For parallel writing in MEBL, a layout is split into stripes and patterns are cut by stripe boundaries, which are defined as stitching lines. Critical patterns cut by stitching lines could suffer from severe pattern distortion or even yield loss. Therefore, considering the positions of stitching lines and avoiding stitching line-induced bad patterns are required during layout design. In this paper, we propose the first work of stitch-aware routing framework for MEBL based on a two-pass bottom-up multilevel router. We first identify three types of stitching line-induced bad patterns which should not exist in an MEBL-friendly routing solution. Then, stitch-aware routing algorithms are, respectively, developed for global routing, layer/track assignment, and detailed routing. Experimental results show that our stitch-aware routing framework can effectively reduce stitching line-induced bad patterns and thus may not only improve the manufacturability but also facilitate the development of MEBL. [ABSTRACT FROM PUBLISHER]

In advanced IC manufacturing, as the gap increases between lithography optical wavelength and feature size, it becomes challenging to detect problematic layout patterns called lithography hotspot. In this paper, we propose a novel fuzzy matching model which extracts appropriate feature vectors of hotspot and nonhotspot patterns. Our model can dynamically tune appropriate fuzzy regions around known hotspots. Based on this paper, we develop a fast algorithm for lithography hotspot detection with high accuracy of detection and low probability of false-alarm counts. In addition, since higher dimensional size of feature vectors can produce better accuracy but requires longer run time, this paper proposes a grid reduction technique to significantly reduce the CPU run time with very minor impact on the advantages of higher dimensional space. Our results are very encouraging, with average 94.5% accuracy and low false-alarm counts on a set of test benchmarks. [ABSTRACT FROM AUTHOR]

Lithography simulation is computationally expensive for hotspot detection. Machine learning-based hotspot detection is a promising technique to reduce the simulation overhead. However, most learning approaches rely on a large amount of training data to achieve good accuracy and generality. At the early stage of developing a new technology node, the amount of data with labeled hotspots or nonhotspots is very limited. In this paper, we propose a semisupervised hotspot detection with self-paced multitask learning paradigm, leveraging both data samples with/without labels to improve model accuracy and generality. Experimental results demonstrate that our approach can achieve 4.6%–6.5% better accuracy at the same false alarm levels than the state-of-the-art work using 10%–50% of training data. [ABSTRACT FROM AUTHOR]

Rectangular grid graph (RGG) and diagonal grid graph (DGG) are induced subgraphs of a rectangular or diagonal grid, respectively. Their $k$ -coloring problem has direct applications in printing contact/via layouts by multipatterning lithography (MPL). However, the problem in general is computationally difficult for $k>2$ , while it remains an open question on grid graphs due to their regularity and sparsity. On the other hand, directed self-assembly (DSA) technique can work with MPL to optimize the graph by grouping neighboring vertices such that $k$ can be reduced, but the problem of deploying the grouping for coloring is even more intractable. In this paper, we study both of the $k$ -coloring problems, with and without DSA grouping, on RGG and DGG. Without grouping, a complete $k$ -coloring analysis is conducted and particularly the NP-completeness of 3-coloring on a diagonal grid is proved. When considering grouping, we present a 3-coloring solution and prove the NP-completeness to solve the problem of $k=2$. [ABSTRACT FROM AUTHOR]

As CMOS technology continues to scale down due to advances in lithography, the interaction of neighboring patterns is exacerbated. Every pattern printed on silicon is influenced by its neighbors given a technology-specific interaction range. As transistors and cells shrink to sizes of the same order of the interaction range, pattern dependencies at the 16-nm node (and below) make the prediction of functional and parametric yield challenging. Precharacterizing all combinations of layouts as a function of all possible neighboring patterns is impractical due to exponential complexity, whereas silicon characterization of all patterns is practically impossible. In this paper, we propose a virtual characterization vehicle (VCV) methodology that can exhaustively identify all uniquely occurring layout patterns in a standard cell library. VCVs can expose all cell neighboring arrangements as a function of a radius of influence while compiling the pattern frequency and also uncovering the arrangement of cells that create unique patterns. Effects that span multiple layers are also captured in our analysis. VCV results can be used to co-design libraries by suggesting favorable compositions as well as favorable layout styles. Finally, VCVs can be turned into test-chips that are guaranteed to cover all identified patterns with the aid of self-testing features. An extremely regular library was developed in 16-nm FinFET technology and is used to showcase our pattern analysis in which DFM quality is shown to be improved with respect to commercial libraries. Our silicon results demonstrate the feasibility of turning the VCV approach into real silicon test chips. [ABSTRACT FROM AUTHOR]

As extreme ultraviolet (EUV) lithography enters high volume manufacturing (HVM) to enable the sub-7nm scaling roadmap, characterizing and monitoring defects that print at wafer level are of critical importance to yield. This is especially true for defects coming from the EUV mask, due to multi-layer defects or added particles or growth on mask during its use, and for defects coming from the pattern formation process itself, which are known as stochastic printing defects or simply stochastic defects. In this paper we focus on developing inspection solutions for stochastic defects, which essentially are random local variations that occur between structures that should, in principle, print identically. These defects occur at significant frequencies with current state-of-the-art processes. Specifically, we discuss the importance of detecting these defects using KLA broadband plasma (BBP) optical inspection systems and the development of useful analysis methodologies. In addition, we describe use of traditional focus-dose process window discovery methodology developed on these optical inspection systems, for a foundry N5 equivalent M2 layer with both hybrid EUV and direct EUV patterning schemes. We highlight the impact of EUV stochastics to the overall process window. [ABSTRACT FROM AUTHOR]

This paper studies the application of fixed-parameter tractable (FPT) algorithms to solve computer-aided design (CAD) problems. Specifically, we focus on layout decomposition problems for four lithography technologies: 1) double patterning lithography (DPL); 2) DPL with e-beam lithography; 3) DPL with directed self-assembly; and 4) DPL with directed self-assembly and e-beam lithography. Layout decomposition for the first three technologies are long-standing open problems without efficient optimal solutions, and the fourth technology is very promising in the future. The proposed approaches use ideas drastically different from all the previous works and can normally get optimal solutions in a short time. We show the great potential of applying FPT algorithms to solve more NP-hard problems efficiently in CAD. [ABSTRACT FROM AUTHOR]

As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead. [ABSTRACT FROM PUBLISHER]

Optical proximity correction (OPC) is invaluable to precise layout manufacturing in the advanced nanometer technologies. However, lack of research activity on OPC for analog integrated circuits has currently led to sole dependence on digital solutions. In this paper, we propose a rule-based OPC (RB-OPC) methodology with process variation (PV) consideration, which is integrated into an analog layout migration process. Based on the unique features of analog layouts, the accuracy limitation of RB-OPC is compensated by local wire widening and wire shifting operations during layout migration. Moreover, innovative PV-band shifting is deployed to preserve analog circuit performance against PV. According to our experimental results, the proposed analog layout migration with PV-aware RB-OPC can achieve much higher efficiency with an even lower mask complexity and an acceptable edge placement error compared to some well-known commercial and academic digital solutions. The circuit performance by using our proposed methodology is also better than that from alternative methods in the mismatch scenarios due to our special PV-band handling on transistor gates. [ABSTRACT FROM AUTHOR]

Line edge roughness (LER) is a critical variability source in scaled FinFETs. LER produces line width roughness (LWR) that causes threshold voltage ( VT ) variability. Various lithography techniques demonstrate characteristic LER-LWR relationship. For translating LER/LWR to the VT distribution, an analytical model for uncorrelated fin edges (correlation coefficient, \rho =0 ) has been presented in the literature. However, a range of correlation coefficients ( 0\le \rho \le 0.85 ) between two fin edges is experimentally observed for various lithography techniques. In this paper, we present an analytical model to predict \rho dependent \mu ) and standard deviation ( \sigma ) for \rho and nominal fin width {W}_{\text {fin}}) and LER variability (correlation length \Lambda $ and correlation coefficient $\rho $ ) parameters to show excellent match. The model is 1000 times faster compared with TCAD simulations. [ABSTRACT FROM AUTHOR]

The advent of multigate transistor technology for 20-nm technology node and beyond, has increased the importance of wire parasitics, in particular, wire resistance in determining the circuit delay computation. Variability in wire dimensions directly impacts the wire parasitics, hence, the overall system performance. For the first time, in this paper, we study circuit variability for 11- and 7-nm technology nodes based on GDSII-level layouts. We propose novel hybrid multipatterning flows, which combine the litho-etch-litho-etch and self-aligned-spacer technologies, to reduce circuit variability induced by the lithography process. We engineer the hybrid solutions to have reduced variability in wire resistance, and circuit performance, and develop variability models for each patterning proposal. We also find the increasing need of these hybrid solutions at the 7-nm technology node. For Extreme Ultraviolet (EUV) lithography to enable higher circuit performance than the proposed patterning regimes, it requires a high precision in core variation of less than 1 nm. [ABSTRACT FROM AUTHOR]

Tilted ion implantation (TII) can be used in conjunction with pre-existing masking features on the surface of a substrate to form features with smaller dimensions and smaller pitch. In this paper, the resolution limit of this sub-lithographic patterning approach is examined via experiments as well as Monte Carlo process simulations. TII is shown to be capable of defining features with size below 10 nm, in a self-aligned manner, reproducing with high fidelity the line-edge roughness of the pre-existing masking features. Since it has relatively low associated process cost, TII-enhanced patterning is a promising approach to advance high-volume manufacture of integrated circuits beyond the 7-nm technology node. [ABSTRACT FROM PUBLISHER]

In sub-10 nm technology nodes, next generation lithography technologies are urgently required, and the diblock copolymer directed self-assembly (DSA) technology has shown its strong potential for contact/via layer fabrication. In addition, post-layout redundant via insertion has become a necessary step to guarantee sufficient yield and circuit reliability. However, existing redundant via insertion algorithms are not suitable for DSA since they could seriously deteriorate via manufacturability. In contrast, a sophisticated DSA-aware redundant via insertion algorithm may not only enhance circuit reliability but also improve DSA manufacturability. In this paper, we propose the first work of simultaneous guiding template optimization and redundant via insertion for DSA. Two integer linear programming (ILP)-based algorithms and an efficient graph-based approach are provided. The two ILP-based algorithms optimally maximize via manufacturability and the redundant via insertion rate. In addition, reduction techniques are presented to greatly improve the computational efficiency of ILP. For the graph-based approach, all feasible via patterns composed of original vias and redundant vias are identified. Then, the original problem is transformed into a graph formulation and efficiently optimized. Experimental results show that the ILP-based algorithms can find optimal solutions with reasonable computation time, and the graph-based algorithm can solve the problem much more efficiently and derive near-optimal solutions. [ABSTRACT FROM AUTHOR]

As the feature size keeps scaling down and the circuit complexity increases rapidly, a more advanced hybrid lithography, which combines multiple patterning and electron-beam lithography (EBL), is promising to further enhance the pattern resolution. In this paper, we formulate the layout decomposition problem for this hybrid lithography as a minimum vertex deletion K -partition problem, where K is the number of masks in multiple patterning. Stitch minimization and EBL throughput are considered uniformly by adding a virtual vertex between two feature vertices for each stitch candidate during the conflict graph construction phase. For K = 2 , we propose a primal-dual (PD) method for solving the underlying minimum odd-cycle cover problem efficiently. In addition, a chain decomposition algorithm is employed for removing all “noncyclable” edges. Furthermore, we investigate two versions of the PD method, one with planarization and one without. For K > 2 , we propose a random-initialized local search method that iteratively applies the PD solver. Experimental results show that compared with a two-stage method, our proposed methods reduce the EBL usage by 65.5% with double patterning and 38.7% with triple patterning on average for the benchmarks. [ABSTRACT FROM PUBLISHER]

VLSI layout patterns provide critical resources in various design for manufacturability research, from early technology node development to back-end design and sign-off flows. However, a diverse layout pattern library is not always available due to long logic-to-chip design cycle, which slows down the technology node development procedure. To address this issue, in this paper, we explore the capability of generative machine learning models to synthesize layout patterns. A transforming convolutional auto-encoder (TCAE) family is developed to learn vector-based instantiation of squish pattern topologies. We show our TCAE models can capture simple design rules and enlarge the existing squish topology space under certain transformations. With adaptive configurations, the proposed G-TCAE framework allows both massive pattern generation and context-specific pattern generation. Geometry information of each squish topology is obtained from an associated linear system derived from design rule constraints. Experiments on $7nm$ EUV designs show that our framework can more effectively generate diverse pattern libraries with DRC-clean patterns compared to a state-of-the-art industrial layout pattern generator. [ABSTRACT FROM AUTHOR]

Overlay errors depict misalignment between neighboring pattern layers on the wafer and are a critical measure of quality in lithography processes. In addition, stack-up overlay errors, which describe misalignments across non-neighboring layers, have also been shown to be important for product performance. Models relating overlay errors to tool parameters are the foundation of control methods that utilize in-process error measurements to adapt controllable parameters to minimize those errors. Unfortunately, these models are subject to noise and modeling errors whose characteristics cannot be accurately modeled, in that assumptions of Gaussianity or independence of noise terms, or perfect knowledge of model parameters cannot be ascertained. This paper proposes a methodology for robust control of lithography errors that is capable of handling parametric uncertainties in overlay models, as well as shortcomings in describing the noise and modeling errors. A series of simulations was conducted using a model available in the literature, as well as a model and data from a major 300 mm semiconductor fab. The results illustrate advantages of the proposed robust approach, with benefits increasing with higher levels of uncertainties. The results also depict specific improvements of errors in outer regions of the wafer, which are known to suffer from lower yields. [ABSTRACT FROM AUTHOR]

In the photolithography process of wafer fabrication, a mask pattern is transferred to a wafer in a layer-by-layer fashion, and the pattern alignment of adjacent layers is critical to the wafer yield. To enhance the alignment precision, an overlay metrology system measures the overlay error at some markers on the wafer, and the error information is used for constructing an overlay correction model. During the overlay alignment, the layout of the markers has a significant impact on the correction of the overlay error. After the maximum number of available markers has been determined based on the quality and turn-around time of the target device, the positions of those markers should be determined in such a way that the overlay error correction model shows robust performance for future wafers. In this paper, we propose a sparse particle swarm optimization algorithm to find an optimal marker layout in terms of robust performance characterized by the overlay error prediction and irregularity of marker positions. In the experiment, the performance of the marker layouts suggested by several search algorithms was tested on three different layers, and the proposed algorithm demonstrated superiority over the other algorithms. [ABSTRACT FROM AUTHOR]

Thin-film transistors (TFTs) are the fundamental building blocks of today’s display industry. To achieve higher drive currents and device density, it is essential to scale down the channel lengths of TFTs. To be able to fabricate short-channel TFTs in large volumes is also equally important in order to realize lower fabrication costs and higher throughput. In this paper, we demonstrate the application of substrate conformal imprint lithography (SCIL) to pattern top-gate (TG) self-aligned (SA) amorphous indium gallium zinc oxide TFTs down to channel length ${L}_{\textsf {G}} = \textsf {450}$ nm with good device scaling properties resulting in average field-effect mobility (${\mu }_{FE}$) $= \sim 10$ cm $^{\textsf {2}}\cdot \text{V}^{-\textsf {1}}\cdot \text{s}^{\textsf {-1}}$ , ${V}_{\mathrm{ON}} = \,\sim 0.5$ V, and subthreshold swing (SS) $= \sim 0.3$ V/decade. The device performance as a function of channel length outlines the importance of dopant diffusion control for realizing submicrometer SA TFTs. The results demonstrate the compatibility of SCIL-based large-area patterning for the realization of submicrometer TG SA TFTs with a potential for high throughput. [ABSTRACT FROM AUTHOR]

In order to maintain a competitive edge in the face of increasing global competition in the semiconductor memory market, device makers in the IC memory industry need to continuously improve their productivity by implementing novel manufacturing strategies that are applicable to the rapid market changes characteristic of the industry. Conventional wafer productivity strategies typically only focus on maximizing gross die out, a strategy which does not address wafer productivity for profitability, i.e., return on investment (ROI), with respect to current market situations, since ROI is significantly influenced not only by the number of gross die out, but also by other factors both within the manufacturing line, for example by the number of photolithography shots per wafer, and also by external factors, most importantly the market price of the memory devices being produced. In this paper, we propose a novel productivity model based on ROI and use the ROI-based model to evaluate wafer maps and thereby to determine optimal chip sizes for maximizing fab productivity. To evaluate wafer productivity accurately, we predicted yields from various wafer map configurations using deep neural networks, and, to search for productivity-maximal wafer maps in extremely large search spaces, we adopted differential evolution as the optimization technique. Comparison results have demonstrated that our proposed method effectively improved wafer productivity by up to 7.96%, in contrast with the old method. By incorporating these market-oriented indicators into standard yield models, we offer a new way for memory device manufacturers to maximize productivity and maintain competitive advantage for their semiconductor fabrication lines. [ABSTRACT FROM AUTHOR]

The design of a novel low-noise high-force linear motor for precision positioning applications, such as in semiconductor lithography, is presented in this paper. New magnetic designs achieve low noise and vibration by reducing high spatial-frequency magnetic field components, which cause harmonic vibrations of a moving stage. To reduce such force harmonic content, our new motor has fine teeth, narrow slots with high slot aspect ratio, five phases, and a moving skewed Halbach magnet array. As compared with a commercially available iron-core motor, in our new design, the acoustic noise level in Pascals is reduced by more than 90%, corresponding to a 20 dB reduction in sound pressure level, even with a nonskewed magnet array. Using a skewed magnet array, the cogging-driven and velocity-dependent noise is further reduced by 90% in Pascals. This new linear motor simultaneously is capable of very high shear force densities in order to support high-acceleration motions, and thus provides new options for high-performance and quiet linear motion devices. [ABSTRACT FROM AUTHOR]

In this paper, the evolution of various lithographic processes aimed at fabricating robust tantalum nitride (TaN) resistors in GaAs-based BiFET and BiHEMT technologies are discussed in detail. Such approaches include the common image reverse photograph process (via amine poisoning) using a positive tone resist, the use of a chemically amplified negative tone resist, and also straight patterning of a positive tone resist. The aforementioned approaches were found to have their own unique challenges as it applied to printing robust TaN-based resistors approaching nearly a micron in width which is needed for high density mixed signal designs. We will explore many of these challenges in detail for the various lithography schemes. [ABSTRACT FROM AUTHOR]

1-D gridded design is one of the most promising solutions that can enable the scaling to 10 nm technology node and beyond. Line-end cuts are needed to fabricate 1-D layouts, where two techniques are available to resolve the conflicts between cuts: 1) cut redistribution and 2) cut mask assignment. In this paper, we consider incorporating the two techniques to enable the manufacturing of cut patterns in 1-D gridded design. We consider both 2-mask case (double patterning is performed on the cuts) and 3-mask case (triple patterning is performed on the cuts). We first present an accurate integer linear programming (ILP) formulation that can solve the co-optimization of cut redistribution and mask assignment optimally. In addition, we propose efficient graph-theoretic approaches based on a novel integrated graph model and a longest-path-based refinement algorithm. Experimental results demonstrate that our graph-theoretic approaches are orders of magnitude faster than the ILP-based method and meanwhile it can obtain very comparable results. For 2-mask case, comparing with the method that solves mask assignment and cut redistribution optimally but separately, our graph-theoretic approach that solves the two tasks simultaneously can achieve $95.0{\times }$ smaller cost on average. We also extend our graph-theoretic approach to 3-mask case. Comparing with the method that reduces the 3-mask problem to 2-mask problem and solves it indirectly, our innovative approach that solves the problem directly based on a novel framework of identifying and solving 4-cliques can achieve 7.6% smaller cost on average. [ABSTRACT FROM AUTHOR]

In this paper, the low-temperature (≤150 °C) fabrication and characterization of flexible indium–gallium–zinc–oxide (IGZO) top-gate thin-film transistors (TFTs) with channel lengths down to 280 nm is presented. Such extremely short channel lengths in flexible IGZO TFTs were realized with a novel manufacturing process combining two-photon direct laser writing (DLW) photolithography with Ti/Au/Ti source/drain e-beam evaporation and liftoff. The resulting flexible IGZO TFTs exhibit a saturation field-effect mobility of 1.1 cm $^{\textsf {2}}\cdot \textsf {V}^{-\textsf {1}}\cdot \text {s}^{-\textsf {1}}$ and a threshold voltage of 3 V. Thanks to the short channel lengths (280 nm) and the small gate to source/drain overlap ($5.2~\mu \text{m}$), the TFTs yield a transit frequency of 80 MHz (at 8.5-V gate–source voltage) extracted from the measured S-parameters. Furthermore, the devices are fully functional when wrapped around a cylindrical rod with 6-mm radius, corresponding to 0.4% tensile strain in the TFT channel. These results demonstrate a new methodology to realize entirely flexible nanostructures and prove its suitability for the fabrication of short-channel transistors on polymer substrates for future wearable communication electronics. [ABSTRACT FROM AUTHOR]

As nanometer technology advances, conventional optical proximity correction (OPC) that minimizes the edge placement error (EPE) at the nominal process condition alone often leads to poor process windows. To improve the mask printability across various process corners, process-window OPC optimizes EPE for multiple process corners, but often suffers long runtime, due to repeated lithographic simulations. This paper presents an efficient process variation (PV)-aware mask optimization framework, namely PVOPC, to simultaneously minimize EPE and PV band with fast convergence. The PVOPC framework includes EPE-sensitivity-driven dynamic fragmentation, PV-aware EPE modeling, and correction with three new EPE-converging techniques and a systematic subresolution-assisted feature insertion algorithm. Experimental results show that our approach efficiently achieves high-quality EPE and PV band results. [ABSTRACT FROM AUTHOR]

In this paper, bridged-grain (BG) low-temperature polycrystalline silicon thin-film transistors (TFTs) were fabricated. The periodic submicrometer BG structures were patterned using a maskless and large-area applicable laser interference lithography (LIL) technology, which was able to minimize extra manufacture costs of BG structures. Compared with conventional metal-induced crystallized (MIC) poly-Si TFTs, the BG-MIC TFTs involving the LIL technology exhibited reduced threshold voltage and subthreshold swing, improved ON–OFF current ratio, and suppressed leakage current and kink effect. Since the exposure energy density is one of key parameters for LIL, its relationship with device electrical performance was further investigated. It was found that when the exposure energy density was in the vicinity of 60 mJ/cm2, these BG-MIC TFTs could perform optimally without device uniformity degradation. [ABSTRACT FROM PUBLISHER]

Modern very large-scale integration (VLSI) layout databases routinely consist of 10e15 edges, and thus problems of information retrieval, intellectual property (IP) inventory control, tampering detection, IP infringement detection, data tagging, and database version control, are extremely computationally intensive. All these tasks can be reduced to the problem of copy detection, and in this paper, we propose a canonical hash function for VLSI layout datasets which can be used for efficient copy detection and signature generation. The proposed signature is independent of the ordering of the layout elements, their tessellation, resolution, and even vertex count. These parameters, which do not contribute to the final wafer image, increase the entropy of the data and thus standard hash functions such as message digest (MD5) or secure hash algorithm (SHA), are not suitable for this problem of VLSI layout hashing. In this paper, a novel, entropy reduced hash function is developed which can be used to alleviate the above mentioned problems of physical IP management. The proposed method has O(n \log n + k) time complexity, and O(\sqrt n) memory complexity, where n is the number of edges in the input layout, and k is the number of intersections between edges. The proposed system has been implemented, and computational results validating our approach are also provided. [ABSTRACT FROM AUTHOR]

Electron-beam (e-beam) lithography has long been employed for mask writing but the write time is increasing due to the escalating mask pattern complexity. Besides, e-beam direct write is being pursued as an alternative solution for chip production in the sub-22 nm regime. To improve the throughput of e-beam lithography, character projection method is commonly employed and a critical problem is to pack as many useful characters as possible onto the stencil. In this paper, we consider three enhancements in packed stencil design over previous works. First, the fact that the pattern of a character can be located anywhere within its enclosing projection region is exploited to facilitate flexible blank space sharing. Second, the use of multiple shaping apertures with different sizes is explored. Third, the use of overlapping shots for printing some characters is investigated. For the packed stencil design problem with flexible blank space sharing and multiple shaping apertures, two dynamic programming-based algorithms are proposed, one allows overlapping shots and the other does not. Experimental results show that the proposed enhancement and the associated algorithms can significantly reduce the total shot count and hence improve the throughput of e-beam lithography. [ABSTRACT FROM PUBLISHER]

Grayscale mask creation has for the most part been restricted to over-simplified optical and resist models usually based on a contrast curve approach. While this technique has proven to work for microstructures of large dimensions (ten to hundreds of micrometers), its capability has not been assessed for microstructures with smaller dimensions. In this paper, a rigorous lithographic model has been developed in Python to simulate the process of imaging, exposure and development of an i-line photoresist. Using this model, a mask data preparation algorithm capable of optimizing simultaneously both the size and position of the dots on a grayscale mask has been implemented. Experimental results after development of the photoresist confirm the capability of our mask data preparation algorithm to achieve microstructures with dimensions ranging between 1 to 3 μm. [2021-0018] [ABSTRACT FROM AUTHOR]

Positioning calibration under dynamic conditions is becoming increasingly of interest for high precision fields, such as additive manufacturing and semiconductor lithography. Heterodyne interferometry is often used to calibrate a stage’s position because interferometry has a high dynamic range and direct traceability to the meter. When using heterodyne interferometry, filtering is routinely performed to process and determine the measured phase change, which is proportional to the displacement from one target location to another. The filtering in the signal processing introduces a phase delay dependent on the detection frequency, which leads to displacement errors when target velocity is non-constant as is the case in dynamic calibrations. This paper presents a phase delay compensation method by measuring instantaneous detection frequency and solving for the corresponding phase delay in a field-programmable gate array (FPGA) in real time. The FPGA hardware-in-the-loop simulation shows that this method can significantly decrease the displacement error from ±100’s nm to ±3 nm in dynamic cases and it will still keep subnanometer resolution for quasi-static calibrations. [ABSTRACT FROM PUBLISHER]

In this paper, we study row-based detailed placement refinement for triple patterning lithography (TPL), which asks to find a refined detailed placement solution as well as a valid TPL layout decomposition under the objective of minimizing the number of stitches and the half-perimeter wirelength. Our problem does not have precoloring solutions of cells as the input, and it allows using techniques, including white space insertion, cell flipping, adjacent-cell swapping, and vertical cell movement, to optimize the solution quality. We first present (resource-constrained) shortest-path-based algorithms for several TPL-aware single-row placement problems that allow or disallow perturbing a given cell ordering. Based on these algorithms, we then propose an approach to our TPL-aware detailed placement refinement problem, which first minimizes the number of stitches and then minimizes the wirelength. Finally, we report extensive experimental results to demonstrate the effectiveness and efficiency of our approach. [ABSTRACT FROM PUBLISHER]

Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed. [ABSTRACT FROM PUBLISHER]