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Superior scalability and better gate-to-channel capacitive coupling can be achieved with adopting gate-all-around (GAA) device architecture. However, compared against FinFET device structure, the GAA device is not very cost-effective. In addition, its yield for mass production is not as high as expected. In order to explore the device design option for extending the current FinFET device out, we have come up with a new idea, i.e., novel device structure to increase the effective channel width without affecting the contacted poly pitch (CPP). A novel u-FinFET structure is a type of FinFET that has a u-shaped channel. By using 3-D TCAD simulation, it turned out that the u-FinFET (vs. conventional bulk/SOI FinFETs) shows a 27.3% higher drain current at $V_{\mathrm {GS}}$ = 0.7 V because of its 28.7% wider effective channel width. Especially, the u-FinFET can be adopted for high performance applications because it can implement a wider channel width for a given layout area. Moreover, taking advantages of using the current processes and materials for bulk/SOI FinFET, the u-FinFET can be fabricated (which must be very cost-effective). Hence, with taking advantages of using the u-FinFET structure, the current FinFET platform would last more.

For higher density of transistors in Integrated Circuit (IC), various scaling technologies have been introduced. In the light of the physical limit in advancing single-gate transistor architecture, the structural transition from planar device architecture toward 3D device architecture (of which the representative one is Fin-shaped Field-Effect Transistor, or FinFET) manifests itself. However, during fabrication, the unexpected process-induced random variations of the transistor’s electrical characteristics have become more extreme with aggressively scaling down the physical dimension of transistor as well as with evolving from 2D to 3D device structure. Consequently, accurate and rapid estimation of the random variations conditioned on the variation sources (e.g., LER, RDF, and WFV) is required. Recently, machine learning-based approaches were utilized to estimate the LER-induced variations, but they were highly dependent on modeling and evaluation assumptions (e.g., Gaussian or independence). To that end, firstly, we introduce a GAN-based framework for the estimation of process-induced random variations. Since GAN is free from distributional assumptions, this enables precise prediction and, more importantly, enables unified estimation, i.e., adaptable to various variation sources. Secondly, to achieve better generalization on unseen conditions, we additionally suggest a two-step learning strategy utilizing the latest Conditional GAN models. Thirdly, we introduce sample-based evaluation procedure which measures the difference between two sample sets from a probabilistic perspective. Finally, the evaluation results on LER and RDF/WFV datasets show that our GAN-based framework is computationally efficient and is able to generate synthetic samples similar to the TCAD simulated samples that contain random variations, both qualitatively and quantitatively. From such results, our GAN-based framework is expected to be successfully applied to real data, and consequently be able to reliably estimate the random variations of fabricated transistors with multiple orders of magnitude speed-up compared to the conventional TCAD simulation-based estimation.

To design a device that is robust to process-induced random variation, this study proposes a machine-learning-based predictive model that can simulate the electrical characteristics of FinFETs with process-induced line-edge roughness. This model, i.e., a Bayesian neural network (BNN) model with horseshoe priors (Horseshoe-BNN), can significantly reduce the simulation time (as compared to the conventional technology computer-aided design (TCAD) simulation method) in a sufficiently accurate manner. Moreover, this model can perform autonomous model selection over the most compact layer size, which is necessary when the amount of data must be limited. The mean absolute percentage error for the mean and standard deviation of the drain-to-source current $\left ({\mathrm {I}_{\mathrm {DS}} }\right)$ were ~0.5% and ~6%, respectively. By estimating the distribution of the current-voltage characteristics, the distributions of the other device metrics, such as off-state leakage current and threshold voltage, can be estimated as well.

Line-edge-roughness (LER) is one of undesirable process-induced random variation sources. LER is mostly occurred in the process of photo-lithography and etching, and it provokes random variation in performance of transistors such as metal oxide semiconductor field effect transistor (MOSFET), fin-shaped field effect transistor (FinFET), and gate-all-around field effect transistor (GAAFET). LER was analyzed/characterized with technology computer-aided design (TCAD), but it is fundamentally very time consuming. To tackle this issue, machine learning (ML)-based method is proposed in this work. LER parameters (i.e., amplitude, and correlation length X, Y) are provided as inputs. Then, artificial neural network (ANN) predicts 7-parameters [i.e., off-state leakage current (Ioff), saturation drain current (Idsat), linear drain current (Idlin), low drain current (Idlo), high drain current (Idhi), saturation threshold voltage (Vtsat), and linear threshold voltage (Vtlin)] which are usually used to evaluate the performance of FinFET. First, how datasets for training process of ANN were generated is explained. Next, the evaluation method for probabilistic problem is introduced. Finally, the architecture of ANN, training process and our new proposition is presented. It turned out that the prediction results (i.e., non-Gaussian distribution of device performance metrics) obtained from the ANN were very similar to that from TCAD in the respect of both qualitative and quantitative comparison.

A two-dimension (2D) atomic-threshold-switching field-effect transistor (ATS-FET) was implemented, by connecting an AgTi/HfO2-based threshold-switching (TS) device in series to the drain electrode of the 2D baseline-FET with molybdenum disulfide (MoS2) channel material. We optimized/developed the Ag/HfO2-based TS device because its characteristic is associated to the way how to achieve high performance of the 2D ATS-FET. By reducing the effective device area of the Ag/HfO2-based TS device down to $4~\mu \text{m}^{2}$ , low threshold voltage ( $\text{V}_{\mathrm {T}} \sim 0.42$ V), low threshold current (IT, drain current at the threshold voltage, $\sim 3.79 \times 10^{-11}$ A), and low VT variation (~0.09 V) were achieved. This is because the randomly formed filaments and electric field are better controlled with the scaled effective area. Next, the titanium (Ti)-injection barrier layer was inserted between the top electrode and the switching layer, while maintaining the optimized area in the TS device. The inserted Ti-injection barrier layer prevents the migration of Ag ions into the switching layer, enabling the stable TS operation even under the compliance current of $100~\mu \text{A}$ . Additionally, it locally restricts the region where the filaments are created inside the switching layer, resulting in a 17% lower VT variation and stable IT to approximately $\sim 1.5 \times 10^{-11}$ A in 100 cycles. Due to the low off-state leakage current and low variation characteristic of the optimized AgTi/HfO2-based TS device, the 2D ATS-FET (vs. 2D baseline-FET) shows the reduction of off-state leakage current (by $\sim 10^{2}$ in sub-threshold region) and the stable switching characteristic. The proposed 2D ATS-FET shows stably steep switching characteristics, e.g., sub-threshold swing under forward bias (~19 mV/decade) and reverse bias (~26 mV/decade), because of its abruptly switching characteristics of the TS device.

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS)

Previous studies have suggested that the operating voltage and energy-delay properties of a nanoelectromechanical (NEM) system can be improved using the negative capacitance (NC) effect of ferroelectric materials. However, the advantages of using the NC effects alone have been utilized for perovskite ferroelectric materials, which is incompatible in complementary metal-oxide-semiconductor (CMOS) fabrication processes. In this work, a CMOS-compatible HfO2-based ferroelectric material is used for the NC + NEM system. The effects of the ferroelectric properties [i.e., remnant polarization (Pr) and coercive field (Ec)] on the NC + NEM system performance are studied in detail. The results show that the NC + NEM system can operate as a relay or a memory device depending on the Pr and Ec values. Moreover, the pull-in/out voltages of the NC + NEM system are more sensitively affected by Ec rather than Pr and decrease as Ec increases. The device design guideline with appropriate Pr and Ec values of the HfO2-based ferroelectric material is thus developed and discussed to improve the electrical characteristics of NC + NEM relay/memory devices.

The energy-delay sensitivity of a nanoelectromechanical (NEM) relay and an NEM relay with the negative capacitance of a ferroelectric capacitor (NC + NEM relay) are theoretically investigated. The energy-delay characteristics of the NC + NEM relay deteriorate compared to those of the NEM relay when its movable beam becomes shorter/thicker than the critical beam length/thickness. The energy-delay characteristics of the NC + NEM relay (vs. the NEM relay) can be improved by increasing/decreasing the movable beam length/thickness. However, the maximum length and minimum thickness of the movable electrode are specified. This is necessary to avoid stuck-on failure. This study provides guidelines for improving the switching energy-delay characteristics and the operating voltage of the NC + NEM relay (vs. the NEM relay) by optimizing the device design variables.

ML (Machine Learning)-based artificial neural network (ANN) model is proposed to estimate the LER (line edge roughness)-induced performance variation in Fin-shaped Field Effect Transistor (FinFET). For a given LER features such as rms amplitude(Δ), correlation length along x-direction (AX), and correlation length along y-direction (AY), the metrics for device performance such as on-state drive current, off-state leakage current, threshold voltage, and subthreshold swing can be computing-efficiently estimated with the ANN model.

Gate configuration phase transition fully depleted silicon-on-insulator (FDSOI) metal- oxide-semiconductor field-effect transistor (MOSFET) without an external resistor is proposed using Pb(Zr0.52Ti0.48)O3 (PZT)-based threshold selector (TS). Under 1 μA compliance current condition, the PZT-based TS exhibits its threshold switching property at ~0.9 V (threshold voltage) and ~0.01 V (hold voltage) over 4 orders of current. And its off-resistance is measured as ~2.3 × 1011 Ω. The PZT-based gate configuration phase transition FDSOI MOSFET without an external resistor was fabricated by connecting the PZT-based TS to a baseline FDSOI MOSFET. It is confirmed that the fabricated external resistor-free phase transition FDSOI MOSFET can operate regardless of the aforementioned 1 μA of compliance current condition. This device has not only demonstrated the feature of ~4 mV/decade subthreshold slope at ~0.96 V of gate voltage, but it also has decreased the gate leakage current of the baseline FDSOI MOSFET by ~10 times at 0 V of gate voltage and ~320 times at 2 V of gate voltage.

A tunnel field-effect transistor with segmented channels (Seg-TFET) on a corrugated substrate is proposed. The Seg-TFET takes advantage of using three stripes and the selective contact configuration to define the direction of current, and thereby its device performance can be improved. Furthermore, the process flow of the Seg-TFET demonstrates a substantiation of the new device structure. Consequently, its current flow is simply defined by adjusting the appropriate contact configuration at metal-zero-level without any additional front-end-of-line process.

The negative capacitance (NC) of ferroelectric materials has paved the way for achieving sub-60-mV/decade switching feature in complementary metal-oxide-semiconductor (CMOS) field-effect transistors, by simply inserting a ferroelectric thin layer in the gate stack. However, in order to utilize the ferroelectric capacitor (as a breakthrough technique to overcome the Boltzmann limit of the device using thermionic emission process), the thickness of the ferroelectric layer should be scaled down to sub-10-nm for ease of integration with conventional CMOS logic devices. In this paper, we demonstrate an NC fin-shaped field-effect transistor (FinFET) with a 6-nm-thick HfZrO ferroelectric capacitor. The performance parameters of NC FinFET such as on-/off-state currents and subthreshold slope are compared with those of the conventional FinFET. Furthermore, a repetitive and reliable steep switching feature of the NC FinFET at various drain voltages is demonstrated.

The transient response of negative capacitance (NC) in an organic ferroelectric capacitor is experimentally investigated. To observe the transient response of the NC, a simple series network, consisting of an external series resistor and an organic ferroelectric capacitor, is built. The Landau coefficients of the organic ferroelectric capacitor were extracted from the measured polarization versus applied electric field data. A circuit level simulation was provided with the extracted parameters based on the Landau-Khalatnikov equation. To explore the impact of the RC time constant on the NC time duration in the RC series circuit, the external series resistor is altered as a tuning parameter. Also, the effect of various temperatures of the ferroelectric capacitor on the NC time duration is experimented. This paper demonstrates that either the external resistor or the ambient temperature can change the NC time duration in an organic ferroelectric capacitor.

The operating voltage of a nanoelectromechanical (NEM) relay can be scaled down significantly using negative capacitance (NC), which is a unique property of ferroelectric materials. It has been observed that a ferroelectric capacitor can amplify the internal voltage of a device (higher than the externally applied voltage) by means of the NC effect. In this simulation work, depending on the structural parameters of a ferroelectric capacitor and an NEM relay, an NC + NEM relay (in which the gate electrode of the NEM relay is connected in series to the ferroelectric capacitor) was investigated. As a result, a sub-0.5-V operating voltage is theoretically estimated. [ABSTRACT FROM AUTHOR]

With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal-oxide-semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance (gm) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs. [ABSTRACT FROM AUTHOR]

The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages (Vmin) required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared. [ABSTRACT FROM AUTHOR]