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Memristor devices are promising as high-density computing logic for non-high-speed normally off applications using heterogeneous technologies. This brief proposes a set-triggered-parallel-reset memristor logic (STPR-ML)-based on back-end-of-line-based bipolar-type memristor devices to reduce the area overhead and increase compatibility with standard and nonstandard CMOS processes. The proposed STPR-ML has two subsets: with and without nonvolatile storage capability. Two types of physical structures are also proposed for STPR-ML: 2-D and 3-D. A test chip using 2-D \HfOx memristor devices was fabricated using a CMOS process to confirm the functionality of the nand, nor, and xor gates used in STPR-ML. The proposed STPR-ML achieves a $2\sim 8\times$ reduction in area compared with CMOS logic gates with four or more inputs. [ABSTRACT FROM PUBLISHER]

The Resistive Random Access Memory (RRAM) is a new type of non-volatile memory based on the resistive memory device. Researchers are currently moving from resistive device development to memory circuit design and implementation, hoping to fabricate memory chips that can be deployed in the market in the near future. However, so far the low manufacturing yield is still a major issue. In this paper, we propose defect and fault models specific to RRAM, i.e., the Over-Forming (OF) defect and the Read-One-Disturb (R1D) fault. We then propose a March algorithm to cover these defects and faults in addition to the conventional RAM faults, which is called March C*. We also develop a novel squeeze-search scheme to identify the OF defect, which leads to the Stuck-At Fault (SAF). The proposed test algorithm is applied to a first-cut 4-Mb HfO2-based RRAM test chip. Results show that OF defects and R1D faults do exist in the RRAM chip. We also identify specific failure patterns from the test results, which are shown to be induced by multiple short defects between bit-lines. By identifying the defects and faults, designers and process engineers can improve the RRAM yield in a more cost-effective way. [ABSTRACT FROM AUTHOR]

The design of resistive RAM (ReRAM) faces two major challenges: 1) cell area versus write current requirements and 2) cell read current (ICELL) versus read disturbance. This paper proposes ReRAM macros using logic-process-based vertical parasitic-BJT (VPBJT) switches and a corresponding cell array (VPBJT-CA), resulting in a 4.5× macro density compared to conventional NMOS-switch ReRAM for given write current requirements. To overcome temperature-dependent fluctuations in the base-emitter voltage difference (VBE) of VPBJT, we propose a temperature-aware bitline (BL) voltage bias (VBL-R) (TABB) scheme to provide current-mode sensing with 4.7× larger ICELL and 1.6× faster read speeds. Test results of fabricated 0.18 µm 1 Mb and 65 nm 2 Mb VPBJT ReRAM macros confirm the efficacy of the temperature-aware VBL-R, resulting in sub-5-ns random read access times. [ABSTRACT FROM PUBLISHER]

ReRAM is a promising next-generation nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistance distribution and 2) the requirement of accurate bitline (BL) bias voltage control to prevent read disturbance. This study proposes two process-variation-tolerant schemes for current-mode read operation of ReRAM: parallel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes. These schemes are meant to improve the read speed and yield of ReRAM, while taking read disturbance into consideration. PSRC narrows the reference current distribution to achieve high read yield against resistance variation. PTADB achieves small fluctuations in BL bias voltage to prevent read disturbance, while providing rapid BL precharge speeds. This study fabricated a 4-Mb ReRAM macro to confirm the effectiveness of the proposed schemes for both SLC and MLC operations. The fastest sub-8-ns (7.2 ns) read-write random access time among megabit scaled embedded NVM macros has been demonstrated. [ABSTRACT FROM PUBLISHER]

In this paper, recent progress of binary metal–oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal–oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed. [ABSTRACT FROM PUBLISHER]

A new 3-D vertical bipolar junction transistor (BJT) resistive-switching memory (ReRAM) cell with complimentary metal–oxide–semiconductor-compatible process has been demonstrated and characterized. A new logic-compatible BJT is vertically formed underneath the resistive stacked film of \TiN/Ti/HfO2\/\TiN as a high-performance current driver and bit-cell selector. Using a shallow and tiny N-type lightly doped drain to be an emitter connects with ReRAM film as the bitline, a very thin and self-aligned P-pocket implant layer to be the wordline, and the N-well is the collector of the cells. As a result, the new 3-D ReRAM cell is very area saving and efficiently operated by the high-gain (\beta > \50) BJT at a low voltage of 2 V for reset and 1.5 V for set. By adapting the highly shrinkable 3-D BJT current driver in ReRAM, the ReRAM is fully decoupled with the gate length and oxide thickness of logic metal–oxide–semiconductor field-effect transistors; furthermore, it can easily be scaled down to \4F^2 under the lithographic limitation of defining ReRAM film with \F^2 area. [ABSTRACT FROM PUBLISHER]

A 3-D resistive random access memory potentially offers lowest cost per bit and highest bit density memory architecture without the use of transistors in the array. However, without the use of selectors attached to each cell in the array, sneak currents are a key concern, causing signal errors, and excess power dissipation. A nonlinear LRS helps to resolve the issue, but to date, reported LRS nonlinearity values are still insufficient. In this letter, we describe how a 1TNR architecture may be designed and operated to take more advantage of the HRS rather than the LRS nonlinearity, allowing sneak currents to be minimized during write operations, without the use of cell selectors. We show how a recently studied TaOx/HfOx device with highly nonlinear (\sim10^5) HRS can be used in block sizes up to 256 Mb without selectors in a 1T8R architecture with a 25% current margin. [ABSTRACT FROM PUBLISHER]

A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high-k metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/HfO2/SiO2/Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high-K gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products. [ABSTRACT FROM AUTHOR]

Editor's note:Especially for microcontroller and mobile applications, embedded nonvolatile memory is an important technology offering to reduce power and provide local persistent storage. This article describes a new resistive RAM device with fast write operation to improve the speed of embedded nonvolatile memories.—Leland Chang, IBM T.J. Watson Research Center [ABSTRACT FROM PUBLISHER]