1. 6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology
- Author
-
Chen Huan-Sheng, Mohammed Abdul-Latif, Qaiser Nehal, Chung-Hsien Tsai, Yuyun Chang, Tamer Ali, Chun-Cheng Liu, Henry Park, Ramy Yousry, Kevin Tan, Mohammad Elbadry, Yu-Ming Ying, Gandara Miguel Francisco, Yi-Chieh Huang, Yuan-Hao Tung, E-Hung Chen, Po-Shuan Weng, and Kun-Hung Tsai
- Subjects
010302 applied physics ,Computer science ,business.industry ,020208 electrical & electronic engineering ,SerDes ,Equalization (audio) ,Electrical engineering ,02 engineering and technology ,01 natural sciences ,Compensation (engineering) ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Insertion loss ,Transceiver ,business ,Throughput (business) ,Communication channel ,Jitter - Abstract
Explosive growth in mega-scale data centers drives switch chips to transition from 12.8Tb/s to 51.2Tb/s throughput. A 51.2Tb/s switch requires 512 lanes operating at 106Gb/s PAM-4. Such a massive integration of electrical SERDES is restrained by three factors: First, a large switch die size (>25×25mm2) substantially lowers yield and prohibitively increases cost. Second, a large-size package suffers more than 10dB insertion loss from combined TX and RX traces. Considering practical equalization capabilities of a long-reach system (>30dB), 10dB package loss significantly limits the available channel reach. Lastly, channel reflection and cross-talk are excessive at 100Gb/s, which puts a ceiling on attainable BER.
- Published
- 2020