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This paper aims to study the estimation of RF imperfections, i.e., frequency independent (FI) IQ imbalance (IQI) and DC IQ offset. Based on the feedback envelope detector signal, a low-complexity scheme, i.e., the least mean square (LMS) adaptive algorithm, is proposed to estimate the IQI, DC offset, and non-linear parameters. The following steps are designed for the parameters estimation. First, the matrix-form RF impairment model and the non-linear envelope detector model are proposed. Next, the steepest gradient LMS algorithms are developed to minimize the error cost function and acquire the impairment and non-linear parameters. Then, the FI IQI and DC offset values can be estimated by the inversion of parameters. Finally, we have utilized Agilent instruments and the envelope detector module to confirm that the proposed low-complexity algorithms can provide the reliable RF imperfection parameters estimation.

The frequency modulation continuous wave (FMCW) radar algorithms are proposed for the software-defined-radio (SDR) platform to verify the range and speed estimation of the target. The measurement platform can provide the RF imperfection and the multipath channel effects to test the FMCW algorithms. Based on the measurement results via SDR instruments and RF components, it is confirmed that the FMCW algorithm can provide the reliable performance over the RF and channel effect environments.

The main objective of developing an image watermarking technique is to satisfy both imperceptibility and robustness requirements. To achieve this objective, a hybrid image watermarking scheme based on discrete wavelet transform and singular value decomposition is proposed in this paper. In our approach, the edge information of an image is used to embed the watermark. In addition, we apply the particle swarm optimization algorithm to search the proper value of scaling factor which is used to determine the watermark strength. Experimental results are provided to illustrate the proposed approach is able to withstand a variety of image processing attacks.

Three dimensional (3D) stacking technology has been purposed to meet miniaturization trend, high performance, and multi-function electronic products. Chip stacking with through silicon via (TSV) and high density lead free interconnection are believed to realize 3D stacking package. Due to the narrow dispensing request for multi-chip connection, non-conductive paste (NCP) is one of the solutions to replace capillary underfill. Nevertheless, voidless control and wettability are two critical challenges for large dies size flip chip ball grid array (FCBGA) 3D package. In this paper, fine pitch u-bump for large die size 3D stacking using thermal compression bonding (TCB) with NCP is demonstrated. In order to achieve voidless, bonding parameter was studies in different pre-heat time. The effect of bonding conditions such as force, temperature, and time on wettability has been performed. The results showed that longer pre-heat time could accomplish voidless. The u-bump wettability exhibited relationship between TCB parameters and characteristics of NCP. Finally, reliability test was tested for NCP properties discussion.

High density interconnection is a key technology to realize the miniaturization trend in Integrated Circuit (IC) industry, and to reduce power consumption for next generation mobile devices. In advanced three-dimensional (3D) package, fine pitch pillar bump is deployed not only to fulfill ever-growing I/O density requirement, but also provides better electrical performance than that of traditionally solder bump [1]. Meanwhile, to maximize die area utilization, die sizes of top and bottom die are generally kept as close as possible, leaving stringent spacing for underfilling, and makes fillet width control and dispense space two great challenges for capillary underfill (CUF). In this paper, test vehicle of fine pitch micro-bump interconnection was achieved by thermal compression bonding (TCB) with Non-Conductive Paste (NCP). This paper addresses development of TCB process with NCP material by different TCB condition and NCP properties to show the correlation between TCB process parameter and NCP material. In order to achieve spherical bump shape, NCP gel time was studied in different bump melting time. Fillet width was studied to control the exceeding area around chip. Void was also studied for TCB parameter adjusting. Finally, reliability test was tested for NCP properties discussion.

Since 3D-IC becomes popular nowadays, solder micro-bumps plays an important role to develop TSV technology. This study verifies solder micro-bump efficiency via cracking as index. The micro-bump cracking is observed at the interface of intermetallic compound (IMC) layer after Si chip and Si carrier bonding. It was found that P-rich Ni layer will perform weaker and brittle solder joint by means of EDS. Figure 1 shows the cross section schematic drawing as 3D chip stacking for a Si chip and a Si carrier. The solder micro-bumps and under bump metallurgy (UBM) pads are fabricated on the Si chip and the top side of Si carrier respectively. The TSVs in Si carrier functions as interconnects. After flip chip assembled Si chip and Si carrier, the whole assembly is joint onto a bismaleimide triazine (BT) substrate with redistribution layer and solder joints through by bottom of Si carrier. In this study, the Si carrier was patterned with the diameter and depth by 50um and 120um respectively at room temperature with BOSCH process. The smoother scallop was achieved below 150nm. Excellent passivation step coverage for 39% ≃ 50% from via top to bottom side was also obtained. TSV formation processed by electroplating Cu and X-ray result shows void free in TSV. After TSV formation, the electrical nickel and immersion gold (ENIG) was used for the UBM. The total thickness of 50μm Ni/Cu and Sn/Ag solder micro bumps were fabricated by electroplating on top of Si chip.

In order to uniformly expose Cu via, TSV wafer thinning becomes much critical contrary to conventional process. The complete wafer thinning process is expected composed of not only grinding, but also handling. This study develops advance wafer thinning process from temporary carrier bonding to carrier de-bonding that also includes grinding and backside processes. In this case, the bonded wafer thinning target is 100um for backside process. Void-free carrier bonding and bump after backside processes could be addressed. The carrier de-bonding process performs no wafer crack and residue. Moreover, whole wafer thinning process never suffers from Cu scratching. In this study, Under Bump Metallization (UBM) and bump were laid on the backside of Through Silicon Via (TSV) wafer. The wafers composed of various surface structures were carried out to bond glass carrier. The structure difference above came from various designs on UBM and bump. These designs may be backside UBM only, Redistribution Layer (RDL) + UBM, and even bumps on UBM. All the wafers were prepared through passivation patterning, sputtering, solder printing, plating and reflow. Among these processes, the wafer preparation also requires necessary passivation curing, sputtering for Cu seed deposition, and electroplating to form solder bump.

The submodeling technique is a powerful analysis tool. The method promotes more accurate analysis and also helps enhance productivity. It has been shown that by using displacement-force cut boundary condition method, it can be made even more versatile. The local stress phenomena of the solder microbump have been solved with this approach to demonstrate the concept. From the simulation model, it is known that the ENIG pad thickness has an effect on the aluminium pad stress in the silicon chip. This is important as the shear stress will damage the pad and circuitry on the chip. Previously this is not reported in other literatures as there is no strain gage available that can measure such a small dimension.

High density three dimensional (3D) interconnects formed by high aspect ratio through silicon vias (TSVs) and fine pitch solder microbumps are presented in this paper. The aspect ratio of the TSV is larger than 10 and filled with Cu without voids; there are electrical nickel and immersion gold (ENIG) pads on top of the TSV as under bump metallurgy (UBM) layer. On the Si chip, Cu/Sn solder microbumps with 16µm in diameter and 25µm in pitch are fabricated. After singulating the Si chip and the Si carrier, there are joined together and the interconnection is formed between them through the solder micro bumps and the TSV.

In this paper, frequency selective surface with random distributed resistance patches (RRDFSS) has been proposed and the effects of occupancy factor, distribution and surface resistance have been studied numerically with HFSS. The results show that occupancy factor, distribution and aggregative quantities have notable effects on absorbing properties of the proposed RRDFSS and absorbing performances could be improved greatly in wide band while using suitable surface resistance. RRDFSS can be used in composite absorbing material and be easily realized.