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The existing commutative encryption and watermarking (CEW) methods based on feature invariants can achieve both the robustness of the watermarking algorithm and the security of the encryption algorithm. However, they are only applicable to the raster data such as images, videos, etc. In particular, the organization structure and storage structure of vector map have not been considered in these methods. Therefore, they cannot be used for vector map. This paper derives two feature invariants to solve this problem, which are the sum of inner angles and the storage direction of two adjacent objects according to the inherent characteristics of vector map. Based on these two feature invariants, a new CEW method is proposed in this paper, which includes the feature invariants based watermarking algorithm and the perceptual stream cipher based encryption algorithm on coordinates. Since the coordinate values used in encryption and the feature invariants used in watermarking are independent of each other, the commutativity is achieved for the proposed CEW method. The experiments are given to verify that the proposed CEW method can achieve the commutativity between encryption and watermarking without deteriorating accuracy of data. Besides, it has been verified that the proposed method is more robust to rotate, scaling, translation, and projection transformation compared with the existing CEW methods and has high security. The proposed algorithm has good scalability of encryption, and arbitrary encryption methods based on encrypting the coordinate values can be applied without affecting the extracted feature invariants.

In this work, the influence of JFET region width on 1200V SiC MOSFET’s avalanche reliability is studied with unclamped inductive switching (UIS) test. It is revealed that the highest avalanche capability is achieved with a JFET region width of 4μm. As presented in TCAD silmulation, locallized heat accumulation arising from high channel current density proves to be the failure mechanism. Furthermore, the balance between device performance and reliability with different JFET region width design is discussed by considering the device’s figure of merits (FOM).

Silicon carbide metal oxide semiconductor field effect transistor (SiC-MOSFET) power devices have the advantage in high-power and high-frequency applications over silicon insulated gate bipolar transistor (Si-IGBT), due to the superior properties of fast switching speed and low switching loss. In order to meet the requirements of the applications of higher power and higher switching frequency for power devices, the power module based high power density integration becomes the mainstream trend of the development of SiC devices, but the highly integration also increase the concern about the coupling failure by near-filed radiated emission due to fast switching performance of SiC power module. For this problem, in this paper a buck converter based on SiC power module with 62mm standard outline has been built, the near-filed radiated emission of the module has been investigated, and finally, the spectrum and spatial distribution of near-field radiated emission electromagnetic interference (EMI) of the module have been disclosed.

The short-circuit capability of Silicon Carbide (SiC) MOSFETs is much worse than the Si IGBT counterparts. There are two kinds of commercially available SiC MOSFET devices (trench MOSFETs and planar MOSFETs), and their short-circuit capability is not exactly the same. At present, there is a lack of comparative study on the short-circuit capability of these two kinds of devices. To solve this problem, this paper carries out a comparative study of the short-circuit capability of the two devices. Experiment results show that in the case of short circuit tests, it takes more time for planar MOSFETs to reach their peak currents because of their lower channel mobility and higher trap density. The DC voltage has little impact on the peak current which is mainly affected by the gate voltage. At the low DC voltage, such as 400V, 500V and 600V, planar MOSFETs have better short-circuit indexes no matter the short circuit withstand time (SCWT) or the short-circuit energy. However, at 800V DC voltage, trench MOSFETs have a better performance in short-circuit tests. Considering the factor of different areas, the short-circuit energy density of trench MOSFETs is higher than that of planar devices, especially under the condition of 800V high DC voltage.

In this paper, the single pulse avalanche robustness of 1.2kV 4H-SiC Junction Barrier Schottky (JBS) diode with different designs is investigated. The unclamped inductive switching (UIS) tests are carried out to obtain avalanche energy capability. It is found that the JBS diode with the narrower spacing of the P+ region exhibits higher avalanche robustness (around 5%~8.5% improvement in this paper). Simulation analysis reveals that there is a current crowding in avalanche mode, which will be more severe with the increasing spacing of P+ regions. The localized current crowding and unbalanced current distribution can lead to a reduced effective power dissipation area and a higher junction temperature, which is adverse for the device avalanche robustness. Therefore, in the process of device design and optimization, avalanche robustness can be improved by alleviating the issue of the current crowding, which is beneficial to enhance the product's competitiveness and expand the application of the device.

SiC MOSFET Body diodes are expected to compete against SiC schottky barrier diodes (SBD) in high power applications. To investigate the surge capability of the body diodes in commercial SiC MOSFETs, single pulse and repetitive surge current tests are processed on the DUTs. In single pulse surge current test, the DUTs are stressed to failure. Compared with the body diodes in SiC trench-gate MOSFETs, the body diodes in SiC planar-gate MOSFETs tend to show better surge capability at all rated current levels. On the other hand, in repetitive surge current test, the degradation of electrical parameters is observed after hundreds of pulse cycles. The degradation mechanism of bipolar degradation and oxide layer degradation has been analyzed.

In this paper, the typical V-T (avalanche voltage v.s. temperature) model is used to estimate the maximum junction temperature (Tj) during the single pulse unclamped inductive switching (UIS) tests. Experimental results show that the maximum T j at failure will reach 670$\sim$890K, which is less than the melting point of aluminum (933K). The typical parasitic BJT turn-on model with practical chip layout is used to analyze the possible failure mechanism. Different T j calculation models are compared to show the accuracy of the V-T model. The UIS tests at different ambient temperatures are conducted to show the device failure is independent on the fixed critical temperature. Distribution of failure spots of decapsulated failed DUTs is observed under the optical microscope.

Although the body diode of SiC MOSFET has excellent surge capability, the reliability issues about commercial SiC MOSFET under repetitive surge current stress of body diode haven’t been studied thoroughly. In this work, repetitive surge current stress is applied to the body diode of commercial SiC trench MOSFET, and the surge tests are conducted under different gate biases and ambient temperatures. It is found that no bipolar degradation occurs in the body diode but degradation phenomena of gate oxide and package are observed in devices under tests (DUTs). At room temperature, the threshold voltage (V TH ) related to gate oxide degradation degrades more seriously at a negative gate bias of -5V than at OV. At OV gate bias, gate oxide and package degenerate more severely at $125^{\circ}{C}$ than at $25^{\circ}{C}$. The evolution of on-state resistance $(R_{DSON})$ during the tests is influenced by the competitive mechanism between gate oxide degradation and package degradation. As a result, gate oxide degradation causes R DSON to reduce while package degradation makes R DSON rise. Meanwhile, the competitive mechanism is deeply influenced by the gate bias voltage and ambient temperature. The failure analysis shows that all DUTs fail with gate and source terminal shorted, which is mainly attributed to high junction temperature.

In this work, a novel structure design concept (plasma spreading layers, PSL) is introduced into the SiC MPS diode which can significantly improve the surge current capability. The plasma spreading layers can spread bipolar current from the wide P+ region to the other parts and alleviate unbalanced current distribution in the device during the surge conditions, thus, device’s surge capability can be improved. The proposed structure can achieve a better tradeoff relation between the device forward voltage drop at nominal current and surge capability. 1.2kV SiC MPS diodes with two types of plasma spreading layers are designed and fabricated in this work, their forward characteristics and surge current capability are compared to traditional stripe cell design and hexagonal cell design. The results show that a 20% increase of maximum allowed energy is achieved by the new structure design comparing to the traditional hexagonal design, which results in a 10% improvement of the surge current capability.

In this work, the avalanche capability of 1. 2kV 4H-SiC JBS and MPS diodes in single-pulse Unclamped Inductive Switching (UIS) tests is investigated and compared. It is found that the width (W) of wide P+ region has great effects on the device avalanche capability. The experimental results show that the avalanche capability gets increased with W when W=3-8μm, then declines when W exceeds 8μm. TCAD Simulation is carried out to study the device behavior in the avalanche mode. It is revealed that the electric field under avalanche condition is crowded at the corners of the pn junction, which leads to avalanche current crowding and unbalanced current distribution issues. Current non-uniformity coefficient (k) is used to characterize the severity of the current unbalance. Simulation results indicate that k declines with W when W=3-8μm, then get increased when W exceeds 8μm, which is consistent with the optimal design in the experimental results. Based on the study, an optimal MPS diode structure design with W=8μm is obtained and an avalanche capability improvement of 9%~ 28% is achieved by the experiments.

In this work, repetitive surge current stress is applied on the body diode of SiC MOSFET to examine the degradation of the body diode. The repetitive surge tests are conducted at $25^{\circ}\mathrm{C}$ and $125^{\circ}\mathrm{C}$. Static characteristics and reverse recovery transient of the DUT’s body diode are measured after each 50 surge pulses to monitor the electrical parameter variations. Increase in body diode resistance and decrease in reverse recovery charge are observed after hundreds of stress cycles. Meanwhile, the transfer curve and I-V curve of the DUT are measured. No obvious shift of threshold voltage is observed, indicating no gate oxide degradation occurred. Based on the analysis of the resistance components of body diode and MOSFET, bipolar degradation is demonstrated to be the mechanism leading to the degradation.

In this paper, simulation, modeling and experimental studies of 1.2kV/2A 4H-SiC MPS diodes are conducted. First, design considerations for MPS cells and JBS cells are presented. As the pn junction turn-on voltage ( $\boldsymbol{V_{turn}}$ ) has a significant impact on the surge current capability of MPS diodes, a lower $\boldsymbol{V_{turn}}$ is desirable. Both simulation and modeling results show that there is a trade-off between the forward voltage drop at nominal current ( $\boldsymbol{V_{F}}$ ) and the $\boldsymbol{V_{turn}}$ for the MPS cell design. MPS diodes with different designs are fabricated and their experimental results are compared. It is demonstrated that a wider p+ region accompanied with a larger p+ spacing design can get a better trade-off between the $\boldsymbol{V_{F}}$ and $\boldsymbol{V_{turn}}$ . Moreover, the surge current capability can be improved by 17% when the p+ region width is increased from $8\boldsymbol{\mu} \mathbf{m}$ to $20\boldsymbol{\mu} \mathbf{m}$ .

In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) tests are investigated and compared with that of Si IGBT. The experimental results show that the avalanche energy of SiC MOSFET is only 30% that of Si IGBT due to the much smaller chip size (1/7 that of Si IGBT). To improve the avalanche capability of SiC MOSFET, the failure mechanism is analyzed. First, junction temperature in the UIS test is calculated through modeling. The maximum junction temperatures reach 650 K and 490 K in SiC MOSFET and Si IGBT, respectively. Then, BJT latch-up probability is analyzed with an analytical model. It is demonstrated that BJT latch-up can be triggered at the failure temperature (650 K) in SiC MOSFET, whereas it can be eliminated in Si IGBT due to the much deeper P+ body structure. Based on the analyses, the device structure optimization is proposed for SiC MOSFET to prevent the BJT latch-up and enable avalanche capability improvement.

This paper presents a high-efficiency multiple-string linear LED driver with genetic algorithm (GA) based configuration. Compared with traditional LED drivers, linear LED drivers have advantages of high efficiency, simple structure, low cost and long life-time. To achieve the high efficiency target for multiple-string linear LED driver, the configuration of LED number in each string is a great challenge. In this paper, a method based on genetic algorithm is proposed for the string LED number (i.e. string voltage) optimization. The system efficiency analysis with input voltage and LED current is introduced. And, the GA design flowchart and interface are provided. With the developed GA algorithm code, the optimal voltage for each string can be calculated. To validate the methodology, simulations are carried out to compare the GA based configuration and other four references. The results show that the GA based configuration can achieve the highest efficiency of 96%, which is >8% higher than the other configurations under the same condition.

This paper presents an instantaneous pulse power compensator (IPPC) concept to achieve ultra-high density with zero voltage ripple and zero dc-link capacitor for high-power-density single-phase inverter application. Compared with traditional 2ndorder method with various power decoupling topologies, IPPC proposed a totally new theoretical analysis from a pulse-power point of view. For dc-link voltage ripple evaluation, traditional theoretical analysis is not suitable for small-capacitance power decoupling applications, however, pulse power analysis can be applied in the whole range. From a view of state-of-the-art on power decoupling methods, a comparison figure with voltage ripple and dc-link capacitance is given to show the limitation of traditional power decoupling method and improvement of IPPC method on minimizing dc-link capacitance. One case study is presented with full-bridge topology with simulation results. Furthermore, one Silicon Carbide (SiC) based inverter and the IPPC based circuit are built. Experimental results verify the proposed idea very well.

This paper presents a high-temperature implanted 4H-SiC JBS diode with improved surge capability. The fabrication of the P+ region is implemented with 500 °C implantation. It was found that Ti can form ohmic contact on high temperature implanted P+ region without any additional annealing. This could simplify the ohmic contact process for MPS fabrication. In this work, a wide transition P+ region between cell and termination is designed, which can alleviate snapback phenomenon and improve the surge capability.

In this work, avalanche ruggedness and failure mechanisms of 900V SiC MOSFETs under single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si counterparts. It was found in this work that, due to the higher resistance to BJT latch-up, only uniform heating related device temperature limit failure exists in SiC MOSFETs. Experimental results also show that, SiC MOSFETs have 9 times higher avalanche energy per area and 50% higher avalanche current than Si MOSFETs in low inductance/short pulse condition. In large inductance/long pulse condition, SiC MOSFETs have shorter avalanche duration, lower avalanche current and only similar avalanche energy per area compared to Si, due to the much smaller (15∗) chip size, thinner active layer thickness and higher power density.

In this paper, design, fabrication and experimental analysis of a novel 4H-SiC pinched barrier rectifier (PBR) are presented. The operation mechanism of the pinched barrier is analyzed by numerical simulation and energy band diagrams. PN junction depth (X j ) and spacing (S) parameters in the diode structure are carefully designed to achieve a prototype optimal structure, and both forward and reverse characteristics are compared with those of JBS diodes by experimental results. It is demonstrated that, only by simply adjusting the PN junction depth and spacing parameters, the pinched barrier diode can obtain relatively optimal performance close to that of JBS diodes. The addition of channel doping concentration (Nch) consideration for the structure design can achieve further improvements and superior performances than JBS diodes. In comparison with the optimum JBS diode design (S=1.2pm), for an on-set voltage control of 0.8V, PBR diode with optimum design sets of S and Nch can achieve a wider trade-off window (S≤0.8pm) between the device forward and reverse performances. Furthermore, PBR diode can achieve superior performance with lower forward voltage drop (1.3V) than JBS diode (1.6V) for the same reverse blocking capability (∼1600V). The performance limit of PBR diode is also explored in this paper. For a minimum limit on-set voltage control of 0.6 V, a lowest voltage drop of 1.1V as well as a wide design window can be achieved.

This paper is to study the control scheme for neutral-point-clamping three-level (NPC-3L) inverters fed dual three-phase permanent magnet synchronous motor (PMSM) drives based on vector space decomposition (VSD). The key is to propose a novel VSD based space vector modulation (SVM) strategy for the dual-three phase drives. The torque of the PMSM drive is controlled by voltage components on α-β plane while the current harmonics are suppressed by voltage components on x - y plane of the VSD-SVM. The upper and lower capacitor voltages are balanced well in DC link. Based on the proposed VSD-SVM strategy, a simple control scheme is presented for the dual three-phase PMSM drives. The principles of the proposed modulation strategy and control scheme are described in detail. The experiments are carried on a laboratory prototype to verify that the proposed VSD-SVM based control scheme can provide both good steady-state and dynamic performance for the dual three-phase PMSM drives.

In this paper, an innovative series-parallel hybrid circuit topology with silicon carbide MOSFETs is presented and analyzed. This topology consists of two uniform parts in parallel and each of the parts includes three sub-parts in series. The sub-part contains three primary parts connected in string where each of these primary parts has a parallel of two SiC MOSFETs. These 36 SiC devices are divided into six sub-parts, which are driven by a common driving signal. A 10kV/200A SiC MOSFETs module is fabricated based on this hybrid topology with thirty-six 1200V/50A SiC MOSFET dies. The dynamic switching behavior of the module is analyzed and double-pulse tests have been performed at 5400V/200A. The results show a good switching speed of 100ns in turn-on process and 200ns in turn-off process.

In this paper, a current source driver is presented for IGBT modules. For conventional voltage source gate driver, the influence of the gate drive resistance on switching performances is investigated for IGBT modules with SiC-Schottky freewheeling diodes. The influence on turn-off switching losses is marginal while a reduction by a factor of 3 can be achieved for turn-on switching losses when the gate drive resistance reduced from 40Ω to 10Ω. The current source driver can achieve a turn-on loss reduction by a factor of 14 when compared to the conventional gate driver with 40Ω gate drive resistance, without a large Irr due to the SiC-Schottky freewheeling diode. Experimental results are presented to show the IGBT switching performance with this proposed fast gate driver.

In this paper, a new rectifier structure in silicon carbide (SiC) is presented for the first time. The proposed structure involves neither Schottky contact nor minor carrier injection via P-N junction. With adjacent P+ areas placed sufficiently close, pinched barrier is formed for rectifier purpose. Numerical simulations are carried out to verify its function, and optimize its performance. Based on the simulation results, a good trade-off can be achieved between forward drop and reverse leakage, provided that this new structure offers flexibility of controlling onset voltage by adjusting channel parameters continuously.

It is important how to tackle the crucial problems of the resource allocation optimization for High-tech industry to improve its input-output efficiency. In order to solve it, the input-output efficiency assessment index system of High-tech industry is constructed and a novel model based on data envelopment analysis (DEA) and grey correlation degree analysis is designed to find its key factors to influence the input-output efficiency change. The effectiveness indexes of the High-tech industries of all provinces in China in two consecutive years are calculated by DEA. The changes of the assessment indexes and the effectiveness indexes between two years are calculated. The grey correlations between them are obtained by grey correlation analysis method. The key influence factors of the High-tech industry are the indexes with bigger grey correlations including Patent Applications Received, Technology invest funds and Gross Industrial Output Value at Current prices, obtained from the data of the High-tech industry in 2007–2008 in China. It is confirmed that the input-output efficiency is enhanced sensitively when the key factors are improved. Finally, some advices are provided to increase the input-output efficiency of the High-tech industry based on the key influence factors.

This paper introduces functions and features of the MPEG-4 streaming media, combine its media properties with Microsoft's digital rights management component WMRM, design and implemented the digital rights management system based on MPEG-4 streaming media, this system possessed a higher Security and stability, it has a high application value on development of streaming media in e-commerce.

Traffic Grooming in optical networks is one if the most important and hot problems in the area of optical network. In the static traffic grooming problem, we introduce the concept of QoS (Quality of Service); in order to minimize the network cost utilization rate and to maximize the QoS degree of the users at the same time, we apply the intelligent computing algorithm -QIA( the quantum-based Immune Algorithm) to the framework to solve the problem.

A method for the traffic signal recognition of his color space and bp neural network algorithm. First convert the traffic signal images from RGB space to HSI space, and then extracted H Component characteristics from HSI space in the traffic signal images, according to the Component histogram, determine the signal color. Finally, BP neural network is applied for the traffic signal lights recognition. It's demonstrated by practice that BP neural network can be used for fast and efficient recognition of traffic signal with high accuracy and practical value.

Digital Rights Management (DRM) technology play a very important role in solving the problems of digital copyright, it includes streaming media servers, authentication servers, web servers, file servers, database servers several parts. The paper mainly discusses the design and implementation of authentication server.

Service delivery is vital for the success of IMS network in telecom. Current approaches focus on combining existing services into a new composite service. However, there are further requirements for enabling telecom operator to dynamically personalize, manage and enhance user services at runtime outside of the application logic itself. We observe the need and present the SCL (service control layer), an adaptive middleware between the service and network plane in IMS. By using aspect oriented technology, the SCL provide operators with the requisite fine-grained control over service delivery.

With the gradual adoption of Parlay and Parlay-X technologies in the telecom industry, many third party value-added applications have been developed and deployed in telecom networks. Usually third party service providers utilize telecom operator's charging and billing infrastructure to bill service users. Despite the lack of trust between operators and third party service providers, little has been done regarding the management of third party application charging in the operator domain. In this paper, we present an idea of charging validation in service delivery platform to ensure correct execution and charging of complex third party value-added applications by checking service charging records. Charging template and service process model are used to achieve automatic validation