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International audience; Exploiting the analog properties of RRAM cells for learning is a compelling approach, but which raises important challenges in terms of CMOS overhead, impact of device imperfections and device endurance. In this work, we investigate a learning-capable architecture, based on the concept of Binarized Neural Networks, which addresses these three issues. It exploits the analog properties of the weak RESET in hafnium-oxide RRAM cells, but uses exclusively compact and low power digital CMOS. This approach requires no refresh process, is more robust to device imperfections than more conventional analog approaches, and we show that due to the reliance on weak RESETs, the devices show outstanding endurance that can withstand multiple learning processes.

Recently it has been demonstrated that binary neural network (BNNs) can achieve satisfying accuracy on various databases with the significant reduction of computation and memory resources [1], which provides a promising way for on-chip implementation of deep neural networks (DNNs). To storage synaptic weights, the SRAM is traditionally utilized in the CMOS based ASIC designs for hardware acceleration implementation of DNNs. However, it has been proved to be extremely area- and power-inefficiency due to its large cell area $( >200 \mathrm {F}^{2})$and volatility, respectively. To overcome these issues, the emerging non-volatile spin transfer torque magnetoresistive RAM (STT-MRAM) with small cell area $(< 10 \mathrm {F}^{2})$recently has been proposed to implement synaptic weights instead of SRAM [2]. Moreover, STT-MRAM has been demonstrated at Gb chip-level by industry [3]. In this paper, a single-layer binary perceptron (BP) is proposed for image recognition, which can be implemented via the pseudo-crossbar array of 1T-1MTJ (STT-MRAM cell) as shown in Fig. 1(a). With the learning rule in [1], such BP was trained in an off-line manner on a set of $\mathrm {N}=30$patterns, including three stylized letters (‘z’, ‘v’, ‘n’) as shown in Fig. 1(b) [4], which also was used for testing. To classify these three stylized letters, we design a winnertakes-all (WTA) circuit as shown in Fig. 1(c), which is used as the peripheral inference circuit of proposed BP. Based on a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit, the functionality of the proposed BP and WTA circuit have been demonstrated as shown in Fig. 2(a). Additionally, we also investigate the impact of TMR and device variations on the recognition rate as shown in Fig. 2(b)and Fig. 2(c), respectively. In summary, a STT-MRAM based binary synaptic array with a WTA circuit has been proposed for image recognition, which provides a promising solution for hardware implementation of BNNs on-chip.

The input-referred offset of a dynamic latch-based sense amplifier for resistive memories is extensively analyzed. This circuit is modeled using both small and large signal analysis, in order to evaluate mismatch effects and to support design robustness to process variations. Effect of various design parameters on offset are studied and reported. It is shown that load capacitance has a profound effect on the sense amplifier offset. Design optimization is then proposed thanks to this analysis, resulting to an input-referred offset (simply called offset in the rest of the paper) down to about 200 Ohms for one sigma variation with 20fF applied load capacitance.

Spintronic devices have the potential to lower the power consumption of computing architectures such as Arithmetic Logic Units (ALUs). However, the existing spintronic ALUs still rely on charge current, which doesn't allow exploiting the spin devices properties for information transmission. All Spin Logic (ASL) devices based circuits have the potential to further improve these circuits and systems since they rely on pure spin current. Indeed, it has been shown that ASL-based circuits can be reconfigured through modification of the injection current polarity and the states of the control terminals. In this paper, for the first time, we propose two one-bit ALUs implemented using ASL devices. The first ALU is designed by the assembly of logic circuits while the second ALU is synthesized using majority gate method. SPICE simulations have been carried out with 40 nm diameter MTJ and the ALUs are compared regarding energy consumption and the number of ASL devices metrics. Comparison results show that the ALU designed using a majority gate based synthesis method consumes more energy than the logic circuit based ALU (1.917 vs. 0.486 nJ) but is easier to control.

Benefitting from its non-volatility, low power, high speed, nearly infinite endurance, good scalability and great CMOS compatibility, magnetic tunnel junction (MTJ) embedded in conventional CMOS logic circuits has been proposed as one potentially powerful solution to introduce non-volatility in today's programmable logic circuits, which is envisioned to extend the Moore's law [1].

An auto-correlation matrix memory (ACMM) system continuously computes the degree to which a presented input is novel or anomalous relative to past examples. Here we demonstrate that such a filter can be efficiently implemented with memristive nanodevices and accompanying CMOS circuitry. Complete (a full crossbar) and incomplete (an array of memristive devices) variants of the proposed nanofabric are electrically detailed and subsequently simulated on a simple sparse input image test meant to gauge the system's responses to transitions. Both systems demonstrate active novelty filtering with a small level of false positives in the presence of noise, but only the complete system reports all transitions successfully (avoids false negative too). While the system is robust to a noisy channel, degradation towards false positives is more likely when nanodevice variability is taken into account as well. In addition to novelty filtering, the proposed system may be a useful building block for larger reservoir or recurrent on-chip learning systems.

Memristive nanodevices offer new frontiers for computing systems that unite arithmetic and memory operations on-chip. Here, we explore the integration of electrochemical metallization cell (ECM) nanodevices with tunable filamentary switching in nanoscale learning systems. Such devices offer a natural transition between short-term plasticity (STP) and long-term plasticity (LTP). In this work, we show that this property can be exploited to efficiently solve noisy classification tasks. A single crossbar learning scheme is first introduced and evaluated. Perfect classification is possible only for simple input patterns, within critical timing parameters, and when device variability is weak. To overcome these limitations, a dual-crossbar learning system partly inspired by the extreme learning machine (ELM) approach is then introduced. This approach outperforms a conventional ELM-inspired system when the first layer is imprinted before training and testing, and especially so when variability in device timing evolution is considered: variability is therefore transformed from an issue to a feature. In attempting to classify the MNIST database under the same conditions, conventional ELM obtains 84% classification, the imprinted, uniform device system obtains 88% classification, and the imprinted, variable device system reaches 92% classification. We discuss benefits and drawbacks of both systems in terms of energy, complexity, area imprint, and speed. All these results highlight that tuning and exploiting intrinsic device timing parameters may be of central interest to future bio-inspired approximate computing systems.

Spin transfer torque magnetic random access memory (STT-MRAM) has been widely considered as one of the most promising candidates for the next-generation nonvolatile memory technologies, thanks to its attractive features, including high density, high speed, low power and high endurance etc. However, our investigation demonstrates that read disturbance may become a big reliability issue of STT-MRAM, since read and write currents share the same path. As technology scales down to nanoscale nodes, this read disturbance issue becomes more serious and may turn into be a critical reliability barrier for STT-MRAM commercialization, because the difference between the read and write currents decreases. In this paper, we propose a circuit to detect the read disturbance by exploiting its typical features, i.e., (a) the resistance (read current) of the memory cell will have a sudden change if read disturbance occurs; (b) only one-direction of read disturbance can occur during normal read operations. Based on the detection results, the correct data can be restored back into the memory cells after read disturbance or system-level algorithms can be employed to correct the read disturbance fault.

Spin transfer torque magnetic random access memory (STT-MRAM) has emerged as a potential candidate for the next-generation universal memory technology. However, many challenges still exist that block its commercialization and application. One of the main challenges is the reliability concerns, especially as technology scales down to nanometer nodes. For example, the intrinsic stochastic switching characteristics and asymmetry of the STT driven magnetic tunnel junction (MTJ), as well as the process, voltage and temperature (PVT) variations of the manufacturing process. Generally, there exists a technical gap between the device-level designers and system-level circuit or system designers for the STT-MRAM optimizations. To our knowledge, no efficient evaluation tools have been proposed to provide an effective link between them until now. In this paper, we aim to firstly give quantitative analyses of the reliability issues of STT-MRAM, taking into consideration the physical properties and manufacturing process. Secondly, based on these analysis results, a channel model from informative perspective would then be proposed. This model provides an effective simulation tool to evaluate the reliability performance of STT-MRAM. Finally, reliability enhancement design considerations and strategies are presented for the STT-MRAM circuit and system designers.

Recent progress lead spin-transfer torque magnetic tunnel junctions (STT-MTJs) to emerge as a breakthrough for embedded and standalone non-volatile memory [1]. A peculiarity of this technology, however, is its stochastic switching nature [2]. In memory applications, the randomness of the delay to program from a memory state to another requires designing programming times with high safety margins, to ensure reliable programming. However, considering this MTJs behavior as an intrinsic feature and not as a drawback can benefit unconventional applications. In particular, here we propose to use MTJs as “stochastic binary memristive synapses”. We show how MTJs may then be used in a brain-inspired (neuromorphic) system for practical applications, where MTJs implement at the same time massive nonvolatile memory and a stochastic learning rule. We perform simulations of our system using analytical equations to describe MTJs' probabilistic behavior, in different programming regimes. These simulations highlight the potential of the technology for learning systems that are also robust to device variations. We study the impact of the different programming regimes on the operation and on the energy consumption of the system. These results open the way for unexplored applications of MTJs in robust, low power, cognitive-type systems.

Current-induced spin-transfer torque (STT) is a mainstream method of switching the magnetization of free layer of magnetic tunnel junctions (MTJs) [1-2]. However, currently STT-MTJ is suffering from speed and energy bottlenecks caused by two tradeoffs: firstly, since the critical write current (I c0 ) is proportional to the thermal stability barrier (Δ), it is difficult to reduce I c0 without decreasing Δ. Secondly, the write current is limited to a relative small value to avoid the barrier breakdown, resulting in a low write speed. To overcome these bottlenecks, recent experiments [3-7] provide alternative write schemes in which spin Hall effect (SHE) and Rashba effect are used for switching the three-terminal MTJs (see Fig. 1). However, the applications of these schemes are hindered by some disadvantages: For switching a perpendicular-anisotropy MTJ (p-MTJ), both a charge current and an additional magnetic field are required (see Fig. 1(a)), which adds complexity to architecture. If an in-plane-anisotropy MTJ (i-MTJ) is used instead of p-MTJ, deterministic switching can be achieved by a charge current without the need of magnetic field (see Fig. 1(b)), but i-MTJ is inferior to p-MTJ in the scalability.

Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive concept based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. Although the first prototype has been successfully fabricated, its advancement is relatively arduous caused by certain technique and material limitations. Particularly, the storage capacity issue is one of the most serious bottlenecks hindering its application for practical systems. In this paper, we present two alternative solutions to improve the capacity of racetrack memory: magnetic field assistance and chiral domain wall (DW) motion. The former one can lower the current density for DW shifting; the latter one can utilize materials with low resistivity. Both of them are able to increase the nanowire length and allow higher feasibility of large-capacity racetrack memory. Furthermore, system level simulation shows that a racetrack memory based cache can improve system performance by about 15.8% and significantly reduces the energy consumption, compared to the SRAM counterpart.

Emerging magnetic random access memory (MRAM) has been considered as a promising candidate for the next generation high speed, low power and scalable nonvolatile memory technology. However many challenges and issues are still existing before its wide commercialization. One of the critical issues is its low sensing reliability due to the relatively small tunnel magneto-resistance (TMR) ratio of the magnetic tunneling junction (MTJ) and the increasing process variations etc. In this paper, we propose a new MRAM reference cell design as well as a novel dynamic reference scheme to improve the sensing reliability of MRAM. Using a physics-based MTJ model and a CMOS design kit, Monte-Carlo simulations have been performed to demonstrate its effectiveness in 40 nm technology node.

Traditional memory and logic gates are suffering the dilemma of power dissipation rising when the CMOS technology scales down to 40 nm node. By integrating the spin property of electrons, spintronics becomes an emerging technology to overcome definitively this bottleneck. In particular, the magnetic tunnel junction (MTJ) nanopillar combining with spin transfer torque (STT) switching mechanism has become a promising candidate to build novel low power integrated circuits thanks to its fast access speed, no-volatility and infinite endurance. This paper will describe the principle of STT and review its recent development for memories and logic gates. Related performance comparisons and physical challenges will be also outlined and discussed.

Benefiting from its inherent hardness to radiation and non-volatility, magnetic random access memory (MRAM) is considered as one of the most promising non-volatile memory (NVM) technologies for aerospace and avionic electronics. However, MRAM is still sensitive to single event upsets (SEU) due to its CMOS employed peripheral circuit. In this paper, we propose a novel SEU-tolerant MRAM latch circuit, which is based on the special device C-element. By using a physics-based MTJ compact model and the 40nm design kit, hybrid simulations have been performed and simulation results show that the proposed MRAM latch circuit is immune to radiation effects.

Emerging ferroelectric tunnel memristors show large OFF/ON resistance ratio (>100) and high operation speed (~10ns), promising to be widely applied in the future synapse-like systems. In this paper we propose a neuromorphic network with ferroelectric tunnel memristor. This network is arranged with classical crossbar topology, in which each crosspoint forms a synapse consisting of a MOS transistor and a memristor. Based on this architecture, we design a spike-timing dependent plasticity (STDP) scheme and a parallel supervised learning circuit. Using a compact model of ferroelectric tunnel memristor and CMOS 40nm design kit, we perform transient simulation to validate the functionality of the proposed STDP and learning circuit. Simulation results show the potential of our neuromorphic network in low power (~100nA or ~1μA) and high speed (μs or ~100ns) computing system.

Magnetic Tunnel Junctions (MTJs) – the basic structures of the Spin-Transfer Torque Magnetic RAMs (STT-MRAM) currently reaching the market present a complex and probabilistic switching behavior. Although some analytical models describing this behavior exist, they can not describe all the switching regimes of the MTJs. They can model low (“subcritical”) and high (“supercritical”) currents, but not the intermediate currents, which are essential for applications. In this work, we present Monte-Carlo simulations of MTJs that have been used to build a compact model linking the two different current regimes. This model allowed us to perform system-level simulations of an original neuroinspired chip that uses MTJs as binary stochastic “synapses”.

Conventional CMOS integrated circuits suffer from serve power and scalability challenges as technology node scales into ultra-deep-micron technology nodes. Alternative approaches beyond charge-only based circuits. In particular, spin-based devices or integrated circuits show promising merits to overcome these issues by adding the spin freedom of electrons to the electronic circuits. Spintronics has now become a hot topic in both academics and industrials. This paper overviews the status and prospects of spin-based integrated circuits under intense investigation and address particularly their merits and challenges for practical applications.

Advanced computing ICs in ultra deep-micron technology nodes (e.g. 40 nm) suffer from high power issues, which become one of the major bottlenecks for the future performance progress. Both static and dynamic power dissipation are increasing, caused mainly by the intrinsic leakage currents and large data traffic. Alternative approaches beyond charge-based logic circuits become hot research topics to overcome these issues definitively. By integrating the spin freedom of electrons to electronic devices, spin-electronics is promising for ultra-low power computing as it can provide non-volatility, fast data control and high logic density etc. Today, most of large microelectronics industries investigate this emerging field. In this invited paper for the special session “Nanoscale logic fabrics”, we overview spin-electronics based logic fabrics under intense investigation and address particularly the impact of this technology on logic architectures and new computing paradigms.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) provides a promising pathway for the next generation of non-volatile memory and logic chips. The perpendicular magnetic anisotropy (PMA) in CoFeB/MgO/CoFeB magnetic tunnel junction (MTJ) nanopillar provides high thermal stability and low critical current. However, the STT switching mechanism of MTJ has been revealed intrinsically stochastic, which results from the unavoidable thermal fluctuations of magnetization. This phenomenon affects deeply the reliability of hybrid CMOS/MTJ interface circuits and drives important power overhead. In this paper, we present a multilevel cell (MLC) STT-MRAM benefiting from the stochastic behaviors. It allows not only higher storage density, but also reduces the programming power and delay. This new cell can be also used as electrical synapse to build up neuromorphic computing systems or other biological networks. Monte-Carlo statistical simulations based on a 40 nm technology node have been carried out to validate its functionality and demonstrate its performance.

Reconfigurable computing provides a number of advantages such as low RD however its low power efficiency and logic density limit greatly its wide application. One of the major reasons of this shortcoming is the SRAM based configuration memory, which occupies large die area and consumes high static power. The later is more severe due to the rapidly increasing sneak currents, which are intrinsic and become worse following the fabrication node shrinking. Racetrack memory is one of emerging non-volatile memory technologies under intense investigation and promises ultra-high density, non-volatility and low power. In this invited paper, we present the design of racetrack memory based reconfigurable computing. By using a racetrack memory compact model and design kit 28 nm, mixed simulation results show its high density and low power performance compared with conventional SRAM based reconfigurable computing.

Advanced computing systems suffer from high static power due to the rapidly rising leakage currents in deep submicron CMOS technology. Fast access non-volatile memories (NVM) are under intense investigation to be integrated in Flip-Flops or computing memories to allow system power-off in standby state and save power. Spin Torque Transfer MRAM (STT-MRAM) is considered the most promising NVM technology to address this issue thanks to its fast speed, low power, and infinite endurance. In this paper, we present a new design of magnetic flip-flop (MFF) based on STT-MRAM. By integrating multi-context data checkpointing and self-enable switching mechanisms, its overall power can be lowered further than conventional structures. We performed hybrid simulations to validate its functional behaviors and evaluate its performance by using an accurate STT-MRAM spice model and an industrial CMOS 40 nm design kit.

As the technology node shrinks down to 90 nm and below, high power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the increasing leakage currents and data traffic. Emerging non-volatile memories are under intense investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its quasi-infinite endurance, high speed and easy 3D integration at the back-end process of CMOS IC fabrication, Magnetic RAM (MRAM) is considered as one of the most promising candidates. A number of hybrid MRAM/CMOS logic circuits have been proposed and prototyped successfully in the last years. In this introduction paper for the invited special session at NEWCAS 2013, we present an overview and current status of these logic circuits and discuss their potential applications in the future.

Spintronics-based non-volatile storage devices promise great potential to be integrated in reconfigurable circuits to overcome the major hurdles related to conventional flash and SRAM memories, such as low logic density, high standby power and long (re) boot latency. In this paper, we describe a compact design of configurable logic block based on Magnetic RAM (MRAM) crossbar architecture. The logic density can be increased greatly (∼ 5 times) compared to conventional designs; the standby power can be nearly zero thanks to the non-volatility of MRAM. Its high speed and power efficiency (∼10.4 Tera-OPS/Watt in computing mode) are also demonstrated through mixed CMOS/Magnetic spice simulations. Fully dynamic reconfiguration through context switching is also studied, which could be achieved with low area overhead.

In this paper, we propose two general analytic methods for building cartographical representations of large amounts of spatial data collected in the form of Origin-Destination (OD) matrices. The use of classical techniques, such as the Linear Directional Mean (LDM), for the mapping of OD data, may lead to cartographical representations which are difficult to interpret visually, especially when the size of the OD matrix is large. The two methods that we propose, which are extensions of Toblers LDM method, overcome this limitation and allow the discovery of interesting mobility patterns: a first extension, the Weighted Linear Directional Mean (WLDM), computes the mean direction of movement by weighting the volumes of mobility flows. The second extension, the Dempster-Shafer Weighted Linear Directional Mean (DS-WLDM), takes into account ignorance (which corresponds to a missing origin and/or destination for a particular movement), as well as incertitude, which may both occur in real OD data. The paper also presents an example in which the two proposed methods are applied to administrative data, in order to evaluate the spatial and temporal aspects of daily and residential mobility of workers between Luxembourg and its bordering areas. The methods we propose are generic and allow the use of multiple spatial scales (e.g. locality, district, municipality etc.), with potential fields of application including the mapping of social and demographic information (e.g. mobility of people, goods and information) as well as the cartographic representation of traffic flows.

Proposed nanometer-scale electronic devices are generally expected to feature an increased probability of manufacturing defects. We present in this paper a novel, highly fault-tolerant architecture, based on memristor crossbar architecture that may enable reliable implementation of neural network. Simulation results of our learning method inspired of Delta rule [1] for monolayer crossbar, exhibits very fast convergence rate to learn Boolean functions. In addition we simulate the impact of defects to measure the ability of our architecture to repair defective neurons, using a competitive learning scheme with or without redundancy. The architecture is able to learn the Boolean functions with manufacturing defect rate up to 13% with reasonable redundancy amount. It shows the best fault-tolerance performance comparing with the other techniques like RMR, von Neumann multiplexing and reconfiguration.

In this paper, we present a new design of TAS-MRAM, which is dedicated for the embedded applications. The Thermally Assisted Switching (TAS) approach allows the low power memory programming and Pre-Charge Sense Amplifiers (PCSA) enable the reliable, high speed and low power sensing. By using a TAS-MTJ spice model integrating the precise experimental parameters and CMOS 130nm technology, simulations have been done to demonstrate the expected performances; a 128Kb prototype has been developed to validate experimentally the new design by means of standard cell and automatic macro generation techniques.

In this paper, we present the design of artificial neural network architecture to implement the look-up table of reconfigurable circuits. The various cells of schematic used only the carbon nanotubes semiconductors (CNTFET), and the non volatile multi-level resistance. The compatibility between CNTFET and non volatile multi-level resistance in the state of the art has been studied. Then the electrical circuit simulation results demonstrate successful learning of the linearly separable logical functions.

One of the solutions to reduce the computational complexity of image processing is to perform some low-level computations on the sensor focal plane. This paper presents a vision system based on a smart sensor. PARIS1 (Programmable Analog Retina-like Image Sensor) is the first prototype used to evaluate the architecture of an on-chip vision system based on such a sensor and a digital processor. The sensor integrates analog and digital computing units. This architecture makes the vision system more compact and increases the performances reducing the data flow exchanges with the digital processor. A system has been implemented as a proof-of-concept. This has enabled us to evaluate the performance needed for a possible implementation of a digital processor on the same chip. The approach is compared to two architectures implementing CMOS sensors and interfaced to the same processor. The comparison is related to image processing computation time, processing reliability, programmability, precision, bandwidth and subsequent stages of computations.

In this article a switched capacitors based cell, dedicated to analog computing is presented. The aim is to allow the automatic synthesis of analog computing circuit. Therefore, the set of operations that this structure synthesizes and an analysis of the effects of technological non-ideal effects are presented

In this study, the exchange coupling at the interface of two different magnetic materials remains is investigated by using an original local technique combining lithography with scanning probe microscopy. A home-made magnetic force microscopy device that allows measurements in perpendicular magnetic field up to 1.8 T, operating in noncontact mode is used. The sample used is a bilayer of thin layer of nickel on a very thick yttrium-iron garnet layer (YIG), with strong perpendicular anisotropy and developing stripes of alternate magnetization. The nickel top-layer is prepared to obtain several 400 nm-wide Hall crosses by means of electronic lithography. From the measurements done, the YIG magnetic configuration is determined in which the dark regions correspond to the minority magnetic domains, whose magnetization is opposite to the external field and to the moment of the scanning tip. Hall effect measurements of nickel show that an extraordinary Hall effect depending on the perpendicular component of magnetization is predominant. A strong coupling between garnet and nickel is observed, leading to a measurable rotation of the magnetization planar component just by displacement of the YIG domains underneath.

There are many vision algorithms of image processing with CMOS image sensors such as image enhancement, segmentation, feature extraction and pattern recognition. These algorithms are frequently used in software-based operations. Here, the main research interest focuses on how to integrate image processing (vision) algorithms with CMOS integrated systems or how to implement smart retinas in hardware, in terms of their system-level architecture and design methodologies. The approach is compared with state-of-the-art vision chips build using digital SIMD arrays and vision systems using CMOS sensors combined with FPGA technology. As a test bench, an advanced algorithm for an exposure time calibration is presented with experimental results of image processing.

This paper, a new processing architecture approach for a vision system on chip (SoC) is presented. It highlights a compromise between versatility, parallelism, processing speed and resolution. This enables to increase the system performances. The approach consists to set operators, usually integrated close in the pixels, at the array edge. Consequently, the operator's functions are shared by a group of pixels, and the image processing is then carried out sequentially. This architecture results in a pixels array associated to a mixed analog-digital processors vector. Each processor is able to carry out, in situ, a wide range of low-level image processing algorithms. A digital processor can then process the low-level information. A silicon retina is an image sensor in which analog/digital signal processing circuits are integrated in the image-sensing element or at the edge of the image sensor array to achieve some simple low-level image processing. Their key features are their capability to enable massively parallel computations with rather low power consumption. The aim when integrating such a processor, next to image sensor in a single circuit, is to increase the pixel's Fill Factor and to remove the input output bottleneck between the sensor and the digital processor.

This paper discusses design solution for integrating a complete vision system on a single chip. We describe the architecture and the implementation of a smart integrated retina based vision system dedicated for vehicles applications. The retina is a circuit that combines image acquisition and analog/digital processing operators allowing the achievement of real-time image processing. Interests of vision system integration are analysed through comparisons with conventional approaches using CCD cameras and a digital processor or CMOS sensors combined with wired algorithms on FPGA technology. Our solution takes the advantages of both these solutions.

This paper discusses the architecture and implementation of a Smart Integrated Retina based vision system dedicated for intelligent vehicles applications. The Retina is a circuit that combines image acquisition and analog processing elements allowing the achievement of realtime image processing with high efficiency in terms of speed and power consumption. In the current version, an external processor is used to control the data flow image processing. This will enable us to evaluate the performance needed and the implementation of such a processor in the same integrated circuit. This architecture will exploit in an optimal way the capabilities of the retina. The approach is compared with state-of-the-art vision chips build using digital SIMD arrays and vision systems using CMOS sensors combined with FPGA technology. As a test bench, an advanced algorithm for an exposure time calibration is presented with experimental results.

In this paper, an original architecture of cellular neural network (CNN) vision chip is addressed. In the introduction, an analyse of the limitations of the usual approaches leads us to propose an original architecture. The paper is dedicated to the description of the three main blocks of our vision chip. Then, the major building blocks are detailed. Finally, design considerations and the practical implementation of a typical CNN algorithm are discussed.

The design of systems implementing low precision neural networks with emerging memories such as resistive random access memory (RRAM) is a major lead for reducing the energy consumption of artificial intelligence (AI). Multiple works have for example proposed in-memory architectures to implement low power binarized neural networks. These simple neural networks, where synaptic weights and neuronal activations assume binary values, can indeed approach state-of-the-art performance on vision tasks. In this work, we revisit one of these architectures where synapses are implemented in a differential fashion to reduce bit errors, and synaptic weights are read using precharge sense amplifiers. Based on experimental measurements on a hybrid 130 nm CMOS/RRAM chip and on circuit simulation, we show that the same memory array architecture can be used to implement ternary weights instead of binary weights, and that this technique is particularly appropriate if the sense amplifier is operated in near-threshold regime. We also show based on neural network simulation on the CIFAR-10 image recognition task that going from binary to ternary neural networks significantly increases neural network performance. These results highlight that AI circuits function may sometimes be revisited when operated in low power regimes.