Search

Monitoring train integrity is a very important topic for economical, management and safety reasons. Knowing the localization, volume and other parameters is very valuable for most train and large industry companies. Current literature focuses on placing many sensors in a Wireless Sensor Network (WSN) around the train wagons, but do not take battery lifetime into perspective. With the increasing interest in industrial Internet of Things (IoT) applications, the connectivity and battery lifetime are very important parameters. In this paper, the vibrations measured on train wagons are analyzed in order to find the most optimal trigger point to wake up or to put the WSN in a deep sleep mode. This way, a large amount of power can be saved and extend the battery lifetime significantly. Furthermore, several Received Signal Strength Indicator (RSSI) measurements were performed to find the optimal Tx level and antenna topology for communication between different wireless sensor nodes on the train wagon. The proposed measurements show that an inexpensive accelerometer and a prefabricated antenna are perfectly usable in the WSN. RF measurements on the brakes results in an average Package Receive Rate (PRR) of approximately 92 % and an Average Received Power (ARP) of around −83 dBm starting from a Tx level of 4 dBm.

With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews the latest trends and advances in technology to enable logic scaling. Dimensional scaling, enabled by EUV lithography, will continue with advances in multi-patterning. Higher costs of EUV multi-patterning will be mitigated by high (0.55) numerical aperture (NA) EUV simplifying the patterning and potentially leading to higher yield. Logic standard cell scaling below 6-track (6T) with adequate drive current per footprint will require adoption of Gate-All-Around (GAA) device architectures, like nanosheets, along with scaling boosters like buried power rails (BPR) and semi-damascene metal integration scheme with air-gaps. Scaling below 5-track (5T) will require new compact device architectures like complementary FETs (CFETs) and alternate intra-cell interconnect layouts. Slowing SRAM scaling can also benefit from migration to BPR, forksheets and CFETs. Channels formed from 2D materials can theoretically enable gate length (L g ) and contacted poly pitch (CPP) scaling. Several new material innovations will be needed to enable 2D atomic channel transistors. Changing our view from circuits to systems, 3D integration techniques will continue to enable subsystem scaling like cache partitioning of SoCs to improve memory access. Finally, a methodology to estimate the environmental impact of technology scaling choices is proposed.

[Background]: Developing conceptual models is an integral part of the requirements engineering (RE) process. Goal models are requirements engineering conceptual models that allow diagrammatic representation of stakeholder intentions and how they affect each other. A specific goal modeling language construct, the contribution of goal satisfaction of one goal to another, plays a central role in supporting decision problem exploration within goal models. [Aims]: We report on an experiment whose aim was to measure the user perception of the meaning of the aforementioned modeling construct. [Method]: A set of contributions under different scenarios were given to experimental participants who were asked what they thought the effect of the contribution was. [Results]: We found that participants are not always in agreement either within themselves or with the designers' intentions on the meaning of the language. [Conclusions]: The results call for possible adaptations to the way goal modeling languages are used.

The development of an antifouling coating for 316L 2B stainless steel pipes used in heat exchangers for milk products was studied in this paper. The coating was obtained using hexamethyldisiloxane (HMDSO) as precursor applied by atmospheric plasma on stainless steel. The stainless steel plates were first pre-treated using nitrogen or air atmospheric pressure plasma to improve the surface properties before coating. Various conditions (distance between plasma source and substrate, aging time and number of passes) were tested to study the influence of these parameters on the surface energy of stainless steel. The HMDSO based coating was then deposited by atmospheric plasma on the pre-treated steel plates and the plates obtained were tested to fouling in a pilot heat-exchanger. Surface response methodology (experimental design) was used in order to identify the optimized coating conditions to minimize the fouling. Mechanical profilometry, Atomic Force Microscopy (AFM), Electron Probe Micro Analyzis (EPMA), Flight-Secondary Ion Mass Spectroscopy (ToF-SIMS), X-Ray Photoelectron Spectrometry (XPS) and goniometry were used to evaluate the coating roughness, morphology, surface energy and chemical composition.

We report high yield sub-0.1µm2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099µm2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089µm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

We demonstrate electrically functional 0.099µm2 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L g ∼40nm, 12–17nm wide Fins, and cell β ratio ∼1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM≫10%V DD down to 0.4V, and healthy electrical characteristics for the cell transistors [SS∼80mV/dec, DIBL∼50–80mV/V, and |V Tlin |≤0.2V (PMOS), V Tlin ∼0.36V (NMOS)] are reported.

In this paper, the experiences on full field EUVL lithography are reviewed. Besides the imaging performance of the EUV ADT at IMEC, also the progress in resists and reticles are discussed and compared to the production requirements for EUV lithography.

We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3sigmales7 nm after double-dipole 193 nm immersion litho (NA=0.85) and 3sigmales9 nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM VDD scalability down to 0.6V (SNM>0.1VDD) and healthy electrical characteristics (VT, sigma(DeltaVT), I-V) for the cell transistors are obtained.

Reliable segmentation of 3D magnetic resonance angiography (MRA) is fundamental for planning and performing neurosurgical procedures, but also for detecting vascular pathologies. We propose here a method for brain vessel segmentation based on mathematical morphology tools. This method, devoted to phase-contrast MRA (PC-MRA) performs vessel segmentation by applying an adaptive set of grey-level hit-or-miss operators on each point of the MR data. High level anatomical knowledge modeled by a vascular atlas is used in order to adapt the parameters of these operators (number, size, and orientation) to the current position. The method has been performed on 30 PC-MRA cases composed of both phase and magnitude images. The results have been validated and compared to segmented data obtained by applying a region-growing algorithm on the same database. They tend to prove that the method is reliable for brain vessel detection and additionally provides information on vessel size and orientation without requiring any post-processing step.

Magnetic resonance angiography (MRA) is currently used for cerebral flowing blood visualization. Many segmentation methods have been proposed for brain vessel segmentation, in order to help analyzing the huge data (generally more than 10/sup 7/ voxels) provided by MRA acquisitions. Recently, a new family of segmentation algorithms, involving high level anatomical knowledge, has been studied. These new algorithms require a way to model and store this knowledge. An efficient and general approach to reach that goal consists in using atlases. In this paper a method is proposed to create vascular atlases of the brain, containing information useful for vessel segmentation purpose. This atlas creation process, designed for phase-contrast MRA (PC-MRA), is composed of four steps: segmentation, quantification, registration and data fusion. It uses a region-growing algorithm for vessel segmentation, a skeleton and vessel size determination algorithm, based on discrete geometry, for determination of quantitative properties, and a topology preserving non-rigid registration method to fuse the information. This method, which has been applied to a 18 PC-MRA database, enables to create vascular atlases containing information on brain vessels position, density, size and orientation. The generated atlases are essentially devoted to segmentation purpose but can also be used for anatomical description or pathology detection.

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

193nm immersion lithography has recently gained a lot of momentum, and is currently anticipated to be the prime lithography solution for the 65nm and 45nm half pitch technology nodes. In this paper, the latest achievements obtained in the IMEC immersion program are reviewed. Also the remaining concerns are addressed. Items touched upon are: lithographic performance of the full field scanner, defectivity including bubbles, resist and top coat progress and polarization effects.

This work experimentally investigates the impact of line-edge roughness (LER) on the intrinsic transistor performance of the MOS transistor. Examined gate lengths range down to 50 nm. To emphasize the impact of LER, transistors with extra rough poly gates are created by e-beam lithography. Assumptions of models, that describe the effects of LER, are tested on transistors with sinusoidal gate-shapes. For the first time, the impact of LER on transistor yield is reported.

In order to cope with the progressive scaling of CMOS, new lithography techniques are introduced for sub-90nm applications. Among them are the introduction of the 157nm wavelength and extreme ultra-violet lithography (EUVL). However, the delay in availability of these tools requires the extension of 193nm lithography towards future technology nodes. This paper gives an overview of the latest breakthroughs and the remaining challenges to the lithography community.

It is generally accepted that optical lithography will be the technology of choice for the fabrication of devices for several generations to come. In this paper some of the current challenges to print 0.25 /spl mu/m dimensions are addressed. Although the mainstream technologies for 0.35 /spl mu/m and 0.25 /spl mu/m processes are more or less settled, the main challenge will most likely be CD control. Optical proximity effects and CD variations resulting from substrate reflections start to play a major role in the CD budget. Several methods to reduce these contributions (such as the use of optical proximity correction techniques and the use of anti-reflection coatings and surface imaging processes) are presented. Moreover, it will be indicated that considerable improvements in CD control can be obtained by optimization of stepper parameters. Finally, in an attempt to indicate the future of optical lithography, a simulation study is presented, indicating the available process latitudes which can be obtained by combining several of the above listed techniques.

Optical lithography is continuously pushed to its limits for volume manufacturing of integrated circuits. With the implementation of low-k dielectrics in the back-end-of-line processes, the optical properties of the dielectric stack have drastically changed. Also the transition from the conventional AlCu dry-etch scheme to several potential damascene integration schemes has significant impact on the lithography process and should be taken into account. Usually front-end-of-line development is considered as the driving force for lithography. However back-end lithography has become as challenging recently. In this paper, the various issues for back-end damascene lithography processes for the 0.13 um technology node will be outlined. The IMEC strategy for back-end-of-line lithography solutions will be outlined, for both 248 nm and 193 nm lithography.