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Reliability is an important consideration during semiconductor technology development, which ensures that the performances of devices, circuits, and systems are maintained over a specified period of time, leading to successful products. Device reliability is at the core of overall product reliability, which continues to remain an important area of research and has attracted the attention of IEEE Transactions on Electron Devices (T-ED) authors and readers throughout the years. Device reliability can be classified into two broad areas: gradual drift of device performance over time or sudden failure, and both are of importance for logic, memory, RF, and power devices. Different aspects of device reliability are usually reported, such as the development of electrical or physical characterization methods, investigation and modeling of a particular phenomenon, impact of material and processes on reliability, and development of reliability tolerant technologies. [ABSTRACT FROM AUTHOR]

We present GoldMine, a methodology for generating assertions automatically in hardware. Our method involves a combination of data mining and static analysis of the register transfer level (RTL) design. The RTL design is first simulated to generate data about the design's dynamic behavior. The generated data is then mined for “candidate assertions” that are likely to be invariants. The data mining algorithm is a decision-tree-based supervised learning algorithm. These candidate assertions are then passed through a formal verification engine to filter out the spurious candidates. The assertions that are attested as true by the formal engine are system invariants. These are then evaluated by a process of designer ranking that is provided as feedback to the data mining engine. We demonstrate the scalability of GoldMine by showing assertion generation of the RTL of Sun's OpenSparc T2 many-threaded processor. Our results show that GoldMine can generate complex, high coverage assertions for sequential as well as combinational designs in RTL, thereby minimizing human effort in this process. GoldMine assertions distill the random input stimulus space and can be used for calibrating directed tests. They can be used in a regression test suite of an evolving RTL. They are also useful in providing differing perspectives from the designer, as well as hints to designers for manually writing assertions. [ABSTRACT FROM PUBLISHER]

A practical parameter extraction procedure for a power silicon carbide (SiC) junction field-effect transistor (JFET) is presented. The carrier mobility and carrier concentration are very important parameters, strongly affecting the device current capability and dynamic characteristics for a given design. When modeling JFETs, the values of these parameters are usually based on assumptions and given by a vendor in a range. As a result, model accuracy is compromised. In this paper, a step-by-step parameter extraction procedure is described that includes the extraction of mobility and carrier concentration in the channel and drift regions based on knowledge of device geometrical parameters. For the first time, carrier mobilities in the channel and drift regions of a power JFET are extracted individually. It is found that channel and drift region mobilities can be very different for a given device since they are strongly dependent on the fabrication process. The separate extraction of these two mobilities can also improve model accuracy in the case of imperfect knowledge of the device geometry. The developed procedure includes the extraction of empirical parameters describing the temperature dependence of mobilities in the channel and drift regions. A simple static I– V characterization and C–V measurements are the only measurements required for the parameter extraction. In this paper, the procedure is experimentally validated for both normally off (enhancement mode) and normally on (depletion mode) JFETs. [ABSTRACT FROM AUTHOR]

A novel SiC junction field-effect transistor (JFET) model that uses a unified description of linear and saturated conduction modes is proposed. Advantages of the proposed model are improved robustness and convergence, inclusion of field-dependent mobility effects, and more physical description of the current saturation phenomenon. The model is validated against a normally off JFET sample over a wide temperature range. Finite-element simulations are used to demonstrate the physics-based nature of the proposed model. [ABSTRACT FROM AUTHOR]

In this paper, a physical model for a SiC Junction Field Effect Transistor (JFET) is presented. The novel feature of the model is that the mobility dependence on both temperature and electric field is taken into account. This is particularly important for high-current power devices where the maximum conduction current is limited by drift velocity saturation in the channel. The model equations are described in detail, emphasizing the differences introduced by the field-dependent mobility model. The model is then implemented in Pspice. Both static and dynamic simulation results are given. The results are validated with experimental results under static conditions and under resistive and inductive switching conditions. [ABSTRACT FROM AUTHOR]

This paper presents modeling of correlated RF noise in the intrinsic base and collector currents of SiGe heterojunction bipolar transistors using quasi-static equivalent circuits. The noises are first extracted from measured noise parameters using standard noise circuit analysis. Using the extraction results, model equations are proposed to describe both the frequency and bias dependence of the correlated noise sources using a single set of model parameters. The model is demonstrated using noise data from both measurement and microscopic noise simulation. The model is shown to work at frequencies up to at least half of the peak fT and at biasing currents below high injection fT rolloff. [ABSTRACT FROM AUTHOR]

Proton irradiation is used to probe the physics of 4H-silicon carbide (SiC) Schottky barrier diodes (SBDs) and negative channel metal oxide semiconductor (nMOS) capacitors for the first time. Both 4H-SiC SBD diodes and SIC MOS structures show excellent radiation tolerance under high-energy, high-dose proton exposure. Unlike for SiC JBS diodes, which show a strong increase in series resistance after proton irradiation, these SiC SBDs show very little forward bias I-V degradation after exposure to 63.3 MeV protons up to a fluence of 5 × 1013 p/cm2. An improvement in reverse leakage current after irradiation is also observed, which could be due to a proton annealing effect. The small but observable increase in blocking voltage for these SiC SBDs is attributed to a negative surface charge increase, consistent with earlier gamma results. The resultant Qeff change of 4H-SiC nMOS capacitors under proton irradiation was used to quantify the radiation induced changes to the blocking voltage in the SBD diodes in MEDIC! simulations, and showed a good agreement with the experimental data. Characterization of these capacitors also suggests that 4H-SiC MOS structures are radiation hard. [ABSTRACT FROM AUTHOR]

This paper discusses and illustrates the key device design issues for SiGe BiCMOS HBTs suitable for wireless power amplifier (PA) applications. Experimental results addressing ruggedness, ac performance, and safe operating area for high-breakdown SiGe HBTs built in several generations of BiCMOS technology are presented. Implications of recent high-performance SiGe HBT scaling achievements for BiCMOS technologies targeting wireless PA applications are considered. Circuit results for GSM, PCS, GPRS, and EDGE front-end modules have been obtained. A one-chip solution is demonstrated, including control circuitry and switching functionality, that supports all GPRS, PCS, and EDGE modes featuring output power at 33.8 dBm and overall power added efficiency of 37% withstanding voltage standing wave ratio conditions of 15:1. [ABSTRACT FROM AUTHOR]

The effects of proton irradiation on the static (dc) and dynamic (switching) performance of high-voltage.. 4H-SiC Junction Barrier Schottky (JBS) diodes are investigated for the first time. In contrast to that Observed on a high-voltage Si p - i -n diode control device; these sic JBS devices show a increase (degradation) in series resistance (Rs), a decrease (improvement) of reverse leakage current, and increase (improvement) in blocking voltage after high-fluence proton exposure. Measured breakdown voltages of post-irradiated SiC diodes `increase on average by about 200 V after irradiation. Dynamic reverse recovery transient measurements show good agreement, between the, various dc observations regarding differences between high-power SiC and Si diodes, and show that SiC JBS diodes are very effective in minimizing switching losses for high-power applications, even under high levels of radiation exposure. [ABSTRACT FROM AUTHOR]

Presents information on the characterization of high-voltage 4H-Silicon carbide (SiC) Schottky diodes under high gamma irradiation. Critical electric field strength of SiC; Schematic cross section of the irradiated diodes; Typical forward characteristics of the difference Schottky diodes before and after each radiation dose.