96 results on '"WANG Chun-yao"'
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2. Minimizing Computation in Binarized Neural Network Inference using Partial-Filter Sharing
3. Accelerating Binarized Neural Network Inference by Reusing Operation Results and Elevating Resource Utilization on Edge devices
4. A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation
5. Overview of 2021 CAD Contest at ICCAD
6. A Don’t-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks.
7. Cluster Tool Performance Analysis using Graph Database
8. An IMU-aided Fitness System
9. On Reduction of Computations for Threshold Function Identification
10. On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays
11. Don’t Care Computation and De Morgan Transformation for Threshold Logic Network Optimization.
12. Majority Logic Circuit Minimization Using Node Addition and Removal.
13. LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach.
14. A Dynamic Expansion Order Algorithm for the SAT-based Minimization
15. Rehabilitation System for Limbs using IMUs
16. A Convolutional Result Sharing Approach for Binarized Neural Network Inference
17. Empirical Study of Multi-Objective Parameter Optimization in Wire Bonding Process
18. A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises
19. A Glitch Key-Gate for Logic Locking
20. A Data Mining Approach for Optimizing Manufacturing Parameters of Wire Bonding Process in IC Packaging Industry and Empirical Study
21. A New Necessary Condition for Threshold Function Identification.
22. LOOPLock: Logic Optimization-Based Cyclic Logic Locking.
23. Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments.
24. Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays
25. Using range-equivalent circuits for facilitating bounded sequential equivalence checking
26. Efficient synthesis of approximate threshold logic circuits with an error rate guarantee
27. Logic optimization with considering boolean relations
28. In&Out: Restructuring for threshold logic network optimization
29. Majority logic circuits optimisation by node merging
30. On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses.
31. MajorSat: A SAT solver to majority logic
32. CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction
33. The Cadabia Cloud
34. Synthesis and verification of cyclic combinational circuits
35. A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays
36. BDD-based synthesis of reconfigurable single-electron transistor arrays
37. Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays.
38. Using a Class Algebra Ontology To Define Conversions between OWL/SQL/Java Beans
39. Alzheimer's disease classification based on gait information
40. Sensitization criterion for threshold logic circuits and its application
41. Using structural relations for checking combinationality of cyclic circuits.
42. Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays.
43. Synthesis for Width Minimization in the Single-Electron Transistor Array.
44. CA-ABAC: Class Algebra Attribute-Based Access Control
45. Width minimization in the Single-Electron Transistor array synthesis.
46. Rewiring for threshold logic circuit minimization.
47. Gait analysis for patients with Alzheimer'S disease using a triaxial accelerometer
48. On rewiring and simplification for canonicity in threshold logic circuits
49. A register-transfer level testability analyzer
50. Distributed Transactions for Semantic Web Workflows - Overcoming the CAP Limitations on Virtual Organizations
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