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The reliability of graphene-capped copper (Gr/Cu) against humidity is assessed by spectroscopic ellipsometry (SE). Changes in the volume fraction of crystalline Gr in single-layer graphene (SLG) and tri-layer graphene (TLG), and also Cu-oxide thicknesses under the Gr cap were characterized by SE before and after humidity reliability testing. It was found that TLG has a higher moisture resistance than SLG with less change in the crystalline Gr volume fraction and thickness than that of SLG, and this leads to the reduction in Cu-oxide thickness and the uniformity under the Gr cap. The results were consistent with the analysis results by X-ray photoelectron spectroscopy and Raman spectroscopy excluding variations due to differences in analysis areas of each method. Since detailed structural changes, such as Gr quality and thickness, can be evaluated non-destructively, SE is considered to be a promising method for the detailed analysis of Gr/Cu structures.

Multilayer graphene (MLG) has been proposed as an alternative material for nanometer-wide interconnects. However, it has not been put to practical use, since the process technology that leads to practical use has been immature. Recent advances in MLG processes and applications, such as MLG-capped copper interconnects, the direct deposition of MLG by solid-phase deposition (SPD) at a low temperature, stable intercalation doping to MLG and selective chemical vapor deposition (CVD) of high-crystallinity MLG for inductor and antenna applications are reviewed. Based on these advances, MLG is considered to be approaching the stage of practical application for device metallization and high-frequency devices. Based on the characteristics of MLG as a conductor and recent development trends, the prospects and issues regarding the future practical use of MLG graphene are discussed.

To improve the long-term reliability of copper (Cu) pads used in LSIs, nitrogen-doped amorphous carbon (a-C:N) coating is applied to the Cu pads with direct wire-bonding to prevent Cu oxidation in humidity. To obtain a thin barrier, the thickness optimization of a-C:N layer was carried out under temperature humidity storage (THS) testing at the conditions of 85 °C/85% relative humidity. Cu pad chains coated with the optimized a-C:N film were fabricated by direct bonding with aluminum (Al) wires. The electrical connection up to 210 bonds was obtained with the 10 and 15 nm thick a-C:N coated Cu pads. The reliability test of the pad-chains under the THS was carried out, and a 15 nm thick a-C:N can preserve the electrical connection along 100 h of the THS test. The a-C:N coating is expected to improve the humidity reliability of Cu pads with direct wire-bonding for long-term data storage.

To enhance the humidity reliability of copper (Cu) metallization used in memory LSIs, nitrogen (N)-doped amorphous carbon (a-C:N) deposited by sputtering on the Cu surface is proposed. Since the preparation of a-C:N film can be achieved at room temperature, the process temperature is compatible with LSIs fabrication. After the high-temperature/humidity storage test, the a-C:N layer was found to be an excellent barrier to protect the Cu surface from oxidation and avoid the increase of Cu sheet resistance. Depth profiles imply no oxidation occurs on the underlying Cu surface. An appropriate concentration of N-doping is considered to prevent the penetration of moisture with the effects of the repulsive force between both N and O atoms. The proposed method is promising as a practical method to improve the reliability of Cu metallization for long-term storage.

To investigate the feasibility of flash memory reliability in an environment for the application of long-term data storage, temperature and humidity acceleration tests have been carried out for commercial flash memories. Nine commercial 16GB SD cards with conventional package were kept in a test chamber of 85 °C/85%RH for up to 3040 h and we checked the write/read operation using free software "Check Flash" after the storage test. The lifetime against humidity is predicted by the power law humidity model (Peck model), which is widely used for the lifetime prediction, assuming the average parameters such as humidity acceleration factor (n) and activation energy () from the literatures. Although further studies to assure the reliability, the results indicate that commercial flash memories preliminary have the feasibility of a long-term storage media over 100 years.

To establish the lifetime prediction model for Cu-based metallization against moisture, temperature humidity storage test under the various accelerated conditions is performed. The increase of Cu sheet resistance induced by Cu-oxidation is measured by a four-point probe method. X-ray photoelectron spectroscopy analysis is carried out to investigate the variation of oxidized Cu. The activation energy and the humidity acceleration factor for Cu-based metallization have been derived by the statistical analysis to predict the lifetime against moisture for the first time. The results indicate that Cu-based metallization is comparatively more sensitive to the temperature than humidity at around the practical use condition.

A method for producing a uniform multilayer graphene (MLG) film directly on SiO2 via solid-phase precipitation from carbon-doped cobalt (Co–C) with a Cu capping layer has been developed for a large scale integration (LSI) interconnect application. One advantage is that no transfer process is required. A 20 nm thick MLG film was grown uniformly from a 100 nm thick Co–C (20 at%) catalyst layer with a Cu capping layer. Cross-sectional TEM/EDX images revealed that the optimized Cu capping layer prevents Co agglomeration during annealing and promotes C precipitation on the SiO2 while eliminating it on the top surface of the catalytic metals.

In order to develop highly reliable Cu interconnects, temperature dependence of the electromigration (EM) lifetime of metal (CoWP) capped Cu interconnects is investigated. It is found that the EM lifetime is enhanced as the test temperature rise from 275 to 380 °C. NH3 plasma treatment before the dielectric cap layer deposition on the CoWP capped Cu interconnects influenced the temperature dependence of EM lifetime, that is, the interconnects without the NH3 plasma treatment have longer EM lifetime than those with the NH3 plasma treatment at the higher test temperatures. In order to investigate the mechanism for this lifetime enhancement, micro-analysis and failure mode analysis were carried out. It is concluded that the Co alloying with Cu and the CoWP coverage repair due to Co diffusion at the high temperature lead to the EM lifetime enhancement.

As the wiring-space decreases, the time-dependent dielectric breakdown (TDDB) of Cu/low-dielectric constant (k) interconnects becomes a critical reliability issue and more accurate prediction of the TDDB lifetime will be required. In this investigation, TDDB dependences on temperature and electric field are studied comprehensively for 90- and 65-nm-node Cu/SiOC interconnects using practical multilevel test structures with via plugs. Low-electric-field TDDB tests down to 1 MV/cm were carried out by a package TDDB method with high temperature up to 300 °C. Linear dependence of the TDDB lifetime on the electric-field is observed down to 1 MV/cm, and this suggests that the lifetime can be predicted using the E-model. The linear dependence of the TDDB lifetime on temperature is also observed up to 300 °C at 1.8 MV/cm. The activation energies for the 90 and 65 nm nodes are almost the same values, 0.76 eV for the 90 nm node and 0.74 eV for the 65 nm node. Failure is observed at the interfaces between the cap dielectric (SiCN) and the silicon dioxide layer with a surface polished by chemical-mechanical polishing (CMP) for both nodes. It is noted that no difference in the failure modes is seen between dense SiOC for the 90 nm node and porous SiOC for the 65 nm node, in spite of the different materials used for the intermetal dielectrics. This suggests that the polished interfaces greatly affect on the TDDB lifetime for both nodes. Improved TDDB lifetime is obtained by increasing the post-CMP cleaning time and the pretreatment time before the cap dielectric deposition. Sufficient TDDB lifetimes of over 10 years under practical operating conditions are obtained for both 90- and 65-nm-node Cu/low-k interconnects with via plugs.

A robust embedded ladder-oxide (k=2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 µm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 µm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

Multilayer graphene (MLG)/n-GaN Schottky diodes were fabricated by transfer-free deposition of MLG on n-GaN by solid-phase reactions with cobalt as a catalyst. The thermal stability of the diodes was determined from the current–voltage (I–V) characteristics after annealing the diodes in vacuum at 200–500 °C, at intervals of 100 °C. The diode characteristics evaluated using a thermionic emission model and Cheung's function using I–V data revealed that the Schottky barrier diode (SBD) fabricated with MLG as a Schottky contact on n-GaN showed better thermal stability than the conventional Ni/n-GaN SBD. The prevention of Au diffusion to n-GaN with MLG as a diffusion barrier layer and the unaffected interface reactions between n-GaN and MLG are possible reasons for the improved thermal stability, enabling potential application of this new diode in high-power and high-temperature operations.

Transfer-free deposition of multilayer graphene (MLG) on n-GaN by a solid-phase reaction was demonstrated for the first time for the fabrication of a Schottky diode. To improve the crystallinity and uniformity of MLG films, a new approach of heat sputtering for the deposition of amorphous carbon (C) and cobalt (Co) as catalyst layers has been investigated. The characteristics obtained by Raman spectroscopy and scanning electron microscopy (SEM) measurements revealed that the crystallinity and uniformity of MLG films were improved significantly by employing heat sputtering rather than conventional room-temperature sputtering. MLG–GaN Schottky diodes were fabricated with optimized deposition of MLG on n-GaN. The Schottky barrier height determined on the basis of the thermionic emission theory using current–voltage (I–V) data was 0.75 eV. The reverse leakage current was found to be of the order of 10−7 A/mm2. The obtained results indicate the MLG fabrication on n-GaN by our proposed method might have potential applications in the fabrication of Schottky diodes.

We investigated doping material selection for multilayer graphene (MLG) interconnects and a passivation process to stabilize the doped state. Intercalation doping with Br2, FeCl3, and MoCl5 was compared in terms of doping ability and robustness against environmental effects, which are exacerbated by miniaturization. We found that MoCl5 was advantageous for miniaturization. We hypothesized that environmental stability would be enhanced by partially oxidizing MoCl5 and avoiding hydrolysis by water vapor in air. To test this, we examined a passivation process by dry oxygen exposure. We verified that the doping effect was improved and that intercalated material (MoCl5) was partially oxidized and confined in the MLG.

To improve the crystallinity of multilayer graphene (MLG) films by solid-phase precipitation, a new method by which current stress is introduced during annealing of a carbon-doped cobalt (Co-C) layer using cobalt (Co) as the catalyst has been investigated. The effects of current stress on the formation and crystallinity of MLG films were investigated by comparing the characteristics of the films annealed at the same temperature with and without current by taking into account the temperature rise due to Joule heating. The characteristics obtained by Raman spectroscopy, scanning electron microscopy (SEM), transmission electron microscopy (TEM), and X-ray diffraction (XRD) measurements revealed that the MLG films produced were crystalline in nature and their crystallinity increased with applied current stress at the same temperature. From SEM observations, beside Joule heating, enhancement of Co grain size by agglomeration induced by current stress may be the potential reason for the improvement of the crystallinity of MLG films. We have also improved the uniformity of MLG films by depositing an additional copper (Cu) capping layer over the Co-C layer. Current stress application can lead to low-temperature fabrication of MLG with higher crystallinity by solid-phase precipitation.

To investigate the similarity and difference of substrate conduction type in the time-dependent dielectric breakdown (TDDB) tests for the barrier integrity against Cu diffusion under bias-temperature stress (BTS), the TDDB reliability of electroless NiB and CoWP/NiB was determined by metal oxide semiconductor (MOS) structures on n-type Si (n-Si) substrates, and the test results were compared with those using p-type Si (p-Si) substrates. The TDDB results and mechanism were observed to be qualitatively the same as Cu diffusion for both conduction types. However, the TDDB lifetime using p-Si was found to be potentially shorter because of the reverse bias conditions than that using n-Si under the forward bias conditions.

Multilayer graphene (MLG) is expected to be a low-resistance and high-reliability interconnect material replacing copper (Cu) in nanoscale interconnects. To achieve low-resistance interconnect with MLG, carrier doping is necessary since the carrier concentrations in pristine MLGs are low. In this work, the effects of bromine (Br) doping by intercalation on the carrier concentration and sheet resistance of exfoliated highly oriented pyrolytic graphite (HOPG) were investigated by measuring the Fermi level shift using ultraviolet photoelectron spectroscopy (UPS) and the four-terminal method, respectively. The Fermi level was shifted downward up to 0.63 eV, and the sheet resistance was reduced to less than 10% of that of the pristine HOPG by increasing the Br concentration. A similar Fermi level shift was observed for the commercially available CVD-MLG. Br doping is thus promising for low-resistance MLG interconnects from the perspective of carrier doping.

Low-resistance metal contacts for CVD-nanocarbon (NC)/cobalt (Co) interconnects have been investigated among contact metals such as Ni, Ti, Au, and Cu. Contact resistivity was independent of contact area owing to low-resistance NC/Co interconnect structure. The lowest contact resistivity and superior adhesion were obtained from Ni. Although the factors for the low contact resistivity were not clear enough from the comparison of work-function difference and adhesion strength for the contact metals, Ni is a promising low-resistivity contact metal for CVD-NC interconnects in the future.

Multilayer graphene (MLG) is expected to be a low-resistance and high-reliability interconnect material replacing copper (Cu) in nanoscale interconnects. Chemical vapor deposition (CVD) on catalytic metals is expected as a practical method for MLG deposition. To obtain high-quality MLG films without catalyst agglomeration by CVD, heat-resistant Co–W catalytic metals were investigated. The agglomeration of the Co–W catalytic metals was suppressed by increasing the W composition; however, MLG deposition was suppressed at the same time. The effects of W addition on the MLG growth were discussed from the viewpoints of the crystallographic change of the Co–W catalysts and chemical reactions. It was found that the Co grain size was reduced and the fcc Co formation was suppressed by W addition. In addition, graphite formation was supposed to be suppressed by W addition owing to the formation of phases other than fcc Co according to the Co–W–C phase diagram. With the optimum W concentration, MLG crystallinity was improved by high-temperature CVD using the heat-resistant Co–W catalytic metals (0.7 at. %) without agglomeration, compared with that in the case of using pure-Co catalysts.

To study the potential of electric current stress in enhancing the grain growth of electroplated copper (Cu) films, the behavior of Cu grain growth at different additive concentrations with current stress applied was investigated. It was found that the lower poly(ethylene glycol) (PEG) concentration alone slightly enhanced the grain growth, but the higher sulfopropyl sulfonate (SPS) concentration was favored in assisting larger grain growth in the current induced grain growth. The effect of current density and temperature on the current induced grain growth have also been studied, and it was found that current stress with a high current density and at a high temperature promotes a larger grain size and anisotropic grain growth along the current direction.

Barrier integrity of electroless NiB and CoWP/NiB thin layers against copper (Cu) diffusion was evaluated by time-dependent dielectric breakdown (TDDB) under bias temperature stress (BTS) using metal oxide semiconductor (MOS) test structures. The BTS tests were carried out also for an approximately 2.2-nm-thick organosilane monolayer (OSML), which has been used as the underlayer of the electroless barrier layers (EBLs). It was found that the barrier integrity of the EBLs was NiB 40 nm > NiB 10 nm > CoWP/NiB 40 nm = CoWP/NiB 10 nm in this order. The field acceleration parameter of the TDDB lifetime was almost the same for all EBLs. Initial failures and wide lifetime distributions were observed for CoWP/NiB when the NiB catalyst layer for CoWP was not thick enough, which is considered to be due to the large surface roughness. In addition, the OSML was found to have some barrier properties. Although the reliability of OSML was inferior to electroless NiB and CoWP/NiB barrier layers, it is considered that the barrier integrity of the EBLs was partially supported by the OSML.

Nanocarbon materials have been expected as post-Cu interconnect materials for large-scale integrated circuits (LSIs). In this paper, we present a nanocarbon deposition process using electroless plated NiB as the catalyst, which features conformal deposition on patterned dielectric surfaces. It was found that carbon nanotubes (CNTs) and graphitic films were deposited on the electroless NiB by atmospheric pressure chemical vapor deposition (CVD) using ethanol as the precursor. The graphitic quality estimated from the Raman spectra of the nanocarbon on the NiB catalyst was equivalent to that on a sputter-deposited pure Ni catalyst. The nanocarbon shape was dependent on NiB thickness, and CNTs were grown on 10-nm-thick NiB and graphitic films were grown on 30 nm or thicker NiB. The deposition temperature can be lowered to 505 °C, although the graphitic quality was degraded. It is considered that the electroless catalysts can be effective for nanocarbon deposition on patterned dielectric surfaces.

The resistivity increase caused by grain boundary (GB) scattering is a challenging problem in the formation of narrow copper (Cu) interconnects less than 100 nm wide. In order to reduce GB scattering, a new annealing method was successfully developed to enhance the grain growth of electroplated Cu films using supercritical (SC) CO2 with H2. In order to determine the effect of H2, the Cu surface was analyzed using X-ray photoelectron spectroscopy (XPS). The amounts of oxygen (O) and carbon (C) at the Cu surface after SC annealing were reduced with increasing H2 pressure. Surface migration was considered to be enhanced by the reduced amount of O and C, which led to grain growth enhancement. The cross-sectional grain structure in 100-nm-wide interconnect trenches was observed using secondary ion microscopy (SIM). The Cu grains inside the trench were found to be affected by the microstructure in the Cu overburden. Accordingly, Cu grain growth in trenches is also expected to be enhanced by SC annealing.

As promising technologies for fabrication of highly reliable Cu interconnects, using Ti barrier metal (Cu/Ti) and chemical vapor deposition (CVD) Co capping (Co/Cu/Ta/TaN) were compared. Both Cu interconnects similarly showed longer electromigration (EM) lifetime and larger activation energy of lifetime than conventional Cu interconnects fabricated using Ta/TaN barrier metal without capping metal (Cu/Ta/TaN). The residual resistance of Cu lines was measured cryogenically. Cu/Ti showed a higher residual resistance than Co/Cu/Ta/TaN and Cu/Ta/TaN, which indicates the presence of more impurities and a higher density of grain boundaries in Cu/Ti. Energy dispersive X-ray spectroscopy (EDX) analysis showed that a large amount of Ti doped into the Cu line segregated mostly at the grain boundaries on the Cu surface. It is suggested that Ti doped into a Cu line suppresses Cu diffusion through only the grain boundaries on the Cu surface. On the other hand, Co capping suppresses Cu diffusion through the entire Cu surface. As Cu/Ti improved EM lifetime significantly, the grain boundaries on the Cu surface are proposed to be a predominant diffusion path in EM. Since the density of grain boundaries probably increases on the Cu surface as interconnects shrink, suppressing the grain boundary diffusion on the Cu surface is highly effective to strengthen EM reliability.

The electromigration (EM) lifetime of Cu/porous low-k interconnects was evaluated by EM experiments in which the effect of back-flow stress was negligible. The EM lifetime of the downstream mode was reduced using a porous low-k film (SiOCH) as an intermetal dielectric (IMD) in comparison with using a SiO2 dielectric. The reduction in EM lifetime was observed only at low cumulative failure probability, considered as "early failure". The early failure was caused by the formation of a slit void under a via. It was found that the early failure was suppressed by placing a dummy metal near the metal/via contact that inhibited the formation of a slit void. The EM degradation of Cu/porous low-k interconnects is likely to be caused by the mechanical properties of porous low-k film. The dummy metal supports the porous low-k film near the metal/via contact, which leads to improved EM.

The total thermal budget of the wafer fabrication process for structures with multilevel Cu/low-k interconnects has been increasing, and its effect on the electromigration (EM) reliability of the lower-level interconnects has become a concern. The annealing of packaged samples including two-level interconnects for EM tests was shown here to be an effective method of evaluating the effect of the thermal budget on interconnects. EM lifetime was reduced by postannealing at the maximum process temperature (350 ?C), and its failure mode was a slitlike void generated at the interface between the via and the Cu line. It was shown that the degradation mechanism was related to the contact between the via and the Cu line and that postannealing may affect the stress at this contact by changing the stress in the dielectric interlayer film.

A 0.7-µm-pitch double level aluminum (Al) interconnection technology on a 1-µm-high step is established for 1-Gbit dynamic random access memories (DRAMs). A SiO2 film which has a high resistance to Al etching was used as the mask layer. 0.35-µm-width Al wirings were fabricated even on a 1-µm-high step. 0.2-µm-spaces (aspect ratio=2.5) between the taper shaped Al lines were filled, for the first time, by a plasma enhanced chemical vapor deposition (PECVD) fluorine doped silicon oxide (SiOF) film (ε=3.9). The SiOF film capped with the PECVD SiO2 film has enough stability for the process integration. It was confirmed that these technologies can be applied to a double level Al interconnection using a 0.3-µm-diameter tungsten (W) plug.