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Second harmonic generation (SHG) intensity, Raman scattering stress, photoluminescence and reflected interference pattern are used to determine the distributions of threading dislocations (TDs) and horizontal dislocations (HDs) in the c-plane GaN epitaxial layers on 6 inch Si wafer which is a structure of high electron mobility transistor (HEMT). The Raman scattering spectra show that the TD and HD result in the tensile stress and compressive stress in the GaN epitaxial layers, respectively. Besides, the SHG intensity is confirmed that to be proportional to the stress value of GaN epitaxial layers, which explains the spatial distribution of SHG intensity for the first time. It is noted that the dislocation-mediated SHG intensity mapping image of the GaN epitaxial layers on 6 inch Si wafer can be obtained within 2 h, which can be used in the optimization of high-performance GaN based HEMTs.

We simulate the static behavior of Ge-p/Si-n nanosheet complementary FETs (CFETs), where p-type FETs containing Ge nanosheet channels are stacked on top of n-type FETs containing Si nanosheet channels, and we investigate its relation to temperature while comparing it with that of Si-p/Si-n nanosheet CFETs, whose p-type FETs contain Si nanosheet channels. It is found that temperature rise has similar effects on the static characteristics of the two CFETs operating as inverters, although the variations in threshold voltage and noise margin with rising temperature are slightly smaller in the Ge-p/Si-n CFET inverter than in the Si-p/Si-n CFET inverter. The temperature rise effects are fully explained by the temperature dependence of material and carrier properties of Ge and Si.

The effect of HI and O2 plasma treatments on a Ge surface is studied by X-ray photoelectron spectroscopy. Ge oxide on a Ge surface can be effectively removed at room temperature by remote HI plasma in inductively coupled plasma reactive ion etching system without substrate bias. The re-oxidation of oxide-free HI plasma-treated Ge has been performed sequentially by O2 plasma. By utilizing HI and O2 plasma treatment cyclically, we have proved the viability of Ge digital dry etching. Ge digital dry etching by controlling the plasma power and the processing time of HI and O2 plasma treatments will be the building block for achieving Ge atomic layer etching.

Germanium-on-insulator (GeOI) structures with a surface orientation of (111) have been successfully fabricated by using low thermal budget epitaxial-lift-off (ELO) technology via direct bonding and selective etching. The material characteristics and transport properties of the Ge(111)OI structure have been systematically investigated through secondary-ion mass spectrometry, Raman spectroscopy, X-ray diffraction, high-resolution transmission electron microscope, and Hall measurement. The transferred Ge (111) layer remained almost intact from the as-grown epitaxial layers, indicating the benefits of ELO technology. The low thermal budget ELO technology demonstrated in this work is promising to integrate Ge channels with different surface orientations on Si (100) substrates for future monolithic 3D applications.

Scalable chemical vapor deposition (CVD) of two-dimensional semiconducting materials such as MoS2 and WS2 is a key technology for the application of these materials in real devices. In this work, we demonstrate the growth behavior of WS2 crystals from gaseous precursors, i.e. H2S and WF6, under alkali-metal-free conditions. The WS2 crystal growth exhibits layer-by-layer growth, and its behaviors, such as nucleation and lateral growth, are a thermally activated process: the temperature-dependent grain size and density are well fitted by the Arrhenius equation. The obtained WS2 crystal shows quality comparable to that obtained from metal oxides: the WS2 film shows sharp photoluminescence with a peak width of 54 meV and n-type field-effect transistor operation. Optimizing the growth conditions enabled us to obtain WS2 crystals with a grain size of ∼1.5 μm, which is the largest size ever reported for a transition-metal dichalcogenide grown by gas-source CVD without an alkali-metal promotor.

To enhance the feasibility of 2-dimensional transition metal dichalcogenides (TMDCs) channels in future nano-electronic and optoelectronic devices, a top gate device structure fabricated with very-large-scale-integration compatible process is mandatory. High-κ dielectric ZrO2 has been directly deposited on MoS2 through low-temperature atomic layer deposition (ALD) without any surface protection layers. The uniform growth of ZrO2 on MoS2 was confirmed to be caused by the physical adsorption, resulting in the suppressed interfacial oxidation and the reduced damage of monolayer (1L) MoS2 channel. Low thermal budget post-deposition annealing was found to be effective for reducing interfacial traps between ZrO2 and MoS2 interface, thus enhancing the device performances of 1L MoS2 nMOSFETs. Low capacitance equivalent thickness (CET) of ZrO2 of 2.3 nm has been achieved while maintaining decent device performance, indicating low-temperature ALD is promising for future TMDC top gate devices with a high-quality interface and thin CET.

Bilayer WSe2/MoSe2 van der Waals heterostructures have been directly grown on SiO2/Si substrates by 2-step chemical vapor deposition method. Bilayer nature with well aligned in-plane crystal orientation has been confirmed by Raman and transmission electron microscopy characterizations. Back gate transistors having bilayer WSe2/MoSe2 in the source side have been fabricated and high on/off ratio larger than 106 have been obtained. Gate-induced modulation of electron direct tunneling from source metal to the bottom MoSe2 layer and band to band tunneling from the valence band of WSe2 to the conduction band of MoSe2 can be an operation mechanism. Thanks to the drastic reduction of contact resistance due to the change of electron injection configuration, from edge to area injection at the source electrode, much higher on/off ratio with steeper switching was obtained in the WSe2/MoSe2 bilayer device as compared with the monolayer MoSe2 and WSe2 devices.

InGaAs photo field-effect transistors (PhotoFETs) integrated on a half-inch Si wafer have been demonstrated by means of layer transfer technology. According to the Raman measurement and scanning transmission electron microscopy (STEM), the InGaAs layer was transferred onto the half-inch Si wafer without degradation of crystal quality or introduction of strain. The optical performance of InGaAs photoFETs on Si, operating in shortwave infrared (SWIR) region was also investigated. The photoFETs on Si wafer show a responsivity of ~3 A/W at SWIR of 1550 nm with investigated range of bias. These results demonstrate InGaAs layer transfer technology is suitable for SWIR detectors on CMOS compatible platforms for monolithic integration.

Ultra-thin germanium-tin on insulator (GeSnOI) structure on Si substrate has been fabricated using the direct bonding and substrate etching techniques. This process involves the growth of GeSn layer on Ge (001) substrate followed by the deposition of ALD-Al2O3 on GeSn layer, the bonding of GeSn/Ge (001) substrate to a SiO2/Si substrate, and the removal of the Ge substrate. Using the bevel substrate etching technique, we prepared different GeSnOI structures, whose thicknesses gradually varied from 50 to 0 nm, in one sample. We investigated the thickness dependence of the material quality of the fabricated structure via micro-Raman spectroscopy; the strong Ge–Ge peaks are observed in a few nm thick GeSnOI structure, suggesting high quality of the fabricated GeSnOI structure and the enhancement of Raman intensity of the Ge–Ge peak in the ultra-thin GeSnOI structure of thickness less than 10 nm is attributed to the quantum size effect.

Ultra-thin-body (UTB) germanium-on-insulator (GeOI) substrates with Si-passivated back interfaces have been fabricated by using advanced epitaxial-lift-off (ELO) technology. Performance of UTB GeOI p-MOSFETs with body thickness (T body) in the 4–16 nm range has also been characterized. Si-passivated back interfaces have been fabricated and found to be effective in mitigating the unpleasant hole-mobility degradation in the UTB GeOI regime owing to the suppression of the back interface scattering.

The parasitic resistance (Rpara) of Ge p-channel metal–oxide–semiconductor field-effect transistors (p-MOSFETs) fabricated by ion implantation after germanidation (IAG) has been investigated by varying the drive-in annealing temperature. The lowest Rpara of 835 Ω µm was achieved after 450 °C drive-in annealing for 1 min. Boron segregation between NiGe and Ge induced by drive-in annealing has advantages in forming an abrupt metallic source/drain (S/D) junction and contributes to the decrease in Rpara. The appropriate process window for fabricating Ge p-MOSFETs by IAG was also given. IAG, a pathway for introducing a Ge channel into CMOS technology beyond the 10 nm node, was proved to be effective for reducing Rpara.

In-situ ultrahigh-vacuum-deposited Y2O3 2–3-monolayer-thick on freshly grown In0.53Ga0.47As with an Al2O3 cap were employed as a gate dielectric. A low interfacial density of states of (8–9)×1011 eV-1 cm-2 near the midgap has been measured using the conductance method. The strong Y2O3/InGaAs interfacial bonding, revealed using X-ray photoelectron spectroscopy, enables attainment of an atomically smooth interface with 750 °C annealing. Low subthreshold swing of 97 mV/decade, high drain current of 1.5 mA/µm, high transconductance of 0.77 mS/µm, and field-effect mobility of 2,100 cm2 V-1 s-1 were achieved in a self-aligned inversion-channel InGaAs metal–oxide–semiconductor field-effect-transistor of 1 µm gate length.