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All-inkjet-printing of transistors has received much attention for low cost and flexible integrated circuits. However, most flexible field-effect transistors (FETs) based on the emerging two-dimensional materials suffer from the high cost of substrate and electrode materials. The requirements for high-temperature synthesis and precise control in processing add another layer of complexity. To overcome these issues, low-cost flexible paper-based MoS2 FETs were fabricated by inkjet printing of MoS2 channel materials on paper. Additionally, we proposed and achieved the mask-less and low-temperature formation of source and drain electrodes on paper using in-situ selective-area copper reduction. A low sub-threshold swing of 80 mV/dec, high on/off ratio of 105, and very high turn-on current (Ion) of 200 μA of the paper-based flexible MoS2 FETs were demonstrated using the proposed low-cost and facile all-inkjet-printing technique. The all-inkjet-printing technique assisted by in-situ copper reduction opens new opportunities for low-cost and batch fabrication of paper-based electronic devices in ambient conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a visual management scheme of medical things with a color-change radio frequency identification (RFID) tag. The color-change RFID tag employs a specific RFID tag integrated circuit (IC) and a laminated pH-indicating paper. The IC has energy harvesting and switched ground functions, which enable it to generate electricity to the laminated pH-indicating paper. This phenomenon causes electrolysis of NaCl solution absorbed in the laminated pH-indicating paper. Electrolysis generates alkaline matter to change the color of the pH-indicating paper. This paper gives a new and sensitive structure of the laminated pH-indicating paper. The proposed advanced color-change RFID tag with new laminated pH-indicating paper succeeds in changing its color noticeably at a 1 m distance using an RFID reader radiating 1 W radio waves. The color change was observed 3–5 s after starting radio wave irradiation. The results of this experiment also confirm that the changed color can be held for over 24 h. Furthermore, two demonstrations of the visual management system of medical things (patient clothes and sanitizers) are presented. [ABSTRACT FROM AUTHOR]

This special issue contains papers obtained through open call-for-papers as well as from the selected extended versions of the papers presented in the 4th International Conference "2021 Devices for Integrated Circuit (DevIC)", held at Kalyani Government Engineering College from May 19-20, 2021. This special issue publishes a collection of papers that were submitted to the Journal of Materials Science: Materials in Electronics on the theme of experimental electronic and optical materials for nano-dimensional device applications. [Extracted from the article]

Origami, an ancient form of papercraft, provides a way to develop functional structures for engineering applications. In this paper, we report an approach to design and manufacture a stretchable circuit board (SCB) with origami structures. The benefits of developable, flat-foldable, and rigid-foldable origami-based structures as SCBs are discussed, and a representative structure, Miura fold (or Miura-ori), is chosen to be investigated. Under the constraints induced by the mounted components' dimensions, the Miura-ori structures for specific applications can be defined. We propose three methods for better fabrication, including direct folding, stiffness modification, and kirigami enhancement, to improve a planar sheet's foldability. A wearable ECG (electrocardiogram) system based on MO-SCB (Miura-ori enabled SCB) technology is built, and the stretchable portion is made of commercial FPCBs (flexible printed circuit board), providing desired stretchability and reliability. The proposed technology routine is compatible with industrial production and may pave the application of stretchable electronics. [ABSTRACT FROM AUTHOR]

This paper introduces a novel, cost-effective solution designed to achieve large absorption bandwidth within the THz spectrum employing a miniaturized, single-layer metamaterial structure. The designed structure features a single circular ring composed of an ohmic resistive sheet with notably higher sheet resistance than traditional metallic resonators. This distinctive design is implemented on a lossy dielectric polyimide substrate with a backing of metallic gold. Our developed absorbing structure demonstrates the capability to achieve a substantial absorption bandwidth ranging from 3.78 to 4.25 THz, maintaining a consistent absorption rate of over 90%. Moreover, we conducted an analysis to assess its absorption performance under various sheet resistance values within the top layer. Additionally, we characterized its angular stability and polarization insensitivity through oblique incident and polarization angle analysis. Finally, an RLC circuital and interference theory approach is adopted to justify its simulated results. The proposed absorber shows potential for a broad spectrum of applications, encompassing communication, imaging, and diverse integrated circuits operating within the THz band. [ABSTRACT FROM AUTHOR]

This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node. [ABSTRACT FROM AUTHOR]

The dielectric loss of Cu with high thermal conductivity is large at high frequency, which cannot meet the performance requirements in high-integrated circuits. There is an urgent need for materials to reduce its dielectric loss. In this paper, the thermal conductivity and dielectric properties of the AlN coating-Cu substrate system were controlled by changing the N2 pressure. The results showed that the crystallinity of hcp-AlN in AlN coating increased significantly when the proportion of N2 pressure was increased. With the increase of the N2 pressure, the particle size on the surface and the roughness of the coating improved. The AlN coating prepared at high N2 pressure had high dielectric constant and low dielectric loss at high frequency compared to those of the coatings prepared at low N2 pressure. At the same time, the AlN coating prepared under high N2 pressure on the Cu substrate did not decrease the thermal conductivity of Cu substrate. The AlN-Cu system prepared in this paper had high thermal conductivity and good dielectric properties, providing theoretical guidance for integrated circuit packaging and capacitor applications. [ABSTRACT FROM AUTHOR]

In this paper the design of power management integrated circuits for the energy harvesting of ultrasound waves in implanted biomedical devices is addressed. In particular, the paper focuses on the main building block of the power conversion stage which is represented by the AC/DC converter. After an in-depth analytical description of cross-coupled passive and active rectifiers, a detailed design procedure for the common-gate comparator is introduced. Then a comparison between the different discussed topologies is carried through simulation results using a 28-nm standard CMOS technology. The results provide useful design guidelines in choosing the best topology according to the design specifications. [ABSTRACT FROM AUTHOR]

The piezoelectric coupling principle is widely used (along with capacitive coupling and piezoresistive coupling) for MEMS accelerometers. Piezoelectric MEMS accelerometers are used primarily for vibration monitoring. Polymer piezoelectric MEMS accelerometers offer the merits of heavy-metal-free structure material and simple microfabrication flow. More importantly, polymeric piezoelectric MEMS accelerometers may be the basis of novel applications, such as fully organic inertial sensing microsystems using polymer sensors and organic integrated circuits. This paper presents a novel polymer piezoelectric MEMS accelerometer design using PVDF films. A simple and rapid microfabrication flow based on laser micromachining of thin films and 3D stereolithography was developed to fabricate three samples of this design. During proof-of-concept experiments, the design achieved a sensitivity of 21.82 pC/g (equivalent open-circuit voltage sensitivity: 126.32 mV/g), a 5% flat band of 58.5 Hz, and a noise density of 6.02 µg/√Hz. Thus, this design rivals state-of-the-art PZT-based counterparts in charge sensitivity and noise density, and it surpasses the performance capabilities of several commercial MEMS accelerometers. Moreover, this design has a 10-times smaller device area and a 4-times larger flat band than previous state-of-the-art organic piezoelectric MEMS accelerometers. These experimentally validated performance metrics demonstrate the promising application potential of the polymeric piezoelectric MEMS accelerometer design presented in this article. [ABSTRACT FROM AUTHOR]

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization. [ABSTRACT FROM AUTHOR]

Research on artificial neural network computing based on conventional integrated circuit chips has made significant progress, but it faces technical bottlenecks such as reduced energy consumption, computing speed, and efficiency. So, it is seeking integrated chips based on optical interconnections to solve the current dilemma. Fortunately, the small size and very localized graphene surface plasmon waves offer the possibility of optical integrated chips. In this paper, we propose a graphene-based one-bit optical numerical comparator. The comparator is located on the top of a 0.4-μm2 rectangular dielectric layer, mainly consisting of Y-shaped graphene nanoribbons. The on/off effect of the graphene nanoribbons is achieved by applying an external voltage to change the chemical potential energy of the graphene switching bands. The proposed optical numerical comparator with 9.55-μm TM mode light achieves a minimum extinction ratio of 31.12 dB and amplitude modulation of 0.77 dB, as shown by the finite-difference time-domain (FDTD) method. Compared with the current optical numerical comparators, it has the advantages of a high extinction ratio, small size, low loss, and high stability. In addition, the effect of process deviation of graphene nanoribbons on the reliability of the designed optical numerical comparator is analyzed by simulation. It is beneficial to developing integrated photonic devices and has some significance for developing ultra-high-frequency and integrating artificial neural network computing. [ABSTRACT FROM AUTHOR]

Medical implants and portable wireless sensors are the most serious of biomedical applications due to the dependence on limited battery lifetime. Consequently, energy efficiency integrated circuits designs must be put to higher attention. A particular distinguishing contribution of this paper is its focus on the power consumption that affects battery life and the heat dissipated for biomedical applications. This paper demonstrates a power-efficient implementation of analog-to-digital converter (ADC) based on voltage-controlled oscillator (VCO) to convert the collected analog vital signs into digital data for digital signal processing. The current-starved scheme is employed to implement the VCO efficiently with five-stage which leads to high savings in power and area. D-flip flop (D-FF) scheme is proposed to simplify the hardware architecture of the proposed reset counter. The proposed architecture is implemented with 130 nm CMOS technology and it can perform conversion of analog input signal to digital output using a straightforward hardware structure. The proposed VCO-based ADC achieves improvement in energy saving. Simulation results confirm that this work attains a power dissipation of 0.257 mW and active area of 0.007 mm2, and a very good Walden FOMW of 125 dB. The proposed methodology can implement any number of bits of the ADC by using the appropriate voltage-controlled oscillator with the convenient reset counter. [ABSTRACT FROM AUTHOR]

This paper designs a novel E-plane waveguide magic-T in 220 GHz and develops a high-power solid-state power amplifier (SSPA) operating at 210–230 GHz in combination with eight InP high electron mobility transistor terahertz monolithic integrated circuits (TMICs). The 8-way divider-combiner network is composed of low-loss WR-4 novel E-plane waveguide magic-T. The matching load of waveguide magic-T is the air outside the waveguide module, which is connected to the pyramidal horn antenna of WR-4 waveguide to WR-10 waveguide. A monolithically integrated dipole-to-waveguide transition eliminates the need for wirebonding and additional substrates. The low-loss corporate power combining and low-loss dipole-to-waveguide transition achieve high-power combining efficiency of SSPA. The hydroxyl-iron is placed in the upper cavity of TMIC to prevent the cavity from resonance. The SSPA module demonstrated small-signal gain ≥ 10 dB from 210 to 229 GHz. The saturated output power was > 100 mW from 215 to 227 GHz and peak output power of 110 mW with 83% power combining efficiency at 220 GHz. [ABSTRACT FROM AUTHOR]

Semiconductor wafer manufacturing relies on the precise control of various performance metrics to ensure the quality and reliability of integrated circuits. In particular, GaN has properties that are advantageous for high voltage and high frequency power devices; however, defects in the substrate growth and manufacturing are preventing vertical devices from performing optimally. This paper explores the application of machine learning techniques utilizing data obtained from optical profilometry as input variables to predict the probability of a wafer meeting performance metrics, specifically the breakdown voltage (Vbk). By incorporating machine learning techniques, it is possible to reliably predict performance metrics that cause devices to fail at low voltage. For diodes that fail at a higher (but still below theoretical) breakdown voltage, alternative inspection methods or a combination of several experimental techniques may be necessary. [ABSTRACT FROM AUTHOR]

Recently, interest in programmable photonics integrated circuits has grown as a potential hardware framework for deep neural networks, quantum computing, and field programmable arrays (FPGAs). However, these circuits are constrained by the limited tuning speed and large power consumption of the phase shifters used. In this paper, we introduce the memresonator, a metal-oxide memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter. These devices are capable of retention times of 12 hours, switching voltages lower than 5 V, and an endurance of 1000 switching cycles. Also, these memresonators have been switched using 300 ps long voltage pulses with a record low switching energy of 0.15 pJ. Furthermore, these memresonators are fabricated on a heterogeneous III-V-on-Si platform capable of integrating a rich family of active and passive optoelectronic devices directly on-chip to enable in-memory photonic computing and further advance the scalability of integrated photonic processors. Photonic integrated circuits have grown as potential hardware for neural networks and quantum computing, yet the tuning speed and large power consumption limited the application. Here, authors introduce the memresonator, a memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter to address these limitations. [ABSTRACT FROM AUTHOR]

Encryption chips are specialized integrated circuits that incorporate encryption algorithms for data encryption and decryption, ensuring data confidentiality and security. In China, the domestic SM4 algorithm is commonly utilized, as opposed to the international AES encryption algorithm. These widely implemented encryption standards have been proven to be difficult to crack through crypt analysis methods Currently, power consumption side-channel attacks are the most prevalent method. They involve capturing power consumption data during the encryption process and subsequently recovering the encryption key from this data. The two leading methods are Differential Power Analysis (DPA) and machine learning techniques. DPA does not necessitate prior knowledge but relies heavily on the number of power consumption curves. With only 50 power consumption data points, the accuracy is a mere 80%. Machine learning methods require prior knowledge, achieving an accuracy rate above 95% with only 30 power traces, albeit with training times typically exceeding 15 min. In this paper, a distributed energy analysis attack approach was presented based on Correlation Power Analysis (CPA). The power consumption data was divided into 16 subsets, with each subset corresponding to 8 bytes of the key. By training each subset separately, the 8-byte key's corresponding power consumption data is reduced to only 100 dimensions, resulting in a 76% decrease in cracking time and a 3% improvement in cracking accuracy rate.This article also trains a more complex 256 classification model to directly crack the final key, achieving a success rate of 28% in cracking 128-bit passwords with only 1 power trace [ABSTRACT FROM AUTHOR]

B Abstract: b Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. [Extracted from the article]

This paper proposes an inductor-less D-latch. In the proposed D-latch, negative feedback is used that makes input impedance appears to be inductive for the high-frequency input signal. The bandwidth is increased by around 23% due to this effect. Two applications are shown in this paper to verify the proposed latch operation: a pseudo-random binary sequence (PRBS) generator and a serializer. The speed of the PRBS generator and serializer has improved by 15.8% and 23% using the proposed latch, respectively. The post-layout simulation results in 90 nm CMOS technology with a power supply of 1 V prove the concept. To study functional correctness and scalability of the proposed architecture to lower technology nodes, 22 nm PTM model is used and verified the correct operation of the proposed architecture. [ABSTRACT FROM AUTHOR]

In this paper, a programmable low-power analog front-end (AFE) integrated circuit (IC) for biomedical signal monitoring systems is presented. The whole system includes four parts, instrumentation amplifiers (IA), programmable gain amplifiers (PGA), programmable bandwidth filters (PBF) and successive approximation register analog-to-digital convertors (SAR ADC). The proposed IA employs a pseudo-differential structure to enhance the input impedance of the system. A novel hybrid bandwidth extension technology is introduced in the proposed PGA to correct the low-frequency distortion and improve the low-frequency bandwidth. In the design of PBF, the current steering technology is applied to achieve an area-efficient and energy-efficient architecture. Furthermore, a novel efficient switching scheme and a self-calibration dynamic element matching method are presented in the design of SAR ADC to reduce the power consumption and eliminate the effect of capacitor mismatch. In 0.18 μm CMOS technology, this AFE IC consumes 46.8 μW and occupies 0.36 mm2. It achieves a variable gain from 40.4 to 55.1 dB under different modes designed for different biomedical signals. The spurious-free dynamic range and signal-to-noise plus distortion ratio of the proposed SAR ADC are 71.3 and 53.3 dB, respectively, along with a figure of merit of 0.18 pJ/conv. [ABSTRACT FROM AUTHOR]

The article discusses research by Jan Schroers and colleagues at Yale University exploring a class of amorphous metals called bulk metallic glasses (BMG). Topics include the difficulties in finding a low-cost yet durable means of molding tiny components such as those used in computer chips, how Schroers and colleagues were able to mold BMGs at nanoscale dimensions, and its potential application in the semiconductor industry.

Since 2007, methods that utilize side-channel data to detect hardware Trojan (HT) problems have been widely studied. Machine learning methods are widely used for hardware Trojan detection, but with the development of integrated circuits (ICs), better results are usually obtained using deep learning methods. In this paper, we propose an architecture inspired by Residual-Block and Dense-Block and combine it with SE Attention Mechanism, which we named the Res-Dense-SE-Net network. By combining residual connectivity, dense connectivity, and attention mechanism, the Res-Dense-SE-Net network can enjoy the advantages of these three network architectures at the same time, which can improve the expressiveness and performance of the model. The Res-Dense-SE-Net network can capture the key features in the image better, and it can solve the problems of gradient vanishing and feature transfer efficiently, which can in turn improve the classification accuracy and the generalization ability of the model. Based on the publicly available AES series of hardware Trojans from TrustHub and the publicly available hardware Trojan-side channel data by Faezi et al., we evaluate the effectiveness of the method proposed in this paper. The experimental results show that when a single Trojan exists, the method proposed in this paper has a high accuracy rate; and when multiple types of hardware Trojans exist at the same time and need to be categorized, the categories of hardware Trojans can also be effectively identified, and the categorization accuracy is high compared with the existing deep learning methods. [ABSTRACT FROM AUTHOR]

Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]

The author reflects on model based high level programming of embedded systems. He states that embedded systems are mostly used in automotive and avionics industries. He further states that most successful representatives of this trend of putting logic and mathematics behind design automation in embedded systems are synchronous languages. He argues that model-based programming is making its way in other fields of software engineering too

The Cu–Fe–P alloy is the mainstream material of IC lead frame at present, which plays a key role in electrical signal transmission and mechanical fixation between bearing chip and external circuit board. With the development of integrated circuits toward high integration and extreme miniaturization, copper alloy strips for lead frames are required to have excellent electrical and mechanical properties, as well as excellent softening resistance under short-term high temperature service conditions. In this paper, the effects of annealing temperature (300, 400, 500 °C) on texture orientation and strength, and precipitates characteristics (morphology, size, interfacial relationship, etc.) of as-cold rolled Cu–2.18Fe–0.03P alloy were studied by means of EBSD and TEM. It is found that annealing at low temperature does not change the texture type, but it affects the texture strength compared with the as-cold rolled alloy. Cubic texture {001} < 100 > and R-type texture {111} < 112 > appear in the annealed alloy. The texture strength increases with the increase in annealing temperature, and the preferred orientation is more obvious. In addition, we found that there are two kinds of precipitated phases in the copper matrix, namely spherical α-Fe phase and irregular Fe3P phase. We further find out the coexistence state of the two precipitates and their evolution with annealing temperature. With the increase in annealing temperature from 300 to 500 °C, the size of the main strengthening phase α-Fe increases and the orientation relationship between α-Fe phase and the matrix changes from coherent to semi-coherent. On this basis, we found that the decrease in texture strength, the change of coherence relationship of α-Fe phase, and the decrease in dislocation barrier are the main factors leading to the softening of Cu–2.18Fe–0.03P alloy at high temperature. The research results of this paper are meaningful in guiding the development of high-end copper alloy strip in the field of electronic information. [ABSTRACT FROM AUTHOR]

This paper introduces a novel, cost-effective solution designed to achieve large absorption bandwidth within the THz spectrum employing a miniaturized, single-layer metamaterial structure. The designed structure features a single circular ring composed of an ohmic resistive sheet with notably higher sheet resistance than traditional metallic resonators. This distinctive design is implemented on a lossy dielectric polyimide substrate with a backing of metallic gold. Our developed absorbing structure demonstrates the capability to achieve a substantial absorption bandwidth ranging from 3.78 to 4.25 THz, maintaining a consistent absorption rate of over 90%. Moreover, we conducted an analysis to assess its absorption performance under various sheet resistance values within the top layer. Additionally, we characterized its angular stability and polarization insensitivity through oblique incident and polarization angle analysis. Finally, an RLC circuital and interference theory approach is adopted to justify its simulated results. The proposed absorber shows potential for a broad spectrum of applications, encompassing communication, imaging, and diverse integrated circuits operating within the THz band. [ABSTRACT FROM AUTHOR]

Explores the progress and emerging trends in the kinetic aspects of analytical chemistry. Kinetics techniques for analytical chemistry; Millisecond kinetics on microchips; Characteristics of an ideal biosensor; Outlook for kinetic approaches.

This paper presents a compact and efficient integrated interface circuit for piezoelectric energy harvesting. While state-of-the-art interface circuits require either an external inductor or a significant number of additional capacitors to achieve high voltage flip and thus improve power efficiency, the proposed Full Active Rectifier on Flipping Capacitor (FAR-FC) is based on a reduced set of flipping capacitors and an active rectifier to efficiently flip the voltage across the piezoelectric transducer. In addition, this optimized SSHC circuit reaches better power efficiency when the piezoelectric transducer operates under low mechanical excitation, i.e. when the open-circuit voltage of the piezoelectric transducer is V o c = 1 V , while usually V o c ≥ 2 V in literature. Furthermore, the FAR-FC supports piezoelectric transducers with higher inherent capacitance values compared to those usually reported in literature, which makes the circuit potentially suitable for a larger variety of applications. The interface circuit was designed and fabricated in a 0.35 μm CMOS process. Measurement results show that the voltage flip efficiency goes up to 90 % . It also reveals that the proposed FAR-FC circuit achieves power performance up to 5.64 × higher than a conventional full-bridge rectifier. [ABSTRACT FROM AUTHOR]

This paper presents the design and numerical investigation of tunable, ultra-compact, and highly-efficient plasmonic filters based on stepped impedance resonators (SIRs). The proposed devices are realized in metal–insulator-metal (MIM) plasmonic waveguide systems and exhibit more degrees of freedom and high flexibility to design resonator-based devices, thanks to the SIRs. The principle of conventional SIRs is discussed in terms of equivalent circuit model and characteristic impedance. Among the three proposed plasmonic filters, one of them acts as a short-wavelength, while the other two nanostructures work as long-wavelength cut-off filters at near-infrared region (NIR) and telecom wavelengths. Simulation results are carried out by a finite element method (FEM)-based solver and indicate that the cut-off wavelengths of the proposed resonators found to be at 1187 nm, 1265 nm, and 999 nm, respectively, can be easily tuned by modulating their structural parameters. In addition to the mentioned remarkable properties of the designed structures including the size which are found to be 500 nm × 310 nm, 350 nm × 285 nm, and 210 nm × 195 nm, respectively, the simple structures of the proposed topologies facilitate their fabrication process. Therefore, the suggested devices can contribute to the development of miniaturized, tunable, and efficient optical components for photonic integrated circuits (PICs) applications and in optical wireless communication systems. [ABSTRACT FROM AUTHOR]

In this paper, four individual structures based on graphene-plasmonic nano combinations are proposed for detection of corona viruses and especially COVID-19. The structures are arranged based on arrays in the shapes of half-sphere and one-dimensional photonic crystal formats. The half-sphere and plate shaped layers are made of Al, Au, SiO2 and graphene. The one-dimensional photonic crystals lead the wavelength and peak corresponding to the absorption peak to lower and higher amounts, respectively. In order to improve the functionality of the proposed structures, effects of structural parameters and chemical potentials are considered. A defect layer of GZO is positioned in the middle of one-dimensional photonic crystal layers to shift the absorption's peak wavelength to the appropriate wavelength range for diagnosing corona viruses (~300 nm to 600 nm). The last proposed structure is considered as a refractive bio-sensor for detection of corona viruses. In the final proposed structure (based on different layers of Al, Au, SiO2, GZO and graphene), corona viruses are considered as the biomolecule layer and the results are obtained. The proposed bio-sensor can be a good and functional candidate for detection of corona viruses and especially COVID-19 in photonic integrated circuits with the satisfying sensitivity of ~664.8 nm/RIU (refractive index unit). [ABSTRACT FROM AUTHOR]

The Internet of Things is gaining popularity throughout the world. With the growth of digital communication, healthcare 4.0 are being implemented by many businesses industry in order to establish a more resilient, competent, and intelligent smart healthcare system. Healthcare monitoring services are the part of smart healthcare system. These types of monitoring systems are mainly based on the Internet of Things (IoT). IoT helps to integrate multiple sensors and objects that can directly communicate with each other without human intervention. This type of IoT based systems are vulnerable to different adversarial threats such as cloning attack, impersonation attack etc. Hence medical IoT device authentication is essential in smart healthcare to verify user legitimacy. One way to verify user legitimacy is using physical unclonable function (PUF). The PUF protects sensor nodes from tampering, cloning attack. In this paper, we have proposed a lightweight PUF based authentication mechanism for embedded IoT devices in e-healthcare system. The proposed authentication technique helps to authenticate IoT sensor nodes which are responsible for transmitting sensitive health data in a health monitoring system. The performance comparison shows that the protocol is efficient with high through put and low computational load. The security analysis of the authentication scheme shows it would resist different types of network attacks. The proposed authentication provides a facility that no one except that the primary users can have access to the raw challenge response pair of integrated PUF circuits so that adversary will unable to build another same PUF model. Also the success probability is 2 - 76 for recovering the transformed 128 bit challenge and responses. [ABSTRACT FROM AUTHOR]

The transformer is an important component of electrical engineering for many applications including those for integrated circuits. For integrated circuit applications, the use of a synthetic transformer has been recognised to be a viable option for a number of applications. This paper presents two new designs of electronically-controllable CMOS active transformers. The first preposition is based upon a capacitive T-network embedded between two active CMOS gyrators each of which has been obtained by a parallel back-to-back connection of one non-inverting and other inverting electronically-controllable CMOS transconductor. This circuit requires thirty-two MOSFETs, all operating in saturation region. The second design simulates an inductive T-network using two CMOS electronically-controllable floating inductors and one electronically-controllable CMOS grounded inductor thereby employing eighty MOSFETs. The first design offers the advantage of realising a step up as well as step down transformer by appropriate selections of the transconductances of two transconductors. The second design although uses a larger number of MOSFETs than the former but has the advantage of using three grounded capacitors which is a desirable from the view point of IC implementation. It may also be mentioned that using more MOSFETs does not increase layout area significantly since the capacitors require more layout area than all the MOSFETs put together. The workability of both the designs, along with their various performance characteristics and non-ideal analysis, has been well corroborated by computer simulations using SPICE software using 0.18 µm CMOS technology parameters. The application of the proposed circuits in the design of double tunned band pass filter has also been shown and its workability too has been validated by computer simulations using SPICE software. [ABSTRACT FROM AUTHOR]

Spotty error-correcting codes are used for byte error correction in computer memory chips. In this paper, we study m-spotty weight enumerators of codes over the mixed alphabet Z 2 (Z 2 + u Z 2) , u 2 = 0 . We have proved a MacWilliams type identity for Hamming weight enumerators of the m-spotty byte error-correcting Z 2 (Z 2 + u Z 2) -linear codes. A Gray map is defined, using which another identity is derived from the above-mentioned MacWilliams type identity. We have also derived Pless type power moments for the spotty weight enumerators of the Gray images of Z 2 (Z 2 + u Z 2) -linear codes. A Griesmer type bound has been derived for the Gray images of byte error-correcting codes over Z 2 (Z 2 + u Z 2) . Examples have been given to illustrate the main results of the paper. [ABSTRACT FROM AUTHOR]

The growing complexity of integrated circuits (ICs) brings expensive manufacturing test cost. Adaptive testing becomes an important way to save test cost by predicting die quality to reduce the actual test content. However, reducing test items often results in unacceptable levels of test quality degradation. An adaptive testing method is proposed in the paper to reduce test cost while guaranteeing test quality. Two quality predictors are trained with a subset of test items and spatial information for subsequent decisions. The dies are clustered according to the prediction results, and the clustering results are graded. The distribution of the different grade classes determines the die quality of each grade. Experimental results using fabricated wafers and the associated test data show that the proposed method reduces more than 42% of test items, and can achieve better test quality, reducing test escapes and yield losses by more than 90% in the Circuit Probing test (CP). [ABSTRACT FROM AUTHOR]

This paper continues the research on the circuit synthesis problem for a multiplexer function of logic algebra, which is a component of many integrated circuits and is also used in theoretical study. The exact value of the depth of a multiplexer with select lines in the standard basis is found under the assumption that the conjunction and disjunction gates are of depth 1 and the negation gate is of depth 0; the depth equals if . Thus, it follows from previous results that the exact depth value equals for all positive integers such that either or . Moreover, for , this value equals 2, and for , it equals either or . Similar results are also obtained for a basis consisting of all elementary conjunctions and elementary disjunctions of two variables. [ABSTRACT FROM AUTHOR]

This paper reports the design and numerical results of three new extremely compact and efficient flat-top band-pass plasmonic filters operating in the near-infrared region. The proposed structures are realized in metal–insulator-metal plasmonic waveguides based on stub, tilted T-junction and right-angle trapezoid configurations. A built-in parameterized genetic algorithm is applied to maximize the transmission efficiency, while at the same time contributing to shrinking down the size of the device structures. It is shown that the tunability of the optical filters can be realized by modulating their structural parameters to gain control over the band-pass filtering wavelengths. Numerical calculations are conducted based on the finite element method of CST Microwave Studio and demonstrate that the suggested ultra-compact plasmonic waveguide filters offer wide bandwidths of more than 270 nm, 424 nm, and 289 nm, with transmission efficiencies of higher than 80%, 74.2%, and 74.3%, respectively. The sizes of the proposed wavelength filters are 490 nm × 575 nm, 350 nm × 180 nm, and 420 nm × 150 nm, respectively, which make them attractive candidates for applications in high density photonic integrated circuits (PICs). As a result, because of the promising characteristics of the proposed topologies such as their high efficiency, compact size, tunability, and simple structure they may find applications in on-chip integration, laser technology, and multi-photon fluorescence. [ABSTRACT FROM AUTHOR]

In this paper, ultra-compact, high isolation-ratio optical isolators for use in wavelength-division multiplexing networks are presented. The isolator is composed of two parts, including a straight waveguide and a resonator. The performance of the isolator is investigated for two kinds of disk and ring resonators. The structure is based on the metal–insulator–metal configuration in which the metal parts are of gold and the insulator parts are of a magneto-optical material. The effecting parameters, including the dimensions of the disk/ring resonator, the gap between the waveguide and the resonator, and the waveguide material are comprehensively studied using the finite-difference time-domain method. By changing the geometrical variables and materials, the isolation ratio of the disk-and ring-based isolators can reach up to 33.47 dB and 29.06 dB, respectively. The footprint of both isolators is less than 1 μm2. The proposed isolators can be used in photonic integrated circuits due to their ultra-compact footprint, high isolation ratio, and CMOS-compatible structures. [ABSTRACT FROM AUTHOR]

Silicon (Si) waveguide crossing serves as an enabling technology for dense Si photonic integrated circuits. Efficient crossing designs significantly boost the performance of photonic devices with many crossings. In this paper, several fundamental optical logic functions, such as XOR, AND, OR, NOT, NOR, NAND, and XNOR, are reported at 1550 nm telecom wavelength using direct Si waveguide crossing. The proposed scheme is made up of three input waveguides and one output waveguide arranged in the shape of the symbol ' + ' with a microring resonator in the middle. The operation of the specified logic functions depends on the constructive and destructive interferences generated by the phase differences between the incident optical beams. Using the contrast ratio and amplitude modulation metrics, the performance of the target logic operations is evaluated. Additionally, it is investigated and assessed how much the critical operating parameters affect the spectrum transmission. The proposed waveguide-based scheme can achieve better performance compared to other reported designs of similar nature, according to simulation outcomes derived using Lumerical FDTD. [ABSTRACT FROM AUTHOR]

Although analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin–orbit torque (SOT) switching mechanism is designed, fabricated and characterized. In this ADC, each MTJ plays the role of a comparator whose threshold is set by the engineering of the heavy metal (HM) width. Such an approach can reduce the ADC footprint. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we propose the design of a track and hold (T&H) integrated circuit that is able to sample an incoming high-speed PAM4 signal and feed it to an analog to digital converter (ADC). This building block acts as a front-end in optical transceivers carrying sensitive data, where power consumption and cost are a primary concern. The proposed architecture is discussed in detail and a design approach based on the switched capacitor architecture is examined and simulated. Parasitic based capacitance is utilized to hold the signal, and post-layout simulation shows a low power consumption of 42 mW while sampling a 1 GS/s PAM4 signal at 200 MSps (Mega-samples per second). Our circuit has a 10 times lower power consumption compared to a similar implementation in BiCMOS and a comparable power consumption to similar CMOS implementations but with a higher output voltage swing and far less smaller area. Our circuit is designed for PAM4 signals but can be used for NRZ as well, which is a first of its kind in sample and hold circuits targeting serial modulated signals such as PAM4. [ABSTRACT FROM AUTHOR]

This paper presents design and numerical investigations of an ultra-compact, and highly-efficient plasmonic absorber based on metal–insulator–metal waveguides. The proposed device offers multiple narrow-band absorption at visible and near-infrared wavelengths with peak absorbance between 81 and 100%. The finite element method has been used to simulate the proposed structure. The simulation results show that the resonance wavelengths can be easily modulated by tuning the coupling distances between the input and output ports and the triangular resonators. To find the optimized size of the proposed structure, maximize its efficiency, and attain narrow-band resonances, a parameterized genetic algorithm has been used. Taking into account the obtained notable specifications of the proposed structure, it can contribute to the development of miniaturized and efficient optical components for photonic integrated circuits. [ABSTRACT FROM AUTHOR]

Reduction of the crosstalk (CT) between contiguous photonic components is still a big challenge in fabricating high packing density photonic integrated circuits (PICs). Few techniques to accomplish that goal have been offered in recent years but all in the near-IR region. In this paper, we report a design for realizing a highly efficient CT reduction in the MIR regime, for the first time to the best of our knowledge. The reported structure is based on the silicon-on-calcium-fluoride (SOCF) platform with uniform Ge/Si strip arrays. Using Ge strips shows better CT reduction and longer coupling length (Lc) than the conventional Si based devices over a wide bandwidth in the MIR region. The effect of adding a different number of Ge and Si strips with different dimensions between two adjacent Si waveguides on the Lc and hence on the CT is analyzed using both full vectorial finite element method and 3D finite difference time domain method. An increase in the Lc by 4 orders of magnitude and 6.5 times are obtained using Ge and Si strips, respectively, compared to strips-free Si waveguides. Consequently, crosstalk suppression of − 35 dB and − 10 dB for the Ge and Si strips, respectively, is shown. The proposed structure is beneficial for high packing density nanophotonic devices in the MIR regime, such as switches, modulators, splitters, and wavelength division (de)multiplexers, which are important for MIR communication integrated circuits, spectrometers, and sensors. [ABSTRACT FROM AUTHOR]

Knowledge of the positions, polarizations, and local environment effect on the light coupling efficiency from a single photon source to an optical waveguide is critically important for the development of an integrated single photon emitter. In this paper, we contribute to a holistic investigation on the dependence of the wideband coupling efficiency and Purcell enhancement factor on the emitter positions, orientations, refractive indices and geometrical parameters of SiNx waveguides for broadband CMOS-compatible quantum photonic integrated circuits using FDTD analysis in very near-infrared ranges. The obtainable spectral range with respect to SiNx waveguide dimensions and optical parameters, the polarization-dependent coupling efficiency of a single photon source with respect to the displacement from the waveguide edge facet, the horizontal and vertical positional variations, and the etching required to maximize and maintain the coupling efficiency values over the spectral range are discussed. [ABSTRACT FROM AUTHOR]

A study was made of a thermal interface based on a two-dimensional allotropic modification of carbon (graphene), presented in the form of a powder, for cooling integrated circuits. Such physical properties of the thermal interface as thermal conductivity, heat capacity, thermal diffusivity, and density are determined by the empirical method. The process of heat transfer in the most efficient thermal interface sample during the operation of integrated circuits in the ANSYS engineering analysis system is presented. The prospects of using pressed graphene powder as a thermal interface in order to eliminate the use of a binder are described. The paper also makes a comparison with the most effective type of thermal interfaces currently in use. [ABSTRACT FROM AUTHOR]

This review presents a distillation of important results published during 2009 in major journals and conference proceedings. Although the commercial promise of silicon photonics has not yet been realized, Group IV photonic science and technology continues to flourish in a remarkable variety of applications-areas discussed here. [ABSTRACT FROM AUTHOR]

This paper presents a theory for the power transfer efficiency of printed circuit board coils to integrated circuit coils, with focus on load-dependence for low-power single-chip systems. The theory is verified with electromagnetic simulations modelled on a 350 nm CMOS process which in turn are verified by measurements on manufactured integrated circuits. The power transfer efficiency is evaluated by on-chip rectification of a 151 MHz signal transmitted by a spiral coil on a printed circuit board at 10 mm of separation to an on-chip coil. Such an approach avoids the influence of off-chip parasitic elements such as bond wires, which would reduce the accuracy of the evaluation. It is found that there is a lower limit for the load below which reducing the power consumption of on-chip circuits yield no increase in voltage generated at the load. For the examined process technology, this limit appears to lie around 56 k Ω . The paper is focused on the analysis and verification of the theory behind this limit. We relate the results presented in this work to the application of wireless single-chip temperature monitoring of power semiconductors and conclude that such a system would be compatible with this limit. [ABSTRACT FROM AUTHOR]

The Boolean satisfiability (SAT) methods are one of the efficient approaches used to solve the problems of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, these methods demonstrate better results than the classic routing algorithms in terms of the speed of operation and the quality of the results. In this paper, the modern practice of using the SAT methods in computer-aided design systems for VLSI is analyzed. The examples of modern SAT approaches to the problems of routing and the formal equivalence checking of digital circuits' descriptions within the technological mapping as a part of the FPGA design flow are considered. The algorithm of the detailed routing of the FPGA switching blocks using the satisfiability problem is developed and presented. The results of its work are demonstrated on the example of the programmable logic block of the integrated circuit 5400TP094 made in Russia. The block has the island architecture, where the configurable logic blocks and switching blocks form a regularly repeated layout template. The properties of the chosen classic architecture allow us to expand the region of the presented algorithm to the entire class of island style of FPGA. The algorithm is tested on the project benchmarks ISCAS-85, ISCAS-89, and LGSynth-89. The comparison of the developed SAT-based algorithm with the well-known routing algorithm Pathfinder is presented by the criteria of the elapsed time and the achieved degree of routed nets in the switching blocks. It is specified that the considered Boolean satisfiability methods for the routing problem are capable to prove the circuit's unroutability, unlike the Pathfinder algorithm whose results can only implicitly indicate it. The paper demonstrates that the application of a more efficient SAT solver significantly accelerates the work of the suggested detailed routing algorithm. [ABSTRACT FROM AUTHOR]

The paper presents a mathematical apparatus based on the set-theoretic approach, which allows the prompt configuration of software routing within the design flow of user circuits in the basis of heterogeneous field-programmable gate array (FPGA) or reconfigurable system on a chip (SoC). The variety and interchangeability of technological and design solutions, the variety of forms and methods of routing resources programming for the implementation of user project nets entail the need to ensure quick adjustment of computer-aided design (CAD) tools for possible changes in the architecture of the basic (FPGA' or SoC's) chip. Taking into account this requirement, by means of the above mentioned mathematical apparatus, the paper provides a generalized description of the routing resources of a heterogeneous FPGA or a reconfigurable SoC, and formalizes the task of routing the nets of user designed circuits. One can also use the given formal descriptions during the analysis of the architectural solutions space within the design flow of problem-oriented heterogeneous FPGAs and reconfigurable SoCs. [ABSTRACT FROM AUTHOR]

In this paper, a new fundamental cell in positive feedback source coupled logic is presented, which is an improvement over the existing fundamental cell employed in digital circuit design in various high resolution mixed-signal integrated circuits. The operation of the existing fundamental cell relies on using large sized transistor in its centre branch, resulting in significantly larger implementation area. The proposed fundamental cell incorporates multi-threshold transistor in the center branch thereby allowing designer to use reduce its dimension and hence the area. The impact of the proposed modification is examined by configuring the cell as two input exclusive OR (XOR2) gate. The behaviour is analysed in terms of static and propagation delay parameters which are modelled and a design procedure is also elaborated. The theoretical prepositions are verified by designing and simulating for various operating conditions using model parameters of 180 nm CMOS technology node. A maximum error of 27% is observed between the simulated and predicted parameters. The process variation study through Monte Carlo analysis and PVT variations identifies the proposed fundamental cell based circuit as less prone to variations in comparison to existing fundamental cell based counterparts. A full adder, as an application of the proposed fundamental cell, shows a significant (66%) area reduction while delay, power and PDP are within 4% of their corresponding values for the existing one. [ABSTRACT FROM AUTHOR]

Pollution that comes from vehicles is the most significant cause in the ecosystem and is increasing every day. This leads to several environmental challenges, including global warming in which Plants and animals are affected significantly. The hybrid E-motorcycle (HE-M) is a technology that helps sort out these kinds of issues. Two or three power sources for complete rechargeable combustion are used in the hybrid electric motor. This paper used two independent electric power units: the drive unit and the integrated circuit (IC) motor unit. One power unit can be used up to 50–90 km from the electric drive and its eco-friendliness motor. It can be converted to an IC motor that makes the motorcycle more flexible, high-speed and long-distance operations. The initial motorcycle is fitted with continuous variable transmission. HE-M has been introduced to overcome the drawbacks and achieve high automatic mode performance. This paper consists of three HE-M modes, two energy management techniques applied, the HE-M servo motor control system and liquid crystal display monitor are addressed. Furthermore, road testing results explicitly demonstrate that the motor's pollutant emissions can be minimized at lower speeds or in operation causes and significantly enhanced by inadequate cruising space for electric motors. [ABSTRACT FROM AUTHOR]